Design of a microprocessor controlled data interface system
by Dennis Ivan Smith
A thesis submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE
in Electrical Engineering
Montana State University
© Copyright by Dennis Ivan Smith (1975)
Abstract:
The subject of this thesis is the design of a microprocessor controlled data interface system. The system
presented may be used as a remote data acquisition system or a type of industrial controller. Several of
these systems may be connected together to create a complex data collection system.
The system requirements and specifications are relatively few. After the specifications of the data bus
are given, several interface circuits are described. This is followed by a description of the controller
requirements. A microprocessor was chosen and a controller designed around it. The programming
techniques required by this specific system are presented as well as the operation of the entire system. STATEMENT OF PERMISSION TO COPY
In presenting th is thesis in p a r tia l f u lfillm e n t of the re q u ire ­
ments fo r an advanced degree a t Montana State U n iv e rs ity , I agree
th a t the Library shall make i t fr e e ly a v a ila b le fo r inspection.
I.
fu rth e r agree th a t permission fo r extensive copying, o f th is thesis
fo r scholarly purposes may be granted by my major professor, o r, in
his absence, by the D irecto r of L ib ra rie s .
I t is understood th a t
any copying or pu b licatio n on th is thesis fo r fin a n c ia l gain shall
not be allowed without my w ritte n permission.
Signature
Date
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DESIGN OF A MICROPROCESSOR CONTROLLED
DATA INTERFACE SYSTEM
by
DENNIS IVAN SMITH
A thesis submitted in p a r tia l f u lfillm e n t
o f.th e requirements fo r the degree
of
MASTER OF SCIENCE
in
E le c tric a l Engineering
Approved:
Head, Major Department
ChaIrman5 Examining Coptic tee
Graduate TDeah
7
/
MONTANA STATE UNIVERSITY
. Bozeman, Montana
June, 1975
iii
ACKNOWLEDGMENT
I
_
The design and development of the data in te rfa c e system pre­
sented in th is thesis has involved several in d iv id u a ls .
The w rite r
would e s p e cia lly lik e to thank Mr. Dick Weaver o f Western Tele­
computing Corporation o f Bozeman, Montana, fo r providing suggestions
fo r improving the o rig in a l design, and fo r designing several of the
in te rfa c e c ir c u its .
Of course, the author is e s p e cia lly g ratefu l
to Dr. Donald K. Weaver fo r his assistance and support o f the
p ro je c t.
D. I . S.
iv
TABLE OF CONTENTS
Chapter
V I T A . . . . ............................. ............................................. . . . . J . .
.
Page
..........
ii
ACKNOWLEDGMENT...................... ...................................... .......................... ............m
TABLE OF CONTENTS................... ........................ ............................ : . . . . .
....
iv
LIST OF TABLES.......................................... .............. .......................... ................ vi
LIST OF FIGURES...................... ................ ................ .......................................... v ii
ABSTRACT............................ ............ ............. .............. ................... ...................... vi i i
I.
INTR O D U CTIO N ................. ......................................................
I
Background................ ........................................................... .................... . I
Organization o f Chapters .............................. ........ . . . . ___ . . .
II.
III.
4.5
DESCRIPTION OF THE SYSTEM B U S . . . . . . . . . . . . . ...........
Description of the System Bus Lines...... .............................
5
Description of the Data Transfer O p eratio n ............................ .
7
INTERFACE CIRCUITS.,....................................
H
Counter-Tim er..............................................
11
Memory............................................................ .................................. .......... ie
S e ria l Output............................................................................ ..
IV . SYSTEM CONTROLLER.. . . ' ..........................
13
20
Control I er Requi rements......................................................................20
Microprocessor Requirements...................................
22
In te l 8008 Microprocessor D e s c r ip t i o n . ... ..................... .......... 23
Description of the Microprocessor C o n tro lle r...........
26
V
Chapter
V.
'
Page
DESCRIPTION OF THE MICROPROCESSOR CONTROLLED SYSTEM............... 40
System C onfiguration...........................
.40
Program Considerations..........................................................
40
Operation of the System.............................................. i ..................... 43
V I.
CONCLUSION......................................................................
REFERENCES...........................................................................................
46
49
LIST OF TABLES
,Page
Table I .
Sample System Configuration
....
41
'
.
:
V ii
. -
■
LIST OF FIGURES
’
'
n
Page
Figure I .
Bus Timing D ia g r a m ...............................................
Figure 2.
Counter-Timer C irc u it:
, C ounter..............................
12
Figure 3.
Counter-Timer C irc u it:
T im e r ............................
13
Figure 4.
Counter-Timer C irc u it:
Control. . . . . . . . . . . . . . . . . .
15
Figure 5.
...C o n tro lle r Block Diagram. .. . . . . . . . . . . . . . — . . . . . .
27
Figure 6.
.C o n tro lle r C irc u it:
Figure 7.
C o n tro lle r C irc u it:
Figure 8.
C o n tro lle r C ir c u it : - D e c o d e r .................
34
Figure 9,
C o n tro lle r C irc u it;
Channel S e l e c t . . J . . . . . . . . . . .
35.
Figure 10.
C o n tro lle r C irc u it:
Transfer C o n t r o l...............
36
Figure 11.
C o n tro lle r C irc u it:
Status Input & Bus D riv e rs ..
37
Figure 12.
C o n tro lle r C irc u it:
Front Panel Control . . . . . . . . .
38
Figure 13.
C o n tro lle r C irc u it:
Front Panel Address Register
39,
Figure 14.
8
I nput . . . . . . . . . . . . . . . 3 2
C P U , . . . ..............................
33
Sample Data Transfer Program Segment. ^. . . ---------... 44
viii
ABSTRACT
The subject of th is thesis is the design o f a microprocessor
contro lled data in te rfa c e system. The system presented may be used
as a remote data a c q u is itio n system or a type of in d u s tria l con­
tr o lle r .
Several of these systems may be connected together to
create a complex data c o lle c tio n system.
. The system requirements and s p e c ific a tio n s are r e la t iv e ly few.
A fte r the s p e c ific a tio n s o f the data bus are given, several in t e r ­
face c ir c u its are described. This is followed by a description of
the c o n tro lle r requirements. A microprocessor was chosen and a
c o n tro lle r designed around i t .
The programming techniques required,
by th is , s p e c ific system are presented as w ell as the operation of
the e n tire system.
CHAPTER I
INTRODUCTION
A data in te rfa c e system is a term ascribed to various systems
capable o f obtaining inform ation or data from various devices, such
as instruments, sensors, transducers, or computer type memory, and
routing th is data to other devices, such as another memory or a
te le p r in te r .
Exactly how the data are obtained and where they are
routed is dependent on the c h a ra c te ris tic s o f a given systems.
In
one system, the data may be stored in memory fo r la t e r use while other
systems may require immediate use o f the data, in which case the data
would be routed to the w aiting device immediately.
The complexity
of the system is dependent on the number and p a rtic u la r types of
devices in terfa c ed to i t as well as the complexity of the c o n tro lle r.
This data in te rfa c e system has been designed to provide an
economical data a c q u is itio n system or a. control u n it.
One p a r tic ­
u la r requirement met by including a microprocessor in the c o n tro lle r
is th a t o f including the a b i l i t y to e a s ily preprocess raw data from
the in te rfa c e c ir c u its before sending them to an external device.
BACKGROUND
Many systems have been developed th a t could be c la s s ifie d as
data in te rfa c e systems.
Computers could be c la s s ifie d as such since
they in te rfa c e memory to external p erip h era ls .
This in te rfa c e may
2
be through the central processor or. through such schemes as d ire c t
memory access or separate I/O processors used in conjunction with
m u lti-p o rt memory.
Data a c q u isitio n systems could also be c la s s i­
fie d as data in te rfa c e systems since they in te rfa c e transducers and
■:
sensors to meters, counters, recorders, e tc .
The data in te rfa c e system described in th is thesis has evolved
from previous data a c q u is itio n systems and present techniques, of
d i g it a ll y bussing data through a system.
The i n i t i a l ob jective of
th is p ro je c t was to update and replace the present data acquisition .
system a t Spring Creek.
p a rtic u la r system.
Refer to William s (6) fo r a report on th a t
That system was designed to measure various .
weather and stream parameters along Spring Creek and to transm it the
corresponding data back to Montana S tate U niversity using telephone
lin e s .
The system was remotely contro lled by an HP2115A minicomputer
located in a laboratory a t MSU.
A ll conversions of the raw data to
reasonable units took place in the computer.
The design of th is data
a c q u is itio n system made i t very d i f f i c u l t to allow the computer to do
much more than i n i t i a t e the transmission o f the current data..
The
control program in the computer in it ia t e d the system p e rio d ic a lly
to c o lle c t the data and store i t in memory.
When not c o lle c tin g data,
the program would enable a user to c a ll the computer and access the
data stored in memory.
The data th a t could have been collected
between system in it ia t io n s were lo s t.
I f the data could be collected .
3
continuously and preprocessed on s it e , the computer's program could
be made more f le x ib le as to when to access the system.
could then be allowed, to access several systems.
The computer
Many o f these fac­
tors prompted the development o f a new data a c q u isitio n system.
Several types of system a rc h ite c tu re were in vestig ated as
possible structures fo r the new system.
The a rc h ite c tu re most
applicable to the i n i t i a l system requirements was a bus oriented
s tru c tu re .
The Register Transfer Modules, designed and manufactured
by the D ig ita l Equipment Corporation ( I ) , and the standard in s tru ­
ment in te rfa c e system proposed by the In te rn a tio n a l E lectrotechnical
Commission (3 ) were in v e s tig a te d .. The re s u ltin g system is s im ila r in
many respects to each system.
The Register Transfer Modules use a
sixteen b i t data bus in conjunction with a fiv e b it control bus.
Control is re a liz e d by a hardwired program using evoke modules or by
a microprogrammed c o n tro lle r.
The In te rn a tio n a l E lectrotechnical
Commission's system u t iliz e s an e ig h t b i t data bus, a fiv e b it
management bus, and a three b it handshake bus.
The control functions
are performed by one o f the instruments connected to the bus.
Commands
are transm itted in the same manner th a t data are transm itted.
A bus organization was developed by combining several features
of both o f the above systems.
This organ izatio n , described in
Smith ( 4 ) , used an e ig h t b it data bus, a six b it control bus, and four
nonbussed lin e s to each channel.
Western Telecomputing Corporation
4
made several additions and changes to th is i n i t i a l bus organization
to use in one o f t h e ir new product lin e s -c a lle d the WTC Data In te r ­
face System.
This modified organization was used in th is thesis
because i t was both convenient and fu n c tio n a lly adequate to. do so.
This bus organization uses an e ig h t b it data bus, an eleven b it
control bus, and two non-bussed control lin e s to each channel.
i n i t i a l design lim its th is system to sixteen channels.
The
Each channel
may have the c a p a b ility o f being both a source and a destinatio n fo r
data tra n s fe rs .
Like the Register Transfer Modules, there is only
one channel acting as the source and one channel acting as the des­
tin a tio n fo r each tra n s fe r.
Control is re a liz e d by a cen tralize d
system c o n tro lle r which may range from a c o n tro lle r with a hard­
wired sequence o f commands to a microprocessor based c o n tro lle r.
With the microprocessor c o n tro lle r, data may be preprocessed before
being transm itted to the external world.
ORGANIZATION OF CHAPTERS
.
This thesis w i l l discuss in g reater d e ta il the various aspects
and parts of the data in te rfa c e system.
Chapter I I w ill cover the
bus lin e s arid the data tra n s fe r sequences.
The descriptio n of several
in te rfa c e c ir u c its is contained in Chapter I I I .
C o n tro lle r develop­
ment fo r the system w ill be covered in Chapter IV w ith a look a t the
o v e rall system in Chapter V.
CHAPTER I I
DESCRIPTION OF THE SYSTEM BUS
This chapter presents a description of the system bus lines
and the sequence of signals necessary to perform the data tra n s fe rs .
DESCRIPTION OF THE SYSTEM BUS LINES
Several lin e s are necessary to control the tra n s fe r of data
between channels.
Eleven bussed Tines control the tra n s fe r operations.
Two nonbussed lin e s from the c o n tro lle r to each o f the sixteen channels
s e le c t which channels are to p a rtic ip a te in the data tra n s fe rs .
data is tran s fe rred via a b id ire c tio n a l e ig h t b it data bus.
The
A ll the
lin e s are ground tru e to allow OR operations using open c o lle c to r TTL.
Lines DB0 - DB? (Data Bus) form the e ig h t b it data bus.
Any
channel can be selected as the data source or the data d e stin atio n .
The selected source channel puts data on the bus, and the destinatio n
channel loads the data from the bus in to one o f it s in te rn a l re g is te rs .
A lte rn a tiv e ly , the c o n tro lle r may also a c t as e ith e r the source or the
d e s tin a tio n .
A fte r the c o n tro lle r has-determined the source and destination
channels, a single b y te .(e ig h t b its ) tra n s fe r is performed using the
EDT, DAV, and DAC lin e s .
The c o n tro lle r sets the EDT (Enable Data
Transfer) lin e tru e to i n i t i a t e the operation.
The selected source
then places e ig h t b its of data on the data bus and sets DAV (Data
6
A v a ila b le ) tru e .
When the d estinatio n detects th a t DAV has gone
tru e , i t tran sfers the data to it s re g is te r and sets DAC (Data
Accepted) tru e .
The c o n tro lle r then sets EDT fa ls e , which in turn
causes the source and destination channels to set DAV and DAC fa ls e
re s p e c tiv e ly .
G enerally, a source transmits a s trin g of bytes to the destinatio n
and the handshake described above is performed fo r each byte.
Nor­
m ally the source determines how many bytes are to be tran s fe rred .
The end of the byte s trin g is usually indicated by s e ttin g the SKP
(SKiP) lin e tru e .
The SKP lin e may also be set true by the des­
tin a tio n to in d ic a te th a t i t cannot accept fu rth e r data.
I f the
c o n tro lle r is programmable, i t may use the SKP lin e fo r conditional
branching.
Two o f the bus lin e s , SC0 and SCI (Source Channel) , are used .to
address one of four possible separate source re g is te rs or to se le c t
one of four possible operating modes.
The source may o p tio n a lly ig ­
nore these lin e s or use them in any way th a t would improve the use­
fulness of the channel.
Two other bus lin e s , DC0 and DCl (Destina­
tio n Channel ) , s im ila r ly control a d e s tin a tio n .
One o f four des­
tin a tio n s or one of four modes of operation can be selected.
Any channel can .request service by S e ttin g SRQ (S e rv ic e .ReQuest )
tru e .
This lin e is OR tie d to enable several channels to request
service simultaneously.
To service the request, the c o n tro lle r sets
7
ESC (Enable Status Check) tru e .
This converts a ll the individual
SSC and SDC lin e s (described below) in to status lin e s to the con­
tr o lle r .
This allows the c o n tro lle r to id e n tify which channels
requested servicing and to take the appropriate actio n .
The remaining bussed lin e is the RST (R eSet). lin e .
When th is
lin e is set true by the c o n tro lle r, a ll the channels are placed in to
a known s ta te .
This is done when the system is s tarted or when
recovering from a power fa ilu r e .
The SSC (S e le c t Source Channel) and SDC (S elect Destination
Channel) lin e s are riot p a rt of the bus s tru c tu re , but are individual
lin e s from the c o n tro lle r to each channel.
These Tines are used by
the c o n tr o lle r to s e le c t the data source and destin atio n channels
fo r the data tra n s fe rs , and to bring status from the channels to the
c o n tro lle r when ESC is tru e .
DESCRIPTION OF THE DATA TRANSFER OPERATION
Several operations occur.simultaneously during each byte trans­
fe r .
The follow ing paragraphs describe the e ffe c t of the bus Tines
on the source and d estinatio n channels as well as the e ffe c ts on the
c o n tro lle r.
A tim ing diagram fo r the bus lin es involved in a byte
tra n s fe r is given in Figure I .
I f the source is ready to transm it data, i t w i l l set it s SSC
lin e true when i t detects th a t ESC is tru e .
When both the channel's
8
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FSC ~
X
pw
SS f
SDc
CDT
X
y
Ul
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Il n
n n
Ji__ji__
in_ n
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Pa V
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Figure I .
Bus Timing Diagram
L
IT
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9
SSC and the EDT lin e s are tru e , the source re g is te r selected by SC0
and SCI w i l l place it s data on the bus.
A fte r an appropriate delay
to allow the data to s e ttle on the bus, DAV is set true to indicate
th a t the source has placed it s data on the bus.
When EDT goes fa ls e
s ig n a llin g the end of the byte tra n s fe r, DAV is set fa ls e and the
data is removed from the bus.
On the tra n s fe r of the la s t byte,
SKP is set true during the same in te rv a l th a t v a lid data is placed
on the bus.
I f the destin atio n is ready to accept data, i t w ill set it s SDC
lin e tru e when i t detects th a t ESC is tru e .
When both the channel's
SDC and EDT lin e s are tru e , the destinatio n re g is te r selected by
DC0 and DCl w ill be loaded with the data from the data bus when the
destin atio n channel detects th a t DAV has gone tru e .
Concurrent with
the tra n s fe r from the bus to a r e g is te r, DAC w ill be set true to
in d ic a te th a t the destinatio n has accepted the data from the bus. .
When EDT goes fa ls e a t the end of a tra n s fe r, the destinatio n sets
DAC fa ls e .
I f the destinatio n cannot accept any more data, i t w ill
set SKP true when i t accepts it s l a s t possible byte.
This feature
must be included in several channels to prevent the destinatio n from
"hanging up" the system.
The c o n tro lle r checks the readiness o f the channels by settin g
ESC true and checking the in divid ual SSC and SDC lin e s .
SC0, SCI,
DC0, and DCl may be used to check the status of any o f the four
10
re g is te rs of each source and d estin atio n s.
To enable a byte tra n s fe r
the c o n tro lle r selects the desired channels by s e ttin g the appro­
p ria te SSC, SDC, SC0, SCI, DC0 and DCl lin e s .
i n i t i a t e the tra n s fe r.
EDT is set true to
When DAC is set true by the d e s tin a tio n , the
c o n tro lle r responds by s e ttin g EDT fa ls e .
CHAPTER I I I
INTERFACE CIRCUITS
This chapter describes several of the in te rfa c e c irc u its th a t
have been designed fo r the system.
The f i r s t c ir c u it , the counter-
tim e r, w i l l be described in greater d e ta il than the subsequent
c ir c u its since the handshake and bus in te rfa c e c ir c u its are
e s s e n tia lly the same fo r a ll the c ir c u its and.are of primary in te re s t
in th is chapter.
COUNTER-TIMER
This in te rfa c e c ir c u it contains both an event counter and an
in te rv a l tim er.
The event counter advances one count whenever an
input pulse is received from an external source, such as a d ig ita l
anemometer.
The in te rv a l tim er measures the time in te rv a l between
any two consecutive pulses.
In the case o f the anemometer,,the coun­
te r w i l l hold the wind flo w , and the tim er w ill hold the reciprocal
o f the wind speed.
•
The counter portion of the c ir c u it , shown in Figure 2, is a four
d ig it decade counter.
Whenever the data in te rfa c e system wants to
access it s contents, the count is latched in to T r i-s ta te latches, which
.
■
'
■
V
each place th e ir d ig its onto the bus in tu rn , the most s ig n ific a n t
digit fir s t.
The tim e r, shown in Figure 3, is much the same as the counter,
12
LATCH
74-151
O e l> u i/ n c # d \
L A TC h
Pulse
CU M A/
Gl 61(i
Figure 2.
Counter-Timer C irc u it:
Counter
13
lT r
61 B
A 7 W
(i Cia
P------T 3 ------------
Figure 3.
Counter-Timer C irc u it:
Timer
14
except an in te rn a l clock is counted.
When an input pulse is received
the time counter contents are latched, the counter cleared , and
counting is resumed.
When the tim er is accessed by the system, the
contents of the latches are latched in T r i -s ta te latch es, which place
th e ir d ig its on the bus in tu rn , the most s ig n ific a n t d ig it f i r s t .
Provisions are included to in h ib it fu rth e r counting when the four
d ig it decade counter overflows.
Overflow is indicated by a 0000
output.
The control po rtion o f th is in te rfa c e performs several func­
tio n s .
I t must control whether the counter or the. tim er is to place
data on the bus, id e n tify which one is to be accessed, and f i l l out
the d ig its from e ith e r to form ASCII characters.
The control wi l l
always in d ic a te th a t i t is ready to transm it data whenever i t is
in terrogated by the ESC lin e .
the tim er.
SC0 is used to s e le c t the counter or
SC0 is fa ls e fo r the counter and true fo r the tim er.
When the system requests th a t the channel transm it it s data, the
control f i r s t sends an id e n tify in g ASCII alphabetic character.
This
character is selected by in s e rtin g jumper diodes in to the appropriate
places of the c ir c u it as shown in Figure 4.
Then the four ASCII
decimal d ig its are tran sm itted , the most s ig n ific a n t d i g it f i r s t .
Concurrent with the la s t d i g it , SKP is set true to signal the end
o f the byte s trin g .
SSC and EDT are ANDed together to detect when
the system is requesting it s data.
This signal is used to enable
15
c?
Cl
Cl
C0
T?
Tl
Tl
TO
Dj
Oi
Dl
Dff1
Figure 4.
Counter-Timer C irc u it:
Control
16
bus d riv e rs , and to advance the character counter.
A delayed signal
is used fo r DAV to allow the data to s e ttle on the bus.
This in t e r ­
face c ir c u it does not use SRQ since very vew circumstances require
An in te rfa c e c ir c u it very s im ila r to the above counter-tim er
is the quad counter.
This in te rfa c e has four event counters.
Oper­
a tio n is id e n tic a l to the counter portion of the counter-tim er.
The
control portion is much the same except th a t one of four sources
must be selected and id e n tifie d ra th e r than one. of two.
MEMORY
Memory is used in th is data in te rfa c e system fo r both data
storage and control program storage.
I t is most e a s ily implemented
in m u ltip les o f 256 bytes since the data bus is e ig h t b its wide.
However, i t is assumed here and in subsequent chapters to be 4096
bytes per channel.
This allows s u ffic ie n t space fo r a r e la tiv e ly
complex control program as well as some data storage space.
Besides
being able to access the contents of the memory, i t is necessary to
specify which p a rtic u la r byte is to be accessed.
re g is te r is included to accomodate th is .
A twelve b it address
When.using the memory fo r
data storage, i t is convenient to keep track of how many bytes have
been stored and where the next byte is to be stored.
A byte counter
and an auto-increment address re g is te r are included to accomodate
th is fe a tu re .
17
. The DC0 and DCT Tines are used to s e le c t the memory, the address
re g is te r, or the byte counter as the d e s tin a tio n .
and DCl tru e to s e le c t the address re g is te r.
DC0 is set fa ls e
Since 4096
bytes re ­
quire twelve b its o f address, two bytes must be received to completely
specify the address.
The f i r s t byte contains the highest four b its
and the second byte the lower e ig h t b its .
f i r s t byte are ignored.
both DC0 and DCl tru e .
The higher four b its of the
The byte counter is accessed by se ttin g
This allows the counter to be set p rio r to
reading from memory when in the data dump mode**.
has two possible modes.
Actual memory access
The.mode used by the c o n tro lle r fo r it s
normal memory w rite operations is selected by s e ttin g both DC0 and
DCl fa ls e .
N either the address re g is te r nor the byte counter is
a lte re d in th is mode.
The other mode, selected by s e ttin g SC0 true
and SCI fa ls e , is used when storing a s trin g of bytes in memory from
one o f the other system channels.
Both the address re g is te r and the
byte counter are incremented by one count fo r each byte stored.
Simi I ary, SC0 and SCI are used to se le c t the memory, the address
re g is te r, or the byte counter as the source.
SCI true to se le c t the address re g is te r.
as two bytes.
The address is transm itted
The higher four b its o f the f i r s t byte are set to 0
since they are not used in the actual address.
the second byte.
counter.
SC0 is Set fa ls e and
SKP is set true on .
Both SC0 and SCI are set true to access the byte
As in the destinatio n mode, there are two modes o f memory
18
access in the source mode.
For normal memory read accesses by the
c o n tr o lle r, both SC0 and SCI are set fa'lse.
The other mode, selected
by s e ttin g SC0 true and SCI fa ls e , is used when dumping stored data
to another channel.
The address re g is te r is incremented and the byte
counter decremented fo r each byte accessed.
SKP is set true when
the byte counter returns to zero.
SERIAL OUTPUT
The s e ria l output in te rfa c e designed by Western Telecomputing
Corporation (5) in terfa c es EIA RS 232C compatible modems and s e ria l
p rin te rs to the data in te rfa c e system.
Ground true TTL compatible
and twenty m illiampere compatible outputs are a v a ila b le in addition
to the EIA le v e ls .
There is one c o n tro l-o u t s ig n a l, one c o n tro l-in
s ig n a l, and the s e ria l character data output lin e on the external side
of the in te rfa c e .
The data from the in te rfa c e are transm itted in
b it s e ria l form on the data output lin e .
the bus are always transm itted.
The lower seven b its from
There are several options
selected by jumpers fo r the eighth b it .
This b it may be the even or
odd p a rity b it of the lower seven b its , a mark, a space, or the eighth
b it from the bus (DB?).
E ith e r one or two stop b its are transm itted,
depending on another jumper of the in te rfa c e .
Several d iffe r e n t data
.
.
.
'
rates may be selected by y e t another jumper and the choice of two
clock c rys ta l frequencies.
The c o n tro l-o u t lin e may be used to
19 . . .
control a modem c a r r ie r or a p r in te r motor.
The c o n tro l-in lin e
is used to enable the transmission o f data from the in te rfa c e and
to control some o f the in te rfa c e operations.
This in te rfa c e operates only as a destination channel.
E ith er
the control r e g is te r .o r the data re g is te r may be addressed during a
byte tra n s fe r by using DC0.
re g is te r.
DB0 sets the c o n tro l-o u t lin e , 0 turning i t o f f and I
turning i t on.
channel.
DC0 is set true to set the control
DB! is used to control the RQS operation o f the
DB! is 0 to enable the operation and I to in h ib it i t .
remaining s ix b its are ignored.
The
A data byte can be placed in the
data re g is te r by s e ttin g DC0 fa ls e during a byte tra n s fe r to th is
channel.
The handshake w ill be completed when the transmission of
the previous character has been completed and the c o n tro l-in lin e is
on.
During a status check by the ESC lin e , th is channel's SDC lin e
w i l l be fa ls e i f the channel is busy tran sm ittin g a character or the
c o n tro l-in lin e is o f f .
I t w ill be tru e only when the channel is
ready to accept another character and the c o n tro l-in lin e is on.
RQS
w ill be set tru e , i f enabled by the control b it described above, when
the c o n tro l-in lin e is on and the channel is not tran s m ittin g a charac
te r .
The RST lin e w i l l set the control re g is te r so th a t the c o n tro l-
out lin e is o f f and the RQS operation is enabled.
CHAPTER IV
SYSTEM CONTROLLER
This chapter presents a description of the basic requirements
of the system c o n tro lle r and the minimum, requirements f o r . a microprocessor to be used in a complex c o n tro lle r.
A microprocessor th a t
f i t s these requirements was selected and designed in to a system
c o n tro lle r.
CONTROLLER REQUIREMENTS
The system c o n tro lle r is in charge o f a ll data tran sfers per­
formed on the bus.
As described in Chapter I I , th e c o n tro lle r
in it ia t e s and terminates each data tra n s fe r sequence.
The status
of each channel is used by the c o n tro lle r to decide which course
o f action i t should fo llo w .
One of the simplest c o n tro lle rs is one in which a s trin g of data
bytes is transm itted upon re c e ip t of a SRQ s ig n al.
One p a ir of.
channels tra n s fe r a s trin g o f bytes u n til the SKP lin e is set true
by the source.
Then another, p a ir of channels tra n s fe r another u n til
'
SKP becomes true again.
'•
. ,
•
-
Upon re c e ip t of the l a s t SKP s ig n a l, the
system enters an id le state u n til the next SRQ signal is .d e te c te d .
When SRQ is received again, the above sequence is repeated.
The
sequence of the pairs o f channels p a rtic ip a tin g in the data tran sfers
can be modified by changing jumpers in the c o n tro lle r.
This con-
21
t r o l l er does not check the status of the in divid ual channels, but
depends on the fa c t th a t the tra n s fe r handshake sequence wi l l be
completed only when both the source and destinatio n channels are
ready to do so.
A.more sophisticated c o n tro lle r contains a microprocessor which
chooses.its course of action on the basis of the in stru ctio n s of the
control program.
These in stru ctio n s d ire c t the c o n tro lle r to check
s ta tu s , i n i t i a t e data tra n s fe rs , and process the data c o lle cte d ,
the control program w i l l be located in a memory located e ith e r in one
of the system channels or in the c o n tro lle r.
In most cases, the
speed of the system w i l l be lim ite d by the speed of the microprocessor
I f the control program memory is located in one o f the system channels
in s tru c tio n fetching may be s lig h t ly slower than i f the program
memory was located in the c o n tro lle r.
However, the memory located
in one o f the system channels should be more general purpose since
i t could also be used fo r data storage using channel to channel
tra n s fe rs .
Using, the memory described in Chapter I I I ,
the in s tru c tio n fetch
or memory read operation would be executed as follow s.
The memory
address would be sent to the memory channel address r e g is te r, the
highest four b its f i r s t followed by the lower e ig h t b i t s .
Then the
contents of the addressed memory lo catio n would be sent from the
memory channel to the c o n tro lle r.
22
The memory w rite operation would be executed as follow s.
The
memory address would be sent to the memory channel address r e g i s t e r ,
in the same way i t was sent fo r the memory read operation.
Then the
data to be stored in the addressed lo catio n would be sent from the
c o n tro lle r to the memory channel.
Data tran sfers between channels are enabled during the exe­
cution o f p a rtic u la r in s tru c tio n s , usually c e rta in I/O in stru c tio n s .
Under normal operation, only one byte may be tran sferred per single,
execution of these in s tru c tio n s .
There would usually be a few
in s tru c tio n fetch operations between data byte tran sfers between
channels.
I f the destinatio n channel or the source channel is one. of
the memory channels, i t should be a d iffe r e n t channel than the one
in stru c tio n s are c u rre n tly being fetched from since the fetch
operation would change the address re g is te r i f they were both access-,
ing the same channel.
MICROPROCESSOR REQUIREMENTS
The c o n tro lle r must be designed so the microprocessor can fetch
it s in stru ctio n s from a memory channel, store data in a memory channel
and enable byte transfers, between channels.
Since the data bus is
e ig h t b its wide, i t is only lo g ic a l th a t the microprocessor u t i liz e
in stru ctio n s and data th a t are e ig h t b its wide.
To allow enough
programming space fo r r e la t iv e ly complex.programs, and to be com­
23
p a tib le with the memory presented in Chapter I I I , the microprocessor
must be capable of addressing a t le a s t 4096 bytes o f memory.
The
in s tru c tio n set should be capable of allowing a r e la t iv e ly complex
program to be e a s ily re a liz e d .
There should be a set of p a rtic u la r
in stru c tio n s to be used to set up and enable tran sfers between system
channels.
Since the time required to access memory depends on the speed
of the handshake, sequences, which may vary considerably, the processor
.
should have the c a p a b ility of being held in an i d l e s ta te u n til the
operation being executed is completed.
The in s tru c tio n execution
time should be short enough to allow the system to respond ra p id ly
to any condition th a t needs immediate a tte n tio n .
INTEL 8008 MICROPROCESSOR DESCRIPTION
The In te l 8008 microprocessor, described in d e ta il in In te l ( 2 ) ,
is the le a s t expensive processor th a t f u l f i l l s the requirements fo r
the system c o n tro lle r.
I t is an e ig h t b it processor with fo rty -e ig h t
data oriented in s tru c tio n s .
o f memory.
It.c a n be used with any type and speed
An address of fourteen b its allows addressing of up to
16,384 bytes of memory.
By using the 1/0 in s tru c tio n s , a data tran s ­
fe r between channels can e a s ily be set up and executed.
cycle time fo r the 8008 is twenty microseconds.
The basic
A fa s te r version,
the 8008-1, has a basic cycle time o f twelve and one h a lf micro­
24
seconds.
deep.
An in te rn a l stack allows nesting subroutines up to seven
Seven re g is te rs are accessable by the program.
One of these
is the accumulator while the other s ix are used fo r temporary data
storage^
,
The processor communicates via an eigh t b it b id ire c tio n a l bus.
Time m ultiplexing of the bus allows control inform ation, fourteen
b i t addresses, and data to be tran sferred between the processor and
external c ir c u its .
Besides.two inputs fo r the two phase non-over-
'
lapping clock, two inputs and four outputs are used fo r processor
c o n tro l.
The sta te outputs (SO, S I, and 52) and the SYNC output
in d ic a te the sta te the processor is in during in s tru c tio n cycles.
The READY lin e is used to hold the processor in an id le state u n til
i t is set tru e .
The 8008 has lim ite d in te rru p t c a p a b ility through
the use of it s INTERRUPT input.
Due. to the r e la tiv e d i f f i c u lt y of
saving the s ta te of the processor during in te rru p t s e rv ic in g , i t is
usually not used except when i n i t i a l l y s ta rtin g execution of the
program.
There are e ig h t states the processor may e n te r. . Five of these
are entered during the normal execution of a ty p ic a l in s tru c tio n .
The lower byte of the address is transm itted during s ta te T l.
The
higher six b its of the address and two control b its are transm itted
during T2.
The two control b its designate what type of in stru ctio n
cycle is being executed.
Both D6 and D7 are 0 fo r the in stru c tio n
25
fe tch cycle.
D6 is O and D7 is I fo r cycles in which addition al bytes
of data or address are fetched from memory.
fo r the memory w rite cycle.
cution cycle.
Both D6 and D7 are I
D6 is I and D7 is 0 fo r the I/O exe­
For the I/O cycle, the contents of the accumulator
is transm itted during T l.
The lower s ix b its of the byte tran s-, .
niitted during T2 contain the I/O device address and specify whether
the in s tru c tio n is an input or output in s tru c tio n .
During T3, the
data from memory or ah input device is received by the processor,
or the data to be stored in memory is transm itted by the processor.
Execution of the in stru ctio n s occurs during states T4 and T5.
in stru ctio n s w ill skip one or both of these la s t s ta te s .
Some
State Tl
is replaced by Tl I when the processor has been in terru p ted to in - .
dicate to the external c ir c u itr y th a t the in te rru p t has been recog­
nized.
This is usually used to signal the c ir c u itr y to jam an in - .
s tru c tio n in to the processor to replace the in s tru c tio n normally
fetched from memory.
The program counter is not advanced during a
cycle beginning with sta te Tl I .
The processor w ill enter state
WAIT immediately a f t e r T2 i f the READY lin e is low.
The processor
w ill remain in WAIT u n til READY is set high, enabling the processor
to enter T3. . The STOPPED state is entered a fte r sta te T3 when a
HALT in s tru c tio n has been received by the processor.
26
DESCRIPTION OF THE MICROPROCESSOR CONTROLLER
B a s ic a lly , the configuration o f the system with a microprocessor
c o n tro lle r is th a t of a simple computer.
In structio ns are fetched
from memory and executed, data is w ritte n in memory, and data trans­
fe rs are set up and executed.
To re a liz e a c o n tro lle r with the In te l 8008, the time m u lti­
plexed data on the processor's bus must be demultiplexed so th a t i t
can be used a t the system's speed, which w ill be qu ite d iffe r e n t
than the speed of the processor.
C irc u itry must also be included to
allow the input data from the bus, status re g is te rs , or in te rru p t
in s tru c tio n re g is te r to be received by the processor during T3.
The
byte transm itted by the processor during T2 is latched and decoded,
to determine what type of cycle is being executed.
The follow ing
paragraphs describe the operations of the d iffe r e n t cycles as
executed by the design shown in the block diagram of Figure 5.
The
schematic diagram is Figures 6 through 12.
The Tl latch contains the low byte of the memory address fo r the
in s tru c tio n fetch or memory read cycle.
The T2 latch contains the
higher s ix b its of the memory address.
The highest two b its of the
address are used to s e le c t one of the f i r s t four system channels
as the destinatio n fo r the next two tran sfers and the source fo r the
th ird tra n s fe r.
The higher address byte is tran sferred from the T2
la tc h f i r s t , followed by the lower address byte from the Tl la tc h .
27
06 0-7
Df(Z)-T
-If
SfC
0n-if fDc
Iv r* AM
DK* AD*
—
AM
SVlTfHfI
LtMt AD*
LtMD AlM---
Figure 5.
FtOVT
PAVfL
AbDAfif
J
KfGHTtR
DATAl
C o n tro lle r Block Diagram
28
Then the selected channel is instructed to transm it the contents of
the addressed memory lo catio n to the c o n tro lle r.
in the INPUT la tc h .
This byte is latched
The contents of th is latch are tran sferred a t
the proper time to the processor fo r in s tru c tio n decoding and
execution.
The Tl la tc h also contains the low byte of the memory address
fo r the memory w rite cycle.
of the address.
The T2 la tc h contains the higher six b its
The highest two b its o f the address are used to
s e le c t one o f the f i r s t four system channels as the destinatio n fo r
the next three tra n s fe rs .
The higher address byte is tran sferred
f i r s t from the T2 la tc h followed by the lower address byte from the
Tl la tc h ,
then the data byte contained in the T3 la tc h is trans­
fe rre d .
For the I/O in s tru c tio n s , the T2 la tc h contains the device
address and an in d ic a tio n of whether an IN or OUT in s tru c tio n is
being executed.
The contents of the Tl la tc h are the same as the
contents o f the processor's accumulator.
The device address and the
type of in s tru c tio n determine how the c o n tro lle r executes the I/O
in s tru c tio n .
An OUT IOB (the B indicates octal or base eight numbers)
in s tru c tio n w ill cause the contents of the Tl latch to be stored in
the XFER SSC la tc h .
This la tc h is used to se le c t the source channel
during a tra n s fe r between channels.
I f the highest b it is tru e , the
c o n tro lle r is specified to be the source channel.
An OUT IlB Tnstruc-
29
tio n w ill cause the contents o f the Tl la tc h to be stored in the
XFER SDC latch, which is used to s e le c t the d estinatio n channel during
a tra n s fe r between channels.
I f the highest b it is tru e , the con­
t r o l l e r is sp e c ifie d to be the d e s tin atio n channel-
An IN 0 in s tru c ­
tio n enables the tra n s fe r of a data byte; between the source and
destin atio n channels specified by the la s t OUT IOB and OUT IlB
in s tru c tio n s .
I f the c o n tro lle r is sp ecified to be the source
channel, the contents o f the Tl la tc h are placed bn the data,bus.
When the byte has been tra n s fe rre d , SKP is latched in to the SRQ/SKP
la tc h and the data byte latched in the INPUT la tc h .
The contents
o f the INPUT la tc h are then transm itted to the processor's accumulator.
The IN I in s tru c tio n is id e n tic a l to the IN 0 in s tru c tio n except th a t
SKP is not latched.
The IN 2 in s tru c tio n is used to load the status
of the channels in to .th e processor's accumulator.
The contents of the
Tl la tc h are used to s e le c t which e ig h t channels are to have th e ir
status sent to the processor.
The IN 3 in s tru c tio n causes the con­
tents o f the SRQ/SKP la tc h to be sent to the processor's accumulator.
In order fo r th is c o n tro lle r to be u s e fu l, several operator
controls must be provided.
An operator should be able to s ta r t and
stop the execution o f the control program.
Also, he should be able
to examine and a lt e r the contents of the program memory.. This design
provides these co n tro ls.
30
Wheri the RUN/STOP switch is operated, an in te rru p t request is
sent to the processor.
I f the processor was stopped, a .RST 0 in s tru c ­
tio n is sent to the processor during the in te rru p t cycle to s ta r t the
execution of the program a t address 00000B.
Whenever the processor
is s ta rte d , the fro n t panel address re g is te r is cleared.
I f th e ,.
processor was executing the program when the RUN/STOP switch was
operated, a HALT in s tru c tio n w ill be sent to the processor during the
in te rru p t cycle.
When the processor has been stopped, the contents
o f the fro n t panel address re g is te r (cleared when the processor was
s ta rte d ) w ill be transm itted to the channel sp ecified by the highest
two b its o f the address.
The contents of th a t memory location
w ill then be transm itted to the c o n tro lle r where i t w ill be displayed,
in the DATA DISPLAY.
The DATA DISPLAY is designed to monitor the
data bus, latchin g the data whenever DAC goes tru e .
The follow ing controls w ill operate only when the processor has
been stopped.
The MANUAL RESET switch w ill set RST tru e momentarily
to reset the lo g ic o f a l l the system channels.
The LOAD ADR switch
w ill cause, the ADR switches to be loaded in to the fr o n t panel address
re g is te r.
DISPLAY.
The contents o f th is re g is te r are displayed in the ADDRESS
INCR ADR w ill increment th is re g is te r, and DECR ADR w ill
decrement i t .
Any o f these la s t three Switches w ill cause the con- ..
tents o f the fro n t panel address re g is te r to be sent to the channel
sp e c ifie d by the highest two b its o f the r e g is te r.
The channel w ill
31
then send the contents o f the addressed memory lo catio n back to the
c o n tro lle r to be displayed in the DATA DISPLAY.
The LOAD MEM switch
causes the DATA switches to be transm itted to the memory location
specified by the la s t LOAD ADR, INCR ADR, or DECR ADR operation.
32
11>
i-t Io
>»
M-K
>5
7M/7$
ct
JO
fkf> O -
C S7 ------
T l----
Figure 6.
C o n tr o lle r C i r c u i t :
Input
33
u/ ool
Figure 7.
C o n tr o lle r C i r c u i t :
CPU
34
JO
Figure 8.
JO
C o n tr o lle r C i r c u i t :
Decoder
35
I —— £) J f c o I
2------ Q f f C O i
4--- 0 $fCot
to — Q src»o
<►
- Cl
-
SfCL
—Osocoo
74111
0 0
esc a
Figure 9.
C o n tr o lle r C i r c u i t :
Channel S e lec t
36
J-CL^W
T l Di
Figure 10.
C o n tr o lle r C i r c u i t :
Transfer Control
37
SSCL
—OPP0
DOt
Ool
DO
Doi-
—O DM
- O Dfr2
- 0 08?
IfOt-
—O P &4
—OD bs
-O D %
Dot-
DOfc
—O D67
It
I fc
74 it;
IC *
'Cf
'C l
#-
If?
3 Cf
Xl
s u D o o -----------UCOI C h —
(SC O J Q -------------
I
S-S'OjQ-----SJc O U O -------------
SJr O f Q ----SSC O
fcO
-------------
Xl
X3
IC0
sst o?Q----------
ICl
SJt « 0 ------
IC3
JJf Oio-------------
Xi
Xl
X3
SJC ID O---------ssc 11 O ---------Sjc 11 0 ------------
SJf 13 I ------
Cfi#
'Cl
C fl
<1
era
CO
CsQ-
rc f
C
J
fe
cr?
sit w O ------
K(P
S
IC
ij O-------------
ICI
s pc 00 0 -----------s o c o i o -----------Ipt O l Q ------
IU
Iri
Xd
JBeoi O-----IprotKJ------
Xl
lea
sptofc O ----------
74-1 S ?
s pe 07 O -------------
SDCOgO-----------
IC(P
s p to iO ---------'P t IOO ---------; or Ii O - --------
IC I
Jpc 110 ------
ICO
le t
lea
41
IC I
IC 3
SPCUO---------Spc IfcO
set i t O ----------
Figure 11.
4»
X?
>Pt or O ---------
ic3
C o n tr o lle r C i r c u i t :
Status Input & Bus Drivers
38
+;
O #UT
B
O
JNCR
1t> 30
4
*
M DATA
Figure 12.
C o n tr o lle r C i r c u i t :
Front Panel Control
39
--------- DO (a
—k) ?
CU CD
ADDRESS'
Figure 13.
C o n tr o lle r C i r c u i t :
DISPLAY
Front Panel Address Register
CHAPTER V
.
DESCRIPTION OF THE MICROPROCESSOR CONTROLLED SYSTEM
This chapter describes the requirements and operation o f the
complete microprocessor controlled data in te rfa c e system.
. SYSTEM CONFIGURATION
The configuration o f the system is almost e n tir e ly up to the
system user.
There is one c o n strain t to be considered, however.
program memory must be located in the lowest numbered channels.
The
If
the memory is a t the f u l l 16,384 byte capacity of the 8008, the
memory would be located in channels 0 through 3, 4096 bytes per channel
I f only 4096 bytes o f memory are to be used, i t must be located in
channel 0.
Keeping the above r e s tric tio n s in mind, a sample system
is configured as shown in Table I , assuming th a t 16,384 bytes of
memory are to be used.
PROGRAMMING CONSIDERATIONS
Developing the control program should be r e la t iv e ly s tra ig h t
forward.
None of the 8008 in stru ctio n s except the 1/0 in stru ctio n s
require any special considerations.
The main considerations with the
1/0 in stru ctio n s is the format o f the data being input or output. .
A ll the OUT in stru ctio n s have the same format.
I f the address
of the output device is OOB, the source channel is being s p e c ifie d .
41
Table I
Sample System Configuration
Channel
Number
0
I
2
3
4
5
6
7
8-15
Channel
Use
Memory (00000B-07777B)
Memory ( I 0000B-17777B)
Memory (20000B-27777B)
Memory (30000B-37777B)
S e ria l Output
Counter-Timer
Quad Counter
Quad Counter
Not used
42
and b its I and O o f the accumulator specify SCI and SC0 re sp ec tiv e ly .
Bits 5 through 2 o f the accumulator specify which one o f the s ix ­
teen channels is to be the.source channel on the next byte tra n s fe r
between channels.
channel.
I f b i t 7 i s . I , the c o n tro lle r w ill be the source
I f the device address is 11B, the contents o f the
accumulator specify which channel is to be the destin atio n channel,
DCl, and DC0.
I f b it 7 is I , the c o n tro lle r w ill be the destination
channel.
Some o f the IN in stru ctio n s require the accumulator to be pre­
set.
I f the input address is 0 or I and the c o n tro lle r has been
sp e c ifie d as the source channel, the accumulator must contain the data
to be transm itted a t the time the IN in s tru c tio n is executed.
The
accumulator w ill always contain the byte th a t was tran sferred upon
completion o f the execution of the IN in s tru c tio n .
I f the input
address is 2, the accumulator must be set to specify which e ig h t
channels are to transm it t h e ir status to the c o n tro lle r.
The lowest
two b its o f the accumulator specify SCI and SC0, and DCl and DC0.
I f b i t 5 o f the accumulator is 0, channels 0 through 7 w ill transm it
th e ir status to the c o n tro lle r.
I f b i t 5 is I , channels 8 through 15
w ill send t h e ir status to the c o n tro lle r.
channels w ill have t h e ir status checked.
I f b i t 6 is 0, the source
I f b it 6 is I , the des­
tin a tio n channels w ill have th e ir status checked.
The accumulator
w ill contain the status o f the selected e ig h t channels a f t e r execution
43
of the IN 2 in s tru c tio n is completed.
The status is received in in ­
verted form, th a t is when a channel is read, the corresponding b it of
the accumulator is set fa ls e .
is not ready.
The b it w ill be set true i f the channel
The accumulator has no e ffe c t on the IN 3 in stru c tio n
and does not need to be preset.
The accumulator w ill contain the
present SRQ and the latched SKP signals upon completion o f the
execution of the IN 3 in s tru c tio n .
SKP in b it 0.
SRQ w ill be stored in b it 7 and
The remaining b its w ill be 0.
Figure 14 presents a possible sequence of in s tru c tio n to command
the system to tra n s fe r the contents of the counter of the counter­
tim er channel to the s e ria l output channel.
The sample configuration
given in Table I is assumed by the program.
OPERATION OF THE SYSTEM
While th is system may be considerably slower than a system with
a hardwired c o n tro lle r, i t is much more f le x ib le and powerful.
The
simple system ju s t needs to be powered up and possibly reset to put
the system in to operation.
The microprocessor controlled system
requires th a t a program be loaded in the program memory before i t can
be s ta rte d .
In the system presented in th is th e s is , loading the program
requires loading the program by hand through the fro n t panel switches
or loading a bootstrap program through the fro n t panel and using th is
44
I
LOOP:
MVI
OUT
MVI
OUT
MVI
IN
MVI
OUT
MVI
OUT
MVI
IN
ANI
JNZ
IN
IN
RAR
JNC
A,200B
IOB
A,21B
IlB
A ,3
I
A,24B
I OB.
A,20B
IlB
IOOB
2
20B
LOOP
O
3
LOOP
CONTROLLER
IS SOURCE
SERIAL OUTPUT
CONTROL IS DESTINATION
TURN ON CONTROL-OUT
AND DISABLE SRQ
SET COUNTER OF
COUNTER-TIMER AS SOURCE
SET DATA REGISTER OF
SERIAL OUTPUT AS DESTINATION
GET STATUS
OF LOWER 8 DESTINATIONS
ISOLATE SERIAL OUTPUT
NOT READY YET
READY: DO A TRANSFER
GET SKP DATA
PUT IN CARRY BIT
SKP NOT SET: DO ANOTHER TRANSFER
SKP SET: FALL OUT OF LOOP .
Figure 14. Sample Data Transfer Program Segment .
45
bootstrap program to load the control program.
The system could be
made e a sie r to load i f the bootstrap were contained in a read-only
memory.
In th is case, only a JMP in s tru c tio n and the bootstrap
address would need to be loaded.
Once the program has been loaded by one of the above methods,
a ll th a t is required to put the system in to operation is to operate
the RUN/STOP switch.
This w ill cause the processor to s t a r t fetching
and executing in stru c tio n s s ta rtin g a t memory address 00000B.
Unless
the program has a HALT in s tru c tio n included or the RUN/STOP switch
is operated, the program w ill continue fetching and executing .
in s tru c tio n s .
By using a b a tte ry system th a t is kept charged by the
commercial mains or some other means, the system w ill be power f a i l
safe.
i
CHAPTER VI
CONCLUSION
The microprocessor controlled data in te rfa c e system is
economically r e a liz a b le using the design presented in th is th esis.
i
.
.
This data in te rfa c e system can be operated with a number o f b e n e fits .
Changing a hardwired c o n tro lle r is elim inated since only a minor
program change is a l l th a t is required in the microprocessor con­
tr o lle d system.
In a d d itio n , some data reduction may be performed
in the processor before being transm itted to the external world.
By designing special in te rfa c e c ir c u it s , th is system may communicate
w ith another s im ila r system or even with instruments connected to a
bus such as the bus stru ctu re proposed by the In te rn a tio n a l E lectro­
technical Commission.
The ease of in te rfa c in g to the system presented here is also
valuable.
Only a small handful of components is required to perform
the in te rfa c e functions.
A ll th a t is required of the device being
in te rfa c e d is th a t i t should be e a s ily adapted to allow it s data to
be time m ultiplexed onto the bus.
The system should be powered by a power f a i l safe source.
Present
semiconductor memories w ill lose t h e ir contents i f the power to them
is in te rru p te d .
Since th is e n tire system is solid s ta te and operates
on r e la tiv e ly low voltages, a possible source may be an automotive
lead-acid b a tte ry kept charged by a t r ic k le charger th a t is connected
47
to the commercial mains.
Cost has been one fa c to r not discussed in d e ta il in th is th e s is ,
but was very important in designing the c o n tro lle r fo r the system.
In t e l's 8008 microprocessor was the le a s t expensive processor on the
market th a t met the system requirements.
This c o n tro lle r should be
producable a t a r e la t iv e ly small fra c tio n of the to ta l system cost,
though i t w ill probably be more expensive than a ty p ic a l in te rfa c e
c ir c u it .
The most expensive in te rfa c e c ir c u it w ill probably be the
memory channel due to the r e la t iv e ly high cost of semiconductor
memories, though th is is dropping f a i r l y ra p id ly .
REFERENCES
49
REFERENCES
1.
D ig ita l Equipment Corporation, Register Transfer Modules,
D ig ita l Equipment Corporation, Dec. 1973.
2.
In te l Corporation, In te l MCS-8 Users Manual, In te l Corporation,
Nov. 1974.
3.
In te rn a tio n a l Electrotechnical Commission, Standard In terfa c e
Systems fo r Programmable Measuring Apparatus, Part 2^: ByteS e r ia l-P a r a lle l In te rfa c e Systems, In tern a tio n a l E le c tro ­
technical Commission, March 1974.
4.
Smith, Dennis, D ig ita l Data A cquisition Systems In terfa c e
S p e c ific a tio n s , Unpublished, June 1974.
5.
Western Telecomputing Corporation, WTC-700, TOO A S e ria l Output
In te rfa c e Card S p e c ific a tio n s , Unpublished, A p ril 1975.
6.
W illiam s, Robert M ., Development of the Spring Creek Data
A cquisition System, M aster's th e s is , Montana State U n iv e rs ity ,
Electronics Research Laboratory Report 3174, August 1974.
MONTANA STATE UNIVERSITY LIBRARIES
3
762 1001 5507 4
N378
Sm54U
cop.2
Smith , Dennis I
Design of a micro­
processor controlled
data interface system
DATE
ISSUED TO
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