10-20 GS/s Sampling chip V2
-1 Specifications.
Channels
Sampling rate
Analog Bandwidth
Self and External trigger
Dynamic range
Sampling window
Sampling jitter
Crosstalk
DLL Timing generator
DC Input impedance
Conversion clock
Read clock
Power
Power supply
Process
4 + 1 test
10-20 GS/s
1-2GHz
Yes
800mV
400ps-800ps (or 8 delay cells)
10ps
1%
Internal phase comparator and charge pump, external LP filter
½ 50Ω internal, ½ external
Adjustable 500MHz 1GHz internal ring oscillator.
Maximum conversion time 8us.
40 MHz. Readout time (4-channel) 4 x 256 x 25ns=25.6 µs
40mW/channel
1.2V
IBM 8RF-DM (130nm CMOS)
-2 I/Os
Signal Name Type
Sampling cells
Biasl_0-3
In_0-3
aI
Write_0-255 dI
Ctrl_rd_0-3 dI
Vpol_cell_N
Vpol_cell_P
aI
aI
I/O Pad
y
y
n
y
y
y
14
Triggers
Trigger_mode dI
y
Trigger
dI
y
Th_0-3
aI
y
6
Function
Input return
Analog inputs 0-1V, 50Ω to returns Biasl_0_1
Store voltages across the sampling cells (timing).
Read switch control. Enables the sampling cell voltage onto the
ADC’s comparator
Bias current sampling cell N
Bias current sampling cell P
High: use internal input discriminators to stop the sampling process;
Low: use Triggers input.
External Trigger input when Self-External = External. High: sample, Enables
the sampling windows closing the sampling switches.
Low: hold, stops the recording process. All sampling switches open.
External Trigger thresholds
Timing generator
MCk
dI
VCN
aI
VCP
aI
VDL_out
dO
Out_0-255
Pump_out
aIO
y
y
y
y
n
y
6
Write clock (40 MHz to timing generator)
Timing cell control (falling)
(rising)
Output from VCDL for delay lock
Outputs to sampling windows
Phase comparator up output
ADC control
Cext
Ibias _rp
Ibias_buf
Rp
V2GN
V2GP
Ck_cv
Clear_ADC
Ibias_comp
aIO
aI
aI
dI
aI
aI
dO
dI
aI
y
y
y
y
y
y
y
y
y
10
External ramp input or internal ramp output (Vramp_out)
Ramp current
Ramp analog buffer (one for each channel)
Ramp (Ramp) active low, high clears the ramp cap.
Controls 2G counter ring oscillator (falling)
(rising)
Buffered ADC clock output monitors (2 GHz/4096=500 kHz).
Clears the ADC counter before conversion.
Comparator’s biasing
Read control
Ck_rd
Tok_in
Tok out
Clear_token
AD0-3
D0-11
dI
dI
dO
dI
dI
dI
y
y
y
y
y
y
Read clock (40 MHz)
Input of the token passing
Output of the token passing
Clear token
Channel address, selects channel to be read.
12-bit data bus controlled by the token and AD0_4. Tied to Gnd
in the Hi-Z state with a large internal resistor.
20
Power supplies
Vdd
Gnd
+1.2V
0V
Test structures
Sampling cell
Biasl_test
In_test
Vpol_cell
Trig_test
Write_test
Samp_out
Ctrl_rd_test
aI
aI
aI
dI
dI
dO
dI
y
y
y
y
y
y
y
7
Input return
Analog input 0-1V
Bias sampling cell
Sample and Hold
Write_test
Sampling cell out (after buffer)
Read sampling cell
Comparator
Comp_n
Comp_p
Comp_out
aI y
aI y
aO y
3
Test comparator input Test comparator input +
Test comparator output
Chip:
66 I/Os
36 Gnd
24 Vdd
126 pads
Package CQFP120A:
120 pads
All analog inputs protected with DC path to Gnd and Vdd +/- .6V (5 x 10 µm2 regular diodes).
-3
Operation Modes
Modes
-4
Write
Writes continuously samples of inputs in a caps arrays at 10 GS/s for 25.6µs.
Sampling stopped upon trigger.
Convert
Clears 2 GHz counter, ramps up Wilkinson ADCs for 2 µs.
Read
Sequences 256 counters of the channel selected by AD0-3 onto the data bus
at 40 MHz read clock rate.
Layout
Blocks sizes: Timing generator
Sampling cell
Input comparator
Comparator
Counter
Token
Ramp
Ramp buffer
Ring Oscillator
10 x 12 µm2
12 x 25
30 x 25
12 x 30
12 x 300
12 x 40
100 x 300
260 x 65
12 x 50
x 256
“
x4
x 256
“
“
Divider
12 x 300
Sampling Array
Delays ctrl
Token I
Write ck
ADC controls
Tests structures
3072 x 40
Comparator
In
disc
30x25
In
disc
30 x 25
SCA Channel 0
ADCs
2560 x 400
SCA Channel 1
ADC’s
3072 x 400
3072 x 400
30 x 10
Ramp
Buffer
260x65
Ctrl_rd 0-3
Sampling
cell
10 x 40
Ramp
Buffer
260x65
AD 0-4
Comp_tests
Sampling_cell
_tests
Ck_rd
Token
Timing Generator 3072 x 12
Ramp
Ch_Pump
300 x200
In
disc
30 x 25
SCA Channel 2
ADC’s
3072 x 400
Ramp
Buffer
260x65
In
disc
30 x 25
SCA Channel 3
ADC’s
3072 x 400
Inputs 03
RO
350 x 10
Pump_out
Data out
Th-0-3
Trigger
Trigger_
mode
RO controls
Token I I
Ramp
Buffer
260x65
5
ADC ck
Data
3072 x 40
Data
Size: 4000x 5000 µm2