EP20K30E I/O Pins
ver. 1.1
I/O & VREF
Bank
Pad Number
Orientation
Pin/Pad Function 144-Pin TQFP 208-Pin PQFP 144-Pin
(1)
(1)
FineLine BGA
324-Pin
FineLine BGA
8
8
8
8
8
8
8
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
8
8
8
8
7
7
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
I/O, DATA6 (2)
VCCINT
I/O, DATA7 (2)
I/O, nWS (2)
I/O, nRS (2)
VCCIO
I/O, nCS (2)
VCC_CKLK4 (3)
GND_CKLK4 (3)
GND_CKLK4 (3)
I/O, CS (2)
I/O, DEV_CLRn (4)
GNDINT
I/O, CLKLK_FB2n
(5)
CLKLK_FB2p
I/O, CLK4n (5)
CLK4p
I/O, CLK2n (5)
DATA0 (6), (7)
DCLK (6)
CLK2p
nCE (6)
TDI (6)
GNDIO
GND_CKLK2 (3)
GND_CKLK2 (3)
VCC_CKLK2 (3)
I/O, DEV_OE (4)
VCC_CKOUT2 (8)
GND_CKOUT2 (8)
I/O,
CLKLK_OUT2n (5)
CLKLK_OUT2p
VCCINT
I/O, LOCK2 (9)
I/O
I/O, LOCK4 (9)
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
GNDINT
GNDIO
VCCIO
I/O
I/O
I/O
I/O
GNDIO
I/O
I/O
I/O
I/O
Altera Corporation
105
VCCINT
104
103
102
VCCIO8
101
100
99
99
98
97
GND
-
150
VCCINT
146
145
142
VCCIO8
141
140
139
139
138
137
GND
-
B2
VCCINT
C1
C2
D2
VCCIO8
D3
D4
E2
E2
E3
E4
GND
F5
G4
VCCINT
H6
K5
J6
VCCIO8
H5
K6
L6
L6
M2
L5
GND
M4
96
95
94
93
92
91
90
GND
88
88
85
84
83
82
-
135
134
133
132
131
130
129
GND
128
128
125
124
123
122
121
F4
F3
F2
G4
G3
G2
G7
H5
H2
GND
G5
G5
G6
J3
H4
H3
K2
N4
L3
L2
J5
J2
J3
J4
K2
K3
GND
K7
K7
J7
L4
P3
P2
N3
81
VCCINT
80
79
78
76
75
VCCIO7
GND
GND
VCCIO6
71
70
69
GND
68
67
66
120
VCCINT
119
117
116
113
112
VCCIO7
111
110
109
108
GND
GND
VCCIO6
104
103
102
101
GND
100
99
98
97
J2
VCCINT
K3
J4
L2
L1
L3
VCCIO7
GND
GND
VCCIO6
L4
K4
J5
GND
K5
L5
K6
M3
VCCINT
N2
H4
R3
H2
G5
VCCIO7
H3
G1
H1
K1
GND
GND
VCCIO6
U5
U4
T4
R5
GND
V5
R6
T6
V7
1
EP20K30E I/O Pins
ver. 1.1
I/O & VREF
Bank
Pad Number
Orientation
Pin/Pad Function 144-Pin TQFP 208-Pin PQFP 144-Pin
(1)
(1)
FineLine BGA
324-Pin
FineLine BGA
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CONF_DONE (6)
nSTATUS (6)
FAST4
GNDINT
GNDINT
VCCINT
VCCINT
GNDINT
GNDINT
GNDIO
FAST3
TCK (6)
TMS (6)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNDIO
I/O
I/O
I/O
VCCIO
GNDIO
I/O
I/O
GNDINT
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
P7
V6
T7
VCCIO6
P8
R8
M9
R10
V8
N9
N8
U8
U9
T9
GND
VCCINT
VCCINT
GND
GND
T10
U10
U11
V9
P10
T11
P11
R11
V12
M10
VCCIO5
T12
R12
N11
V13
P12
V14
T13
U14
GND
R13
R14
T15
VCCIO5
GND
R18
N16
GND
L13
N17
L14
VCCIO4
M16
P18
L15
K14
Altera Corporation
65
VCCIO6
64
63
62
60
59
58
57
56
GND
VCCINT
VCCINT
GND
GND
53
52
51
50
49
48
47
46
VCCIO5
44
43
41
40
GND
39
38
37
VCCIO5
GND
35
33
GND
32
31
30
VCCIO4
29
27
26
96
94
93
VCCIO6
92
91
89
88
87
85
84
83
82
81
GND
VCCINT
VCCINT
GND
GND
77
76
75
74
73
72
71
70
69
68
VCCIO5
66
65
63
62
61
60
59
58
GND
57
56
54
VCCIO5
GND
50
48
GND
47
45
41
VCCIO4
40
37
36
35
J6
VCCIO6
L6
H6
M3
M4
M5
GND
VCCINT
VCCINT
GND
GND
M8
M9
M10
L7
L8
K7
K8
J8
J7
H8
VCCIO5
L9
K9
H7
K10
L10
GND
VCCIO5
GND
L11
L12
GND
K11
J11
J10
VCCIO4
H11
H10
-
2
EP20K30E I/O Pins
ver. 1.1
I/O & VREF
Bank
Pad Number
Orientation
Pin/Pad Function 144-Pin TQFP 208-Pin PQFP 144-Pin
(1)
(1)
FineLine BGA
324-Pin
FineLine BGA
4
4
4
4
4
-
113
114
115
116
117
118
119
120
121
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
-
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
VCCINT
I/O
I/O
I/O, CLK3n (5)
CLK3p
I/O, CLK1n (5)
GNDIO
nCONFIG (6)
CLKLK_ENA (6),
(10)
CLK1p
MSEL1 (6)
MSEL0 (6)
I/O
I/O
I/O
I/O
GNDINT
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
VCCINT
I/O
I/O
GNDIO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNDIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
TRST (6)
NCEO (6)
FAST1
GNDINT
GNDINT
Altera Corporation
VCCINT
25
24
23
GND
22
21
VCCINT
34
33
32
31
30
GND
29
28
VCCINT
J9
H9
G8
G11
GND
G10
G9
VCCINT
J13
M17
H16
H15
K15
GND
K17
K12
20
19
18
15
14
13
GND
11
10
9
VCCIO3
8
7
6
VCCINT
3
2
GND
143
142
141
140
VCCIO2
139
138
137
136
135
GND
133
132
131
130
VCCIO2
129
128
127
GND
-
27
26
25
22
20
19
18
GND
17
14
13
12
VCCIO3
11
9
7
5
VCCINT
4
2
GND
207
206
205
204
VCCIO2
203
202
201
200
198
197
196
GND
194
193
192
191
190
188
187
VCCIO2
186
185
184
GND
-
F9
F10
F11
C11
E8
GND
F8
F7
C10
VCCIO3
E11
E10
E9
D10
VCCINT
D11
C12
GND
B11
C6
B10
D9
VCCIO2
C9
D8
C8
B9
D7
GND
C7
B8
B7
E7
VCCIO2
A10
A9
A8
GND
-
K16
J16
J17
L17
L16
K18
J14
GND
J15
G16
H13
M18
VCCIO3
H14
H17
H18
G18
VCCINT
G17
G14
GND
B15
A15
D14
C14
VCCIO2
A14
A13
B13
C13
D13
E13
C12
GND
A11
B11
A10
A9
G10
C11
E12
VCCIO2
B10
C10
D10
GND
-
3
EP20K30E I/O Pins
ver. 1.1
I/O & VREF
Bank
Pad Number
Orientation
Pin/Pad Function 144-Pin TQFP 208-Pin PQFP 144-Pin
(1)
(1)
FineLine BGA
324-Pin
FineLine BGA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
VCCINT
VCCINT
GNDINT
VCCIO
FAST2
TDO (6)
GNDINT
I/O
I/O, INITDONE (4)
I/O, RDYnBSY (2)
I/O, CLKUSR (2)
I/O
I/O, DATA1 (2)
I/O
GNDIO
I/O, DATA2 (2)
I/O
I/O
I/O
I/O, DATA3 (2)
I/O
I/O
VCCIO
I/O, DATA4 (2)
I/O
I/O
I/O, DATA5 (2)
GNDIO
-
VCCINT
VCCINT
GND
VCCIO1
B9
C9
GND
D9
E11
E10
F10
A7
F9
D8
GND
E8
B7
C8
A5
B6
F8
D7
VCCIO1
C5
A4
B4
B2
GND
-
Altera Corporation
VCCINT
VCCINT
GND
VCCIO1
124
123
122
121
120
119
118
117
GND
115
114
113
112
VCCIO1
111
110
109
GND
-
VCCINT
VCCINT
GND
VCCIO1
181
180
179
178
177
176
175
173
171
GND
168
167
166
164
163
162
161
VCCIO1
160
159
158
157
GND
-
VCCINT
VCCINT
GND
VCCIO1
A5
A4
D6
E6
F6
B5
C5
GND
D5
B6
B4
C4
E5
VCCIO1
C3
A3
B3
GND
-
4
EP20K30E Configuration and Power Pins
ver. 1.1
Pin Name
144-Pin TQFP
208-Pin PQFP
MSEL0 (6)
MSEL1 (6)
NSTATUS (6)
NCONFIG (6)
DCLK (6)
CONF_DONE (6)
INIT_DONE (4)
nCE (6)
nCEO (6)
nWS (2)
nRS (2)
nCS (2)
CS (2)
RDYnBSY (2)
CLKUSR (2)
DATA7 (2)
DATA6 (2)
DATA5 (2)
DATA4 (2)
DATA3 (2)
DATA2 (2)
DATA1 (2)
DATA0 (6), (7)
TDI (6)
TDO (6)
TCK (6)
TMS (6)
TRST (6)
Dedicated Fast I/Os
CLK1p
CLK2p
CLK3p
CLK4p
LOCK2 (9)
LOCK4 (9)
CLKLK_ENA (6),
(10)
CLKLK_OUT2p (11)
CLKLK_FB2p
DEV_CLRn (4)
DEV_OE (4)
VCCINT
18
19
57
22
93
58
121
91
128
103
102
101
98
120
119
104
105
109
111
112
115
117
94
90
123
52
51
129
53, 56, 124, 127
20
92
23
95
80
78
21
81
96
97
84
1, 16, 36, 55, 73,
86, 108, 125
107
89
61
45
28
VCCIO8
VCCIO7
VCCIO6
VCCIO5
VCCIO4
Altera Corporation
25
26
82
29
132
83
178
130
185
145
142
141
138
177
176
146
150
157
160
163
168
173
133
129
180
76
75
186
77, 81, 181, 184
27
131
31
134
119
116
28
144-Pin
FineLine BGA
F11
F10
M4
G10
G2
M3
D6
H5
A9
C2
D2
D3
E3
E6
F6
C1
B2
B3
C3
C4
D5
C5
G3
H2
A4
M9
M10
A10
A5, A8, M5, M8
F9
G7
G8
F2
K3
L2
G9
324-Pin FineLine BGA
J17
J16
U9
K17
J3
U8
E11
K2
C10
K5
J6
H5
M2
E10
F10
H6
G4
B2
C5
B6
E8
F9
J2
K3
C9
U10
U11
B10
D10, B9, T10, T9
K16
J4
H15
L2
N2
R3
K12
120
135
137
124
1, 23, 52, 79, 105,
126, 156, 182
136
115
86
53, 80
42
J2
F4
E4
J3
A7, B1, B12, F1,
F12, H1, H12, M7
D1
K1
M2
M11
K12
M3
N4
L5
L4
G6, G11, F7, H9, H12, J8, K11, L7,
L10, M8, M13, N5, N12
F5, H7
K8, M6
L9, N7, P6
M11, P13
L12, N14
5
EP20K30E Configuration and Power Pins
ver. 1.1
Pin Name
144-Pin TQFP
VCCIO3
VCCIO2
VCCIO1
VCC_CKLK2 (3)
VCC_CKLK4 (3)
VCC_CKOUT2 (8)
GND
5
144
116
85
100
83
4, 12, 17, 34, 42,
54, 72, 74, 77,
87,106, 126, 134
GND_CKLK2 (3)
GND_CKLK4 (3)
GND_CKOUT2 (8)
No Connect (N.C.)
88
99
82
-
Total User I/O Pins
(12)
92
Altera Corporation
208-Pin PQFP
144-Pin
FineLine BGA
8
D12
189, 208
A11
172
A2
125
G6
140
D4
123
H4
10, 16, 24, 39, 43, A1, A6, A12, E1,
64, 78, 95, 114,
E12, G1, G12, J1,
118, 127, 143, 149, J12, M1, M6, M12
169, 183, 199
128
G5
139
E2
122
H3
3, 6, 15, 21, 38, 44, 46, 49, 51, 55, 67,
90, 106, 107, 144,
147, 148, 151, 152,
153, 154, 155, 165,
170, 174, 195
125
93
324-Pin FineLine BGA
J11, G13
F12, H10
E6, G8
J7
K6
P3
D4, D15, E5, E14, F6, F13, G7, G9,
G12, H8, H11, J9, J10, K9, K10, L8,
L11, M7, M12, N6, N13, P5, P14,
R4, R15
K7
L6
P2
A1, A12, A16, A17, A18, A2, A3,
A6, A8, B1, B12, B14, B16, B17,
B18, B3, B5, B8, C1, C15, C16,
C17, C18, C2, C3, C4, C6, C7, D1,
D11, D12, D16, D17, D18, D2, D3,
D5, D6, E1, E15, E16, E17, E18,
E2, E3, E4, E7, E9, F1, F11, F14,
F15, F16, F17, F18, F2, F3, F4,
G15, G2, G3, J1, J12, J18, K13, K4,
L1, L18, M1, M14, M15, M5, N1,
N10, N15, N18, P1, P15, P16, P17,
P4, P9, R1, R16, R17, R2, R7, R9,
T1, T14, T16, T17, T18, T2, T3, T5,
T8, U1, U12, U13, U15, U16, U17,
U18, U2, U3, U6, U7, V1, V10, V11,
V15, V16, V17, V18, V2, V3, V4
128
6
EP20K30E Pin Tables
ver.1.1
Notes:
(1) For the 144-pin and 208-pin QFP packages, four unique VCCIO levels are supported. The VCCIO pins
for I/O banks 1 and 8 must be at the same level. The VCCIO pins for banks 6 and 7 form a single I/O
bank. The VCCIO pins for I/O banks 4 and 5 must be at the same level. The VCCIO pins for I/O banks 2
and 3 must be at the same level. However, unique VREF settings are supported for each of the eight I/O
banks.
(2) This pin can be used as a user I/O pin after configuration.
(3) This pin is the power or ground for the ClockLock and ClockBoost circuitry. To ensure noise resistance,
the power and ground supply to the ClockLock and ClockBoost circuitry should be isolated from the
power and ground to the rest of the device. VCC_CKLK has the same voltage specifications as the
VCCINT and should be connected to a 1.8-V power supply. If the ClockLock or ClockBoost circuitry is
not used, this power or ground pin should be connected to VCCINT or GNDINT, respectively.
(4) This pin can be used as a user I/O pin if it is not used for its device-wide or configuration function.
(5) This pin is the complementary signal for the LVDS pair on dedicated inputs and outputs that can be
configured for the LVDS standard. If not used for the LVDS pair, these pins are regular I/O pins. Pins
with the "n" suffix carry the negative signal for the LVDS channel. Pins with a "p" suffix carry the positive
signal for the LVDS channel.
(6) This pin is a dedicated pin; it is not available as a user I/O pin.
(7) This pin is tri-stated in user mode.
(8) This pin is the power or ground for the external output of a PLL. These pins should be set to the VCCIO
level/standard desired for the external clock ouput. To ensure noise resistance, the power and ground
supply to the PLL external output should be isolated from the power and ground to the rest of the VCCIO
and GNDIO pins. If the PLL or external output is not used, this power or ground pin should be connected
to VCCIO or GNDIO, respectively.
(9) This pin shows the status of the ClockLock and ClockBoost circuitry. When the ClockLock and
ClockBoost circuitry is locked to the incoming clock and generates an internal clock, LOCK is driven
high. LOCK remains high if a periodic clock stops clocking. The LOCK function is optional; if the LOCK
output is not used, this pin is a user I/O pin.
(10) This pin is the active high enable pin for all of the PLL circuits in the device. When de-asserted, all PLLs
are reset to their default, unlocked state and will stop clocking. Once re-asserted, the PLLs will lock
again and start clocking. If this pin function is not needed, the pin should be connected to VCCINT.
(11) The CLKLK_OUT pin is powered by the VCC_CKOUT and GND_CKOUT pins.
(12) The user I/O pin count includes dedicated inputs and dedicated clock inputs. It does not include the
dedicated clock feedback and output pins.
Altera Corporation
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