Hardware Flags
and the RTI system
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
1
Need for hardware flag
• Often a microcontroller needs to test whether some event has
occurred, and then take an action
• For example
– A sensor outputs a pulse when a model train approaches a crossing
– The MCU must sense this pulse and then lower the crossing gate
MCU
sensor
• To make sure that it doesn’t miss the input pulse, the MCU must
continually read the input signal very rapidly
• This means that it can’t do anything else (e.g., sensing and
controlling other gates)
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
2
Hardware flag
• Instead of continuously reading an input signal, it is much more efficient
to have the input signal set a hardware flag (i.e., a flip-flop)
• Then the MCU can occasionally read the flip-flop and tell that the event
occurred – it doesn’t have to catch the input pulse when it happens
• No need to rapidly poll the input
VDD (ie,
logic 1)
D flip-flop
D
Device sets
flag (on rising
edge of input
signal)
Microcomputer Architecture and Interfacing
Q
Computer
tests flag
CLR
Computer
clears flag
Colorado School of Mines
Professor William Hoff
We assert CLR to force
the flip-flop to zero
(this is an asynchronous
control input)
3
Timing for the two methods
• Rapidly polling input signal
n
input
set?
y
read signal
detect
signal
time
output
control
signal
• Occasionally polling hardware flag
flag
set?
y
do other
useful
things
output
control
signal
time
read flag
n
detect
flag
clear flag
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
4
Memory mapped IO
• Recall that input/output
ports are assigned to
memory addresses
– Input is done by reading to
that address
– Output is done by writing
to that address
• A hardware flag looks like a
bit in a memory location
– You can sense whether the
flag is set by reading that
bit
– You can clear the flag by
writing to that bit
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
5
Flag Reading and Clearing
• You read a flag by reading the bit from the data bus
– If a read occurs to that address, signal R/W is set to 1
VDD
D
Event
signal
Data
bus
Q
R/W
CLR
• You clear a flag by writing a 1 to that bit on the data bus
– If a write occurs to that address, signal R/W is set to 0
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
Note: you
clear a flag
(ie, set it to
zero) by
writing a 1 to
it (nonintuitive!)
6
Timer flags
• Flags are set by many kinds of events
– Some are caused externally (e.g., by an input signal)
– Others are caused internally
• Timers are an example of an internal event
– A counter automatically counts up every clock tick
– When it reaches a certain value, a flag is set
• This is a much better way to estimate time than using
delay loops!
– Doesn’t waste (as many) CPU cycles
– Can be more accurate
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
7
Example: RTI System
• Real Time Interrupt (RTI)
system provides a
periodic timer
• Clock divider is set in
register RTICTL
• The period (in units of
OSCCLK cycles) is
determined by bits
RTR0..RTR6
reset:
when timeout occurs,
the RTIF flag (a flipflop) is set
RTR6:RTR0
RTICTL
OSCCLK
÷
Frequency divider
Counter
RTIF
7
6
5
4
3
2
1
0
RTR6
RTR5
RTR4
RTR3
RTR2
RTR1
0
RTR0
0
1
0
0
0
0
0
0
Figure 6.16 CRG RTI control register (RTICTL)
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
8
• The period (in units of OSCCLK cycles) is (N+1)*2(M+9), where
• N is the bit field RTR3 through RTR0
• M is the bit field RTR6 through RTR4
M=0 means
RTI off
Table 6.4 RTI interrupt period (in units of OSCCLK cycle)
RTR[3:0]
N
0000 (1)
0001(2)
0010 (3)
0011 (4)
0100 (5)
0101 (6)
0110 (7)
0111 (8)
1000 (9)
1001 (10)
1010 (11)
1011 (12)
1100 (13)
1101 (14)
1110 (15)
1111 (16)
RTR[6:4]
M
000
(off)
001
(210 )
010
(211 )
011
(212 )
100
(213 )
101
(214 )
110
(215 )
111
(216 )
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
210
2210
3210
4210
5210
6210
7210
8210
9210
10210
11210
12210
13210
14210
15210
16210
211
2211
3211
4211
5211
6211
7211
8211
9211
102 11
112 11
122 11
132 11
142 11
152 11
162 11
2 12
2212
3212
4212
5212
6212
7212
8212
9212
102 12
112 12
122 12
132 12
142 12
152 12
162 12
2 13
22 13
32 13
42 13
52 13
62 13
72 13
82 13
92 13
10213
11213
12213
13213
14213
15213
16213
214
2214
3214
4214
5214
6214
7214
8214
9214
10214
11214
12214
13214
14214
15214
16214
215
2215
3215
4215
5215
6215
7215
8215
9215
102 15
112 15
122 15
132 15
142 15
152 15
162 15
2 16
22 16
32 16
42 16
52 16
62 16
72 16
82 16
92 16
102 16
112 16
122 16
132 16
142 16
152 16
162 16
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
9
RTI Flag
• CRGFLG register
– RTIF is bit 7 of CRGFLG
– Check this bit to see if a timeout has occurred
– Reset the flag by writing a 1 to that bit
reset
7
6
5
4
3
2
1
0
RTIF
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
CRGFLG Register
There are other
flags in bits 6:0 ...
their names aren’t
shown
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
10
A note about clocks
• An external crystal is used to generate a square wave called OSCCLK
– In our board it is 8 MHz
•
This goes into a phase-locked loop (PLL) circuit which
– increases the frequency to 48 MHz
– makes it stable (v.s. jitter, skew, etc)
• The PLL clock is divided by 2 to make the 24 MHz E-clock
• But the RTI system uses the original 8 MHz OSCCLK
OSCCLK (8 MHz)
E-clock (24 MHz)
Colpitts
oscillator circuit
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
11
Example
• Set up the RTI system to generate periodic timeouts at
intervals of approximately 0.01 second
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
12
Example
• Set up the RTI system to generate periodic timeouts at
intervals of approximately 0.01 second
• Solution:
– The desired frequency of timeouts is 100 Hz
• We want to get the 8 MHz OSCCLK frequency down to 100 Hz
• So divide by a factor of 8 MHz/100 Hz = 80000
– 80000 is 10*8000, and 8000 is about 2^13
• We can get this by setting N=9, M=4
• So RTR[3:0] = 9, RTR[6:4] = 4
– Code:
RTICTL = 0x49;
Microcomputer Architecture and Interfacing
0x49 in binary is 01001001
Colorado School of Mines
Professor William Hoff
13
Example
Table 6.4 RTI interrupt period (in units of OSCCLK cycle)
RTR[3:0]
N = 10012
= 910
0000 (1)
0001(2)
0010 (3)
0011 (4)
0100 (5)
0101 (6)
0110 (7)
0111 (8)
1000 (9)
1001 (10)
1010 (11)
1011 (12)
1100 (13)
1101 (14)
1110 (15)
1111 (16)
M = 1002 = 410
RTR[6:4]
000
(off)
001
(210 )
010
(211 )
011
(212 )
100
(213 )
101
(214 )
110
(215 )
111
(216 )
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
210
2210
3210
4210
5210
6210
7210
8210
9210
10210
11210
12210
13210
14210
15210
16210
211
2211
3211
4211
5211
6211
7211
8211
9211
102 11
112 11
122 11
132 11
142 11
152 11
162 11
2 12
2212
3212
4212
5212
6212
7212
8212
9212
102 12
112 12
122 12
132 12
142 12
152 12
162 12
2 13
22 13
32 13
42 13
52 13
62 13
72 13
82 13
92 13
10213
11213
12213
13213
14213
15213
16213
214
2214
3214
4214
5214
6214
7214
8214
9214
10214
11214
12214
13214
14214
15214
16214
215
2215
3215
4215
5215
6215
7215
8215
9215
102 15
112 15
122 15
132 15
142 15
152 15
162 15
2 16
22 16
32 16
42 16
52 16
62 16
72 16
82 16
92 16
102 16
112 16
122 16
132 16
142 16
152 16
162 16
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
14
Example
• What’s the slowest period for the RTI system, assuming a 8
MHz OSC clock?
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
15
Example
• What’s the slowest period for the RTI system, assuming a 8
MHz OSC clock?
• Solution:
–
–
–
–
From the table, 16*(2^16) is the slowest period
This is 2^20, or about 10^6 cycles
At 0.125 us per cycle, this is 0.125 sec
So we get about 8 timeouts per second
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
16
Example - heartbeat
• Flash an LED at a rate of about 1 per second
– I.e., turn on for one second, then turn off for 1 sec
– This is kind of a “heartbeat” indicator by which
you can tell your program is running
PT0
• The slowest RTI timeout rate is 8/second
– So we only want to take an action every 8th
timeout
• We will have to keep a count of timeouts
– Every time we sense a timeout, we increment the
counter
– When the counter reaches 8, we reset the
counter to zero and toggle the LED
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
17
Example - heartbeat (continued)
• Psuedocode
Set up PT0 for output
Set up RTI rate for slowest rate
initialize count = 0
while (true)
while (RTIF is clear)
do nothing
clear RTIF by writing a 1 to it
increment count
if count = 8
toggle PT0
count = 0
end
end
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
18
Example - heartbeat (continued)
• C code
int
count = 0;
DDRT = 0x01;
// Set up PT0 for output
RTICTL = 0x7f; // Set up slowest RTI rate
while (1)
{
while (!(CRGFLG & 0x80)) ; // wait till RTIF set
// Clear RTIF by writing a 1 to it.
// Writing 0’s to other flag bits doesn’t affect them.
// Don’t do CRGFLG |= 0x80; this will clear other flags
CRGFLG = 0x80;
count++;
if (count == 8) {
PTT ^= 0x01;
count = 0;
}
// toggle PT0
Microcomputer Architecture and Interfacing
Colorado School of Mines
}
Professor William Hoff
19
Example – wag tail
• Assume PWM channel 4 is set up to control a servo motor,
such that duty = 10 moves the motor all the way left, and duty
= 20 moves the motor all the way right.
• Gradually move the motor from “all the way left” to “all the
way right” over a period of about 20 seconds.
• Approach:
– We’ll use the RTI system to generate timeouts every ~0.125 seconds
(i.e., 8 per second).
– We will need to increment the duty cycle 10 times over 20 seconds.
Or, increment it once every 2 seconds.
– Each RTI timeout occurs about 0.125 seconds, so in 2 seconds we have
2.0/0.125= 16 timeouts
– Every 16th timeout, increase the PWM duty cycle a little more
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
20
Example – wag tail (continued)
// Some code to set up PWM channel 4 follows ...
// :
// Set up RTI system to generate timeouts at the slowest rate.
// is about 0.125 seconds.
RTICTL = 0x7f; // longest possible period
The period
// We will need to increment the duty cycle 10 times over 20 seconds.
// Or, increment it once every 2 seconds. Each RTI timeout occurs
// every 0.125 seconds, so in 2 seconds we have 2.0/0.125 = 16 timeouts.
PWMDTY4 = 10;
for (i=0; i<10; i++)
{
for (j=0; j<16; j++) {
while (!(CRGFLG & 0x80)) ;
// wait for RTI timeout
CRGFLG = 0x80;
// Clear RTIF by writing a 1 to it
}
PWMDTY4++;
// increment duty time
}
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
21
Summary / Questions
• A hardware flag is just a flip-flop. When an event
occurs (i.e., a signal is received), the flag is set.
– Then the computer can read the flag later and see that the
event had occurred.
• An example of a system that sets a hardware flag is
the “RTI” system. It is just a periodic timer.
• Why is the “flag” system better than just directly
sensing the event, for example by continuously
reading an input pin?
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
22