Computer Architecture
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
1
Computer Hardware Organization
• Processor
– Performs all
computations;
coordinates
data transfer
• Input devices
– Sensors,
keypads, etc
• Output devices
– Motors, LEDs,
etc
• Memory
– RAM and ROM
From Huang, “HCS12/9S12 – An
Introduction to Software and
Hardware Interfacing”, 2010
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
2
Processor (CPU)
• Consists of:
– Arithmetic logic unit (ALU)
• A combinational circuit that performs
arithmetic and logic operations
– Control unit
• A state machine that generates control
signals to control the ALU and memory
transfers
– Registers
• These are storage locations in the CPU
• Sometimes there is a special register
called an accumulator that is used for
most instructions
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
3
Example ALU
• This ALU
performs 4
different
operations on
two n-bit
inputs, A and
B
• The operation
is determined
by a two-bit
opcode
(generated by
the control
unit)
Microcomputer Architecture and Interfacing
A
B
n
n
n
ALU
Result
Cout
2
opcode
Opcode
00
01
10
11
ADD
SUB
AND
OR
Colorado School of Mines
Professor William Hoff
4
Example ALU
drawn with Microsoft Visio
Opcode
00 = ADD
01 = SUB
10 = AND
11 = OR
Sel
B
Cin
0
1
1
Opcode
2
Cin
0
n
X
n
1
A
Sum
n
Y
00
n
Adder
Cou t
01
n
Sel
n
A
B
Opcode
A
2
Comparator
01
Sel
B
n
n
n
10
n
n
n
11
Resu lt
2
Cout
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
5
Example: ADD
Opcode
00 = ADD
01 = SUB
10 = AND
11 = OR
Sel
B
Cin
0
1
1
Opcode
2
Cin
0
n
X
n
1
A
Sum
n
Y
00
n
Adder
Cou t
01
n
Sel
n
A
B
Opcode
A
2
Comparator
01
Sel
B
n
n
n
10
n
n
n
11
Resu lt
2
Cout
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
6
Example: ADD
Opcode
00 = ADD
01 = SUB
10 = AND
11 = OR
Sel
Assume CIN=0
B
Cin
0
1
1
Opcode
00
Cin
0
n
2
0
X
n
1
A
Sum
Y
n
00
n
Adder
Cou t
01
n
Sel
n
A
B
00
Opcode
2
Comparator
01
A
0
Sel
B
n
n
n
10
n
n
n
11
Resu lt
2
Cout
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
7
Example: SUB
• We want A-B,
or A+(-B)
• So we add A
to the
negative of B
Sel
B
Cin
0
1
1
Opcode
2
Cin
0
n
X
n
• Recall that to
negate a
two’s
complement
number, you
invert all the
bits and add 1
Opcode
00 = ADD
01 = SUB
10 = AND
11 = OR
1
A
Sum
n
Y
00
n
Adder
Cou t
01
n
Sel
Resu lt
n
A
B
Opcode
A
2
Comparator
01
Sel
B
n
n
n
10
n
n
n
11
2
Microcomputer Architecture and Interfacing
Cout
Colorado School of Mines
Professor William Hoff
8
Example: SUB
Opcode
00 = ADD
01 = SUB
10 = AND
11 = OR
Sel
Cin
1
B
01
1
1
0
n
Opcode
0
2
Cin
~B
X
n
1
A
Sum
Y
n
00
n
Adder
Cou t
01
n
Sel
n
A
B
Opcode
2
Comparator
01
1
A
Sel
B
n
n
n
10
n
n
n
11
Resu lt
2
Cout
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
9
Control Unit
• The control unit is a little state
machine that generates control
signals for the ALU and
memory
• The sequence of operations is
specified by machine code (the
user’s program)
• Instruction register (IR) holds
the fetched instruction
• Program counter (PC) holds the
address of next instructions
Microcomputer Architecture and Interfacing
Colorado School of Mines
Clock
Control
signals
Control Unit
IR
PC
Data bus
Address bus
Professor William Hoff
10
Memory
• In many computer
architectures, IO
devices are treated
just like memory (this
is called memorymapped IO)
• Busses consist of
– Address bus
– Data bus
– Control bus
Microcomputer Architecture and Interfacing
• Data bus is bidirectional
(has tri-state drivers)
Colorado School of Mines
Professor William Hoff
11
Memory
OE – “output enable”
WE – “write enable”
• Memory is a set of
registers
– A decoder
selects a single
register, based
on the address
value
– The contents of
that register are
written to or
read out to the
data bus
Conceptual model for
an 64KB memory
2^16 = 65536
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
12
Memory Timing
• Memory read cycle
– CPU places address on
address bus, and
asserts RD
– Memory retrieves
contents of that
register, places on data
bus
• Memory write cycle
– CPU places address on
address bus, and data
byte onto data bus,
then asserts WR
– Memory latches in
value on data bus into
appropriate register
Microcomputer Architecture and Interfacing
WR
WR
RD
RD
Assumes the WR and RD signals are active
low, and data is latched on rising edge
Colorado School of Mines
Professor William Hoff
13
data or
machine
code
Location
A Simple Program
Contents
Instruction
Meaning of instructions:
$1000
$25
--
•
$1001
$37
--
$2000
$B6
LDAA $1000
$2001
$10
$2002
$00
$2003
$BB
$2004
$10
$2005
$01
$2006
$43
DECA
$2007
$7A
STAA $1002
$2008
$10
$2009
$02
:
LDAA $1000 (machine code $B6,$10,$00)
–
Load accumulator A with the contents of memory at
location $1000
:
•
–
Assembly
language
ADDA $1001
ADDA $1001 (machine code $BB,$10,$01)
•
DECA (machine code $43)
–
•
Add the contents of memory at location $1001 to
accumulator A
Decrement A by 1
STAA $1002 (machine code $7A,$10,$02)
–
Store the value in A to memory location $1002
:
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
14
Sequence of Events for LDAA Instruction
• (Assume that the program
counter points to address $2000;
the start of the LDAA instruction)
1. The processor puts $2000 onto
the address bus. The memory
responds by putting $B6 on the
data bus.
Location
Contents
Instruction
$1000
$25
--
$2000
$B6
LDAA $1000
$2001
$10
$2002
$00
:
:
$2000
Address bus
Memory
CPU
...
Data bus
$B6
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
15
Sequence of Events for LDAA Instruction
2. The processor “sees” that $B6 was
fetched, which is the opcode for an
LDAA instruction. It knows that it has
to fetch two more bytes for this type
of instruction. The processor puts
$2001 onto the address bus. The
memory responds by putting $10 on
the data bus.
Location
Contents
Instruction
$1000
$25
--
$2000
$B6
LDAA $1000
$2001
$10
$2002
$00
:
:
$2001
Address bus
Memory
CPU
...
Data bus
$10
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
16
Sequence of Events for LDAA Instruction
3. The processor puts $2002 onto
the address bus. The memory
responds by putting $00 on the
data bus. Now the processor
has fetched the entire
instruction.
Location
Contents
Instruction
$1000
$25
--
$2000
$B6
LDAA $1000
$2001
$10
$2002
$00
:
:
$2002
Address bus
Memory
CPU
...
Data bus
$00
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
17
Sequence of Events for LDAA Instruction
4. To execute the instruction, the
processor puts $1000 onto the
address bus. The memory
responds by putting the contents
of $1000, which is $25 on the
data bus. This is loaded into the
processor’s “A” register.
Location
Contents
Instruction
$1000
$25
--
$2000
$B6
LDAA $1000
$2001
$10
$2002
$00
:
:
$1000
Address bus
Memory
CPU
...
Data bus
$25
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
18
Timing diagram for LDAA
Clock
Address bus
(16 bit)
Data bus
(8 bit)
2000
B6
2001
2002
10
00
1000
25
Note: as this is not a real CPU, timing diagram is conceptual only
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
19
Summary
• The CPU consists of
– Arithmetic/logic unit (ALU)
– Control unit
– Registers
• Memory (and devices) are accessed through the
address bus, data bus, and control bus
• At the lowest level, the CPU executes “machine
code” (we can better read it by writing it as
“assembly language”)
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
20