Logic as language TDDC05: Embedded Systems • Propositional logic (sv. Satslogik) • Defined in terms of syntax and semantics • Syntax defined over a given vocabulary • A vocabulary is a set Simulation and Verification Lecture 4: Propositional logic Σ = {A, B, C,...} Simin Nadjm-Tehrani of proposition symbols Real-time Systems Laboratory Department of Computer and Information Science Embedded systems simulation and verification Linköping university 18 pages Spring term 2006 Embedded systems simulation and verification Linköping university Definition: formula 2 of 18 Spring term 2006 The semantics Let Σ be a vocabulary. • Defined given an evaluation • if A ∈ Σ then A is a formula • if F is a formula then ¬F is a formula • if F and G are formulas then (F∧G), (F∨G), (F→G) and (F↔G) are formulas • ⊥ is a formula • (nothing else is a formula) V: Σ → {0,1} , i.e. associates every proposition symbol to false or true • Formulas are interpreted via an evaluation Embedded systems simulation and verification Linköping university 3 of 18 Spring term 2006 • An evaluation (of Σ) is a function Embedded systems simulation and verification Linköping university Definition: Interpretation Valuation V can be extended over formulas, and is then called an interpretation: • • • • • V(⊥)=0, V(¬F)=1 iff V(F)=0 V(F∧G)=1 iff V(F)=1 and V(G)=1 V(F∨G)=1 iff V(F)=1 or V(G)=1 V(F→G)=1 iff V(F)=0 or V(G)=1 V(F↔G)=1 iff V(F)=V(G) Embedded systems simulation and verification Linköping university Truth tables • To show the interpretation of formulas given each valuation: F 0 0 1 1 5 of 18 Spring term 2006 4 of 18 Spring term 2006 G 0 1 0 1 F→ G 1 1 0 1 Embedded systems simulation and verification Linköping university 6 of 18 Spring term 2006 Models Let F be a formula and Γ a set of formulas. • An interpretation V such that V(F)=1 is a model for F • A model for Γ is an interpretation V such that V is a model for each formula in Γ • Mod(F) resp. Mod(Γ) denote the set of all models for F resp. Γ Embedded systems simulation and verification Linköping university 7 of 18 Spring term 2006 • How does one model a (static) world using logic? Embedded systems simulation and verification Linköping university Example Let P1 ,…, P4 denote: • P1: All students registered on the course are present here • P2: Logic is boring • P3: Logic is fun • P4: Logic is simple • How can one describe this world? • Which conclusions can be derived? Embedded systems simulation and verification Linköping university Axiomatisation (1) (2) (3) (4) ¬P1 → ¬P3 ∨ P4 P3 → ¬ P 2 P4 → P 2 ¬P1 Is P4 a valid conclusion? 9 of 18 Spring term 2006 Embedded systems simulation and verification Linköping university • Tautology: if F is true in all interpretations then F is a tautology • Contradiction: if F is false in all interpretations then F is a contradiction • Satisfiable: if F is true in some interpretation (has at least one model) then F is satisfiable • Falsifiable: if F is false in at least one interpretation then F is falsifiable 11 of 18 Spring term 2006 10 of 18 Spring term 2006 Extension to Γ Properties of formulas Embedded systems simulation and verification Linköping university 8 of 18 Spring term 2006 • Γ is satisfiable if Mod(Γ) ≠ ∅ • Γ is unsatisfiable if Γ has no models • NOTE! Γ can be unsatisfiable even if none of the formulas in Γ are contradictions Embedded systems simulation and verification Linköping university 12 of 18 Spring term 2006 Logical consequence • F is a logical consequence of Γ if every model for Γ is also a model for F, i.e. Mod(Γ) ⊆ Mod(F) • Denoted Γ F • F is a tautology denoted F • F and G are (logically) equivalent iff Mod(F)=Mod(G) • Denoted F ⇔ G Embedded systems simulation and verification Linköping university 13 of 18 Spring term 2006 Theorems • • • • • Γ F iff Γ ∪ {¬F} is unsatisfiable Γ is unsatisfiable iff Γ ⊥ F is satisfiable iff ¬F is falsifiable F G iff F→G F is a tautology iff ¬F is a contradiction Embedded systems simulation and verification Linköping university Example: Train crossing Approaching In-crossing Leaving 14 of 18 Spring term 2006 Modelling (1) Let F denote ”Far”, that is, when train is outside the crossing area. • Train Up T1 ↔ ((F ∨ A) ∨ (I ∨ L)) T2 ↔ (¬(A ∧ I) ∧ ¬(A ∧ L) ∧ ¬(I ∧ L) ∧ ¬(F ∧ I) ∧ ¬(F ∧ L) ∧ ¬(A ∧ F) ) Down • Gate B1 ↔ (U ∨ D) B2 ↔ ¬ (U ∧ D) Embedded systems simulation and verification Linköping university 15 of 18 Spring term 2006 Embedded systems simulation and verification Linköping university Modelling (2) Analysis • Show that: • Control system: S1 ↔ ((A ∨ I) → D) S2 ↔ ((F ∨ L) → U) ((T1 ∧ T2) ∧ (B1 ∧ B2)) ∧ (S1 ∧ S2) → K • That is ((T1 ∧ T2) ∧ (B1 ∧ B2)) ∧ (S1 ∧ S2) K • That is Mod(((T1 ∧ T2) ∧ (B1 ∧ B2)) ∧ (S1 ∧ S2)) ⊆ Mod(K) • Safety property: K ↔ ¬(I ∧ U) Embedded systems simulation and verification Linköping university 16 of 18 Spring term 2006 17 of 18 Spring term 2006 Embedded systems simulation and verification Linköping university 18 of 18 Spring term 2006