FLOATING GATE COMPARATOR WITH AUTOMATIC OFFSET MANIPULATION
FUNCTIONALITY
Eric Liu Wong, Pamela A. Abshire and Marc H. Cohen
Institute for Systems Research, University of Maryland, College Park, MD 20742, U.S.A.
eltan/pabshire/mhcohen@isr.umd.edu
ABSTRACT
We present a novel voltage comparator that uses nonvolatile
floating gate charge storage for either offset nulling or automatic programming of a desired offset. We demonstrate
the ability to reduce the variance of the initial offset and
to accurately program a desired offset. We exploit the negative feedback functionality of pFET hot-electron injection to
achieve fully automatic offset cancellation. The design has
been fabricated in a commercially available 0.35µm process. Experimental results confirm the ability to reduce the
variance of the initial offset by 2 to 3 orders of magnitude
and to accurately define a desired offset with maximum observed deviation of 728µV and typical deviation 109µV. We
achieve adaptation with settling time of 50ms, which is inversely proportional to the exponential of the injection voltage. We achieve controlled injection to accurately program
the input offset to voltages uniformly distributed from -1V
to 1V. The comparator exhibits a 5ns propagation delay.
1. INTRODUCTION
Comparators are decision-making circuits that interface between analog and digital signals. Comparators are used in
a wide variety of circuit applications, including analog-todigital converters, memories, dynamic logic, and sense amplifiers. A comparator usually consists of a pre-amplifier
stage and a regenerative stage followed by a buffer. Mismatches in the pre-amplifier and regenerative stage due to
process variations cause offset that directly affects resolution of a comparator. A common approach used to cancel
offset is dynamic switching which adds switches and multiple non-overlapping clocks, and excellent results have been
reported [1]. Since offset is a constant value, it is natural to store it using nonvolatile storage on a floating gate.
Floating gate circuits have been used to cancel offsets in
imagers [2], to trim current sources [3–5], and to autozero
amplifiers [6, 7]. The ability to store desired nonzero offsets in comparators is a feature that is not readily available
using existing offset cancellation techniques but is intrinsic to the voltage comparator we describe here. We present
the design of a comparator that automatically and accurately
;‹,(((
cancels offset, or depending on the application, can store a
predetermined offset.
2. BACKGROUND
A floating gate MOSFET uses an electrically isolated material as its gate. There are no direct electrical connections
to this circuit node, so charge on this gate remains trapped
for a very long time. In our comparator, the circuit offset
is stored in this high-retention charge form, and altered by
means of injection and tunneling.
The injection mechanism has been extensively described
in the literature [7, 8], and the injection feedback mechanisms for both nFET and pFET are discussed in detail in [9].
We briefly summarize the pFET injection feedback mechanism. For pFET injection, a constant current configuration
has negative feedback in drain-to-channel voltage, and is
thus stable. Fig.1(a) is the configuration used in the autozeroing amplifier [6], and Fig.1(b) is the gate follower configuration we use in our comparator. They are both constant
current configurations.
An accurate model in [10] suggests that injection current
β
Iinj = αIs exp −
+
λ(V
−
V
)
gd
gs
(Vgd + δ)2
scales as an exponential function of gate-to-drain voltage
Vgd . Since the channel current is constant, Is and Vgs are
fixed, so when Vgd increases, Iinj also increases pulling
down the gate voltage, and reducing Vgd . This negative
feedback configuation causes the gate voltage to follow the
drain voltage; hence the name “gate follower” configuration. We use the “gate follower” configuration for the pFET
differential pair in our comparator which couples the output
voltages to the input floating gate voltages to realize output
offset storage [1] for offset nulling.
3. ADAPTIVE FLOATING GATE COMPARATOR
Fig.2 shows the implementation of our Adaptive Floating
Gate Comparator (AFGC). Floating gate transistors M1 and
,
,6&$6
Fig. 1. The constant current configuration in (a) the autozeroing
amplifier [6] and (b) the gate follower used in our adaptive floating
gate comparator.
M2 form the input devices of a differential pair. Crosscoupled n-MOS transistors M3 and M4 form the regenerative elements of the comparator. When the clock signal
is high, the n-MOS switch M5 closes and resets the comparator. When the clock goes low, switch M5 opens and
the evaluation phase begins. With the power supply Vdd
set to a normal operating voltage (3.3 volts), there is insufficient energy to produce hot-electron injection from the
channel onto the floating gates of M1 and M2. As we increase voltage on the input terminals Vi+ Vi− and Vdd,
the Vds of M1 and M2 will increase and the probability
of hot electron injection onto their floating gates increases,
thus we inject charge onto their floating gates. We use a
dynamic technique that uses injection during the evaluation phase when the clock signal clk is low, with adaptation
achieved over many evaluation cycles. By injecting with
a running clock, we use the outcome of each comparison
to correct offset. Thus the feedback loop encompasses all
mismatch and offset within the circuit, so accurate offset
cancellation can be achieved. We bias the common mode
input voltage VCM = (Vi+ + Vi− )/2 so that the drain-tochannel voltage is insufficient for injection during reset, but
sufficient to produce injection during evaluation when one
of the outputs Vo+ and Vo− is grounded. From a simulation model [10] and our own experimental results, injection begins when drain-to-channel voltage exceeds 3V. For
a pFET threshold of 1V, we bias VCM above 2V. During reset both outputs are approximately at the threshold voltage
Vo+ ≈ Vo− ≈ 0.7V, so we set the desired VCM between
2V and 2.7V. For VCM higher than 2.7V, injection initially
occurs during both reset and evaluation, but quickly reduces
the VCM of the floating gates to 2.7V, after which the circuit
enters the desired operating range. Suppose that the initial
mismatch causes the outputs to be unbalanced Vo+ > Vo−
when inputs are equal. When the comparator latches, Vo−
is pulled to ground, injecting a small charge ∆Q on the gate
Vg+ . The charge accumulates on gate Vg+ for each clock
cycle until the gate voltage is low enough that the outcome
reverses (Vo+ < Vo− ). Thereafter, the outcome alternates
for each cycle and causes injection on the opposite side of
the p-differential pair. Therefore, adaptation is controlled by
Fig. 2. Circuit diagram of the AFGC with pFET input floating
gate differential pair.
the outcome of the comparison and the offset can be tuned
acurately.
In practice, any comparator has a limited conversion
accuracy that can be defined by the variance of the inputreferred noise. Ambiguity exists near the switching point
where the outcome is uncertain. This uncertainty is caused
by flicker noise and thermal noise generated by the MOSFETs within the circuit. The probability that the outcome
is correct depends on how far the input is away from the
switching point. Empirically we find that this distribution is
Gaussian, so we characterize the distribution with the mean
and standard deviation obtained from the data. Fig.3(a)
plots the measured cumulative distribution function (cdf) of
the filtered output voltage V (see Fig.4(b)) as a function of
the input offset voltage and an empirically fitted error function. Fig.3(b) shows the probability density function (pdf)
corresponding to the fit which with mean µ and variance σ 2 .
Let X be a random variable representing the actual input
offset having a nonzero mean µ and variance σ 2 . Our goal
is for µ to approach a desired offset µd . Using the dynamic
injection method,
during each clock cycle µ increases by
∆V1 = C1−1 T Iinj1 dt ≈ Qinj1 /C1 for X < µd , and
decreases by ∆V2 ≈ Qinj2 /C2 for X > µd . C1 and C2
are the total capacitance on the floating gates, and T is the
time the clock is low, typically 50% duty cycle. We express
the net shift in µ for one clock cycle as ∆µ = ∆V1 P [X <
µd ] − ∆V2 P [X > µd ]. The calibration finishes when an
equilibrium ∆µ = 0 is reached,
µd − µ
µd − µ
= ∆V2 1 − Φ
,
∆V1 Φ
σ
σ
x
2
where Φ(x) = √12π −∞ e−t /2 dt is the cdf of a Gaussian
random variable with µ = 0 and σ 2 = 1. Therefore, we
express the resulting input offset µ as
∆V2
−1
.
µ = µd − σΦ
∆V1 + ∆V2
,
We can see that the resulting input offset is not a function of
the initial input offset caused by device mismatch,
but rather
2
a function of both injection mismatch ratio ρ = ∆V∆V
1 +∆V2
and the standard deviation σ of the input-referred noise.
Fig. 4. (a) Output buffer. (b) Inverter cascade and external test
setup.
Fig. 3. Input offset distribution (a) measured voltage distribution
and empirically fitted error function, and (b) corresponding Gaussian probability density function.
4. EXPERIMENTAL RESULTS
The circuit configuration used for testing the comparator is
shown in Fig.4. We supply the comparator with a common
mode voltage VCM on the negative input Vi− and a differential voltage Vd the differential inputs. The comparator
depicted in Fig.2 drives the output buffer of Fig.4(a) to generate rail-to-rail signals on Vout+ and Vout− . A cascode of
inverters that are geometrically scaled in Fig.4(b) deliver the
signals to external pads with minimum delay. During reset
(clk=Hi) the outputs of the comparator are high, and during
evaluation the output is determined by the comparison. We
measure a low pass filtered version VA of the digital output
voltage A, as shown in Fig.4. We interpret this voltage to determine the probability that the output is logic high. We use
a Keithley 236 to supply Vd in 100µV increments. For simplicity, we operate the clock at 100kHz, and choose the time
constant of the lowpass filter to be τ = 2πRC = 0.01s,
so that the clock frequency is much larger than τ , which is
much larger than the sampling interval. We measure VA as
a function of Vd then translate the voltage into probability
by shifting and scaling so that it ranges from 0 to 1. We interpret the scaled reading as the Gaussian cdf, and extract µ
and σ from the data using a minimum squared-error curvefitting procedure.
We set Vdd to 4.5V to allow injection and Vdd2 to 3.3V
for the output buffers. We raise VCM to 2.5V (or higher)
for programming, as demonstrated in the following experiments. We measure the offset for AFGC circuits on twelve
different chips before any programming, after UV erasure,
and after programming. For unprogrammed chips, the input offset has mean of 45.35mV and standard deviation of
73mV. After 20 hours of UV erasure, the mean offset is
reduced to 22.02mV with a reduced standard deviation of
6.37mV. Therefore, we can see that a significant amount
of random initial charge exists on the floating gate when
the chip is fabricated. We then zero the offset by performing injection on the p-type differential pair. After programming, the mean offset is -109µV with a standard deviation
of 379µV.
We demonstrate in Fig.5 the resulting voltages after programming different offsets ranging from -1V to +1V. We
used VCM = 2.5V for injection. The voltage residue is defined to be the measured input offset minus the programmed
input offset. The solid trace shows the input offsets measured at a VCM of 1.9V, and the dashed trace shows the
result when measuring at VCM =1.6V. From the figure we
can see that larger shifts of VCM from injection conditions
result in larger offset errors during operation. This is caused
by Early voltage mismatches on the p-type differential pair
and channel length modulation on the pFET that sets the
bias current for the p-type differential pair.
Figure 6 shows the time course of offset cancellation.
We first introduce a 0.2V input offset on the gate, and then
pulse the VCM to an appropriate injection voltage (between
3V and 3.3V) for 10ms (100 clock cycles) with Vd =0V and
clk running at 100kHz. We take measurements with VCM
= 1.9V between each pulse. We can see that for higher
programming VCM we achieve faster injection. The time
,
going and future work will use our AFGC to implement new
classes of adaptive data converters.
6. ACKNOWLEDGEMENTS
We thank the MOSIS service for providing chip fabrication through
their Educational Research Program. P.A. is supported by an NSF
CAREER Award (NSF-EIA-0238061).
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Fig. 5. Programming with a wide range of voltages.
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5. CONCLUSION
We have described a novel floating gate comparator that has
the ability to automatically and accurately either cancel its
input offset or program a specified offset. We have experimentally verified all desired functionality. Our comparator uses pFET hot-electron injection in a negative feedback
loop during calibration and programs a nonvolatile corrective charge on the floating gate. We have shown the theory
and mechanism of the pFET injection that leads to stable
calibration. In addition to canceling offset, our comparator
can accurately store an arbitrary input offset, a feature not
readily available in other offset cancellation schemes. On-
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in 0.35-µm CMOS,” IEEE JSSC, vol. 36, no. 12, pp. 1847–
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,