Research Journal of Applied Sciences, Engineering and Technology 4(4): 342-349, 2012
ISSN: 2040-7467
© Maxwell Scientific Organization, 2012
Submitted: August 26, 2011
Accepted: October 07, 2011
Published: February 15, 2012
Design and Robustness Analysis of a PID Based Sliding Mode Controller
for a dc-dc Converter
1
D.M. Mary Synthia Regis Prabha, 2S. Pushpa Kumar and 1G. Glan Devadhas
1
PRIST University, Thanjavur
2
Heera College of Engineering and Technology, Nedumancadu, Trivandrum
Abstract: This study deals with the design and analysis of a dc-dc converter operating in continuous conduction
mode with Proportional-Integral-Derivative control and PID based Sliding Mode Control (SMC). A small signal
model is developed using Switching Flow Graph (SFG) from which the control coefficients for the PID
controller is selected. PID based SMC uses a control law which constrains the weighted sum of the voltage
error, its derivatives and the integral of the voltage error to zero. The equivalent control technique is used in
its design which makes the converter more suitable for fixed frequency operation. Sensitivity of these
controllers to supply voltage disturbances and load disturbances is studied and results are presented.
Key words: dc-dc converter, PID based SMC, PID control, switching flow graph
Modulation (PWM) for the controller. In this paper this
technique has been demonstrated for a Buck Converter.
PID control and PID based SMC are two different
control techniques considered in this paper. PID control
is a traditional linear control, while SMC is a type of nonlinear control. Linear PID controllers for dc-dc converters
are usually designed by classical frequency response
techniques applied to the small-signal models of
converters (Liping et al., 2009). A bode plot is adjusted in
the design to obtain the desired loop gain, cross-over
frequency and phase margin. The transient response can
be tuned using root locus type approaches (Prodic and
Maksimovic, 2002). The stability of the system is
guaranteed by an adequate phase margin. PID control is
typically designed for one nominal operating point (Perry
et al., 2007). For a buck converter, the magnitude of the
frequency response depends on the duty cycle. Duty cycle
variations do not change the shape of the magnitude plot
of the transfer function, but only shifts the plot upward
(Siew et al., 2008). Therefore, a PID controller may not
respond well to significant changes in operating points.
In this study, the problem of PID based quasi sliding
mode control of a Buck Converter is discussed. The
design of a PID controller for a dc-dc converter is
discussed in detail. Finally, comparison of these two
methods is performed in order to verify the dynamic and
steady state responses and their robustness to sudden line
variations.
INTRODUCTION
Switching mode dc-dc converters are widely used
today in a variety of applications including power
supplies for personal computers, mission critical space
applications, laptop computers, dc motor drives, medical
electronics as well as high power transmission. These
converters are non-linear dynamical systems. The nonlinearities arise primarily due to switching, power
devicesand passive components such as inductors and
capacitors.
A control technique suitable for dc-dc converters
must cope with their intrinsic non-linearity and wide input
voltage and load variations ensuring stability in any
operating condition while providing fast transient
response. Among the various control techniques available,
sliding mode control offers several advantages, namely
large signal stability, robustness, good dynamic response
and simple implementation. The design of a SMC does
not require an accurate model of the system. The ideal
nature of the controller is to operate at an infinite
switching. This nature enables the controlled variable to
track a certain reference path to achieve the desired
dynamic response and better steady state operation (Duan
and Jin, 1999). This extreme high frequency operation
results in excessive switch losses and Electromagnetic
Interference (EMI) noise issues. In addition sliding mode
control also exhibits steady state error for the output
voltage. Hence, for sliding mode controllers to be
applicable for dc-dc power converters, it becomes
essential to constrict the switching frequency within a
practical range. Moreover, variable switching frequency
is undesirable for power converters. A method of ensuring
constant switching frequency is to employ Pulse Width
SYSTEM MODELING
Linear controllers for dc-dc converters are often
designed based on mathematical models. The most
commonly used technique for modeling linear
Corresponding Author: D.M. Mary, Synthia Regis Prabha, Associate Professor, Noor ul Islam University, Kumaracoil
342
Res. J. Appl. Sci. Eng. Technol., 4(4): 342-349, 2012
Fig. 1: Buck converter
Fig. 2: On-state switching flow graph
Fig. 3: Off-State switching flow graph
Fig. 4: SFG of buck converter
controllers is the traditional state space averaging method.
The major drawback of this method is that the linearized
models obtained through averaging process, do not
predict the large-signal stability information, and are only
sufficient to predict small-signal stability.
A small signal model takes a circuit and based on an
operating point (bias) and linearizes all the components.
Nothing changes because the assumption is that the signal
is so small that the operating point (gain, capacitance etc.)
doesn't change. A large signal model on the other hand
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Res. J. Appl. Sci. Eng. Technol., 4(4): 342-349, 2012
Table 1: Prototype Buck Converter circuit parameters
Parameter
Value
24
Input voltage, Vi
Desired output voltage, Vod
12
Load resistance, Ro
6
Filter inductance, L
35
Filter capacitance, C
150
ESR of inductor, RL
0.12
ESR of capacitor, RC
0.03
takes into account the fact that the large signal actually
affects the operating point and takes into account that
elements are non-linear and that circuits can be limited by
power supply values. A small signal model ignores supply
values.
Graphical Analysis Method (GAM): This is a
non-linear modeling method. This is developed for
pulse-width modulated converters. The GAM converts the
switching converter, even the multistate converter
systems, into a unified dynamic model. From unified
model, it is possible to derive large, small signal and
steady state models with mathematical manipulations.
Each system can be represented by a flow graph. The
switching flow graph is obtained by combining the flow
graphs of the subsystems through the use of switching
branches (Mummadi, 2004). The switching flow graph
model is easy to derive, and it provides a visual
representation of a switching converter system.
Buck converter shown in Fig. 1 has two modes of
operation: (i) Switch is on (ii) Switch is off. The circuit
diagram of the Buck converter is shown below.
The switching flow graph is drawn for the on-state
sub-circuit and the off-state sub-circuit which is shown in
Fig. 2 and 3, respectively. These two sub-circuits are
combined together which gives the switching flow graph
of the Buck converter which is shown in Fig. 4.
the filter capacitance C (Perry et al., 2007). The cut-off
frequency of the second order low pass filter is TC
=1/%LC Variations of D, varies the magnitude of the
transfer function. Moreover, it does not change the shape
of the frequency response, but shifts the magnitude plot
upward or downward.
Table 1 gives the circuit parameters of the prototype
Buck Converter selected for experimentation. The
nominal operating point of the prototype Buck converter
is chosen as follows: Input Voltage, Vi = 24 V, Desired
Output Voltage, Vod = 12 V, Duty ratio D = 0.5.
Small signal control to output transfer function at this
nominal operating point is given as:
⎤
V$0 ( s) ⎡
24 + 10.8e − 4 s
=⎢
−4
−9 2 ⎥
$
d ( s) ⎢⎣ 1 + 5817
. e s + 4.243 e s ⎥⎦
⎤
V$0 ( s) ⎡
1 + 45.39 e − 4 s
=
⎢
6
3
2⎥
$
Vin ( s) ⎢⎣ 235.65e + 137 e s + s ⎥⎦
V$0 ( s) V0
=
D
d$( s)
(4)
(1)
Design of PID controller for a buck converter: The
open loop transfer function G(S) H(s) of the Buck
converter is given by Eq. (3). A PID compensator is
designed with a phase margin of 45º at a cross-over
frequency of 125.66 kHz. The steady state error for unit
ramp input is considered to be 0.035%. The PID
controller has a transfer function of GC(S) = KP+ Kis
+Kds. Ki is decided by steady state requirements. Once we
know KI , we can find out KP and Kd, Eq. (5) and (6).
Small Signal Input to Output transfer function is derived
as:
V$0 ( s)
DR0
=
V$in ( s) ( R0 + RL )
⎡
⎤
⎢
⎥
1 + sRC C
⎢
⎥
⎢
⎛
⎛ R0 + RC ⎞ ⎥
RL R0
L ⎞
2
⎢ 1 + s⎜ RC C +
C+
⎟ + S LC⎜
⎟⎥
RL + R0
RL + R0 ⎠
⎢⎣
⎝
⎝ R0 + RL ⎠ ⎥⎦
(3)
Small Signal Input to Output transfer function at this
nominal operating point is given as:
Derivation of small-signal model using switching flow
graph: Small signal control to output transfer function is
derived as:
⎤
⎡
⎥
⎢
1 + sRC C
⎥
⎢
⎢
⎛
⎞
⎛ RO + RC ⎞ ⎥
RL RO
L
2
⎢ 1 + s⎜ RC C +
C+
⎟ + s LC⎜
⎟⎥
RL + RO
RL + RO ⎠
⎢⎣
⎝
⎝ RO + RL ⎠ ⎥⎦
Units
V
V
S
:H
:F
S
S
(2)
In this transfer function, VO is the output voltage, D
is the duty cycle, C is the output capacitance, L is the
inductance and R is the load resistance. RL and RC are the
Equivalent Series Resistance (ESR) of L and C,
respectively. This transfer function is a second order low
pass filter, with a left-half-plane introduced by the ESR of
Kp =
sin θ
| G( jω ) H ( jω )|
(5)
Kd =
Ki − ω cosθ
ω 2 |G ( jω ) H ( jω )|
(6)
where, tan 2 = Kp T/Ki T2 Kd. The KP, Ki and Kd values
are found to be 5.80125, 119.048 and 0.0869×10G4,
respectively.
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Res. J. Appl. Sci. Eng. Technol., 4(4): 342-349, 2012
Design of a sliding mode controller:
C Step 1: Determination of the state variables: The
output voltage error decay is essentially the main
control objective in real time. The selected state
variables are output voltage error, output voltage
error dynamics and the integral of the error of the
output capacitor (Utkin et al., 1999):
C
⎤
⎡V − βV
O
⎥
⎢ ref
⎥
⎢d
X = ⎢ (Vref − βVO ) ⎥
⎥
⎢ dt
⎥
⎢
V
−
β
V
dt
(
)
ref
O
⎥⎦
⎢⎣
C
B
1
− ( L + CR0 RL )
LCRO
0
0⎤
⎥
0⎥
⎥
0⎥⎦
⎡ x1 ⎤
⎢ ⎥
⎢ x2 ⎥
⎢⎣ x3 ⎥⎦
B
[V
− β VO LC −
]
+
( L + CRO RL )
β ic +
CR0
<0
α1
β Lic
α2
βV0 ( R0 − RL )
R0
(9)
>0
For S ÷ 0G0 and Ð > 0 and âs ÷ 0G = 1, we get:
CR0
]
(10)
R0
The simplified existence condition in Eq. (10) is
obtained by combining both Eq. (8) and (9):
α3
α
[V − βVO ]LC − 1 βLiC
α 2 ref
α2
( L + CRO RL )
βV ( R − RL )
+
< βVi
βiC + 0 0
0<
where ‘S’ is the instantaneous state variables
trajectory.
dt
s→ 0 −
<0
Step 5: Derivation of existence condition:
For S ÷ 0+ and Ð < 0 and âs ÷ 0+ = 0, we get:
[
⎧1, when S > 0
u= ⎨
⎩ 0, when S < 0
S = Kd
= K T Ax + K T BU
s→ 0 +
α
α
β Vi > 3 Vref − βVo LC − 1 β LiC
α2
α2
( L + CRO RL )
β V ( R − RL )
+
β ic + 0 0
Step 3: Define the switching status and sliding
equation:
d (Vref − β VO )
S&
ref
⎡
⎤
0
⎡ 0 ⎤
⎢
⎥
⎢ − βV ⎥
β V ( R − RL ) ⎥
i⎥
+⎢
u+ ⎢ 0 O
⎢
⎥
⎢ LC ⎥
LCR0
⎢
⎥
⎢ 0 ⎥
0
⎢⎣
⎥⎦
⎦
⎣
C
= K T Ax + K T BU
s→ 0 −
Step 2: Develop the state variables:
⎡ x&1 ⎤ ⎡ 0
⎢ ⎥ ⎢
⎢ x&2 ⎥ = ⎢ 0
⎢⎣ x&3 ⎥⎦ ⎢
⎢⎣ 1
S&
s→ 0 +
∫
C
has a form similar to a PID (Proportional, Integral
and Derivative) controller. Third, it contained a form
of state-feedback which provides a more flexible way
to close the feedback loop to obtain any type of
responses at will.
Step 4: Ensure existence of sliding mode operation:
The local reachability condition lims÷0 + s.Ñ < 0,
must be satisfied. This is expressed as:
CR0
+ K p (Vref − β VO )
T
∫
R0
The condition given in Eq. (10) provides a range of
employable sliding surface coefficients such that
irrespective of the circuit parameters, the system
trajectories near the surface are directed towards the
sliding surface itself.
(7)
+ Ki (Vref − Vo )dt
O
S = a1x1 + a2 x2 + a3 x3 = K T x
(11)
(8)
Considering the design parameters, the existence
condition is modified. From the left inequality of the
existence condition, we get:
where "1, "2 and "3 are sliding coefficients with KT =
["1 "2 "3].
This Eq. (7) has three significant implications. First,
this control law states that not only the weighted sum
of voltage error and its derivative needs to be
constrained to be zero but also the integral of the
voltage error must be included. Secondly, the Eq. (7)
α1
<
α2
LC
α3
( R − RL )
(V − βVo ) + βVo O
α 2 ref
RO
βLic
⎡ 1
R ⎤
+⎢
+ L⎥
CR
L ⎦
⎣ O
345
(12)
Res. J. Appl. Sci. Eng. Technol., 4(4): 342-349, 2012
From the left inequality of the existence, we get:
1.00
a1
<
a2
( R − RL )
a3
(V − βVo ) − βVo o
a2 ref
Ro
βLiC
(13)
⎡ 1
RL ⎤
+⎢
+
⎥
L ⎦
⎣ CRO
0.98
βVi − LC
0.96
0.94
0.92
0.90
0.88
Dividing Eq. (11) and (12):
0
⎧ ⎡
⎤⎫
R ⎤ α ⎡ Vref
− Vo ⎥ ⎪
⎪Vo ⎢1 − L ⎥ + 3 ⎢
Ro ⎦ α 2 ⎣ β
⎪
⎦⎪
Vi = 2⎨ ⎣
⎬
⎪
⎪ LC − LiC − i R
C L
⎪
⎪
CR
o
⎭
⎩
α1
<
α2
LiC
25
30
35
17.6
17.4
17.2
17.0
16.8
16.6
16.4
16.2
(14)
16.0
15.8
15.6
0
⎡
R ⎤
1
+⎢
+ L⎥
L ⎥⎦
⎢⎣ CRo(max)
10
5
20
15
Load Ro ( Ω)
25
30
U eq = − [ K T Ax ]−1 K T [ Ax + D]
⎧⎪ ⎡
RL ⎤
Vi(min) ≥ 2⎨Vo ⎢1 −
⎥+
Ro(max) ⎥⎦
⎩⎪ ⎢⎣
⎫⎪
⎤
Li c
α3 ⎡ Vref
− Vo ⎥ LC −
− iC RL ⎬
⎢
CRo(max)
α2 ⎣ β
⎪⎭
⎦
35
Fig. 6: Plot between Ro and 81
for
(17)
â eq is continuous and hence 0< â eq < 1.
Comparing Eq. (9) and (10) and mapping the
equivalent control function onto the duty cycle function,
we get:
(15)
Vcon = − λ1ic + λ2 (Vref − βVo ) + λ3βVo
also
α
( R − RL )
βVi − LC 3 (Vref − β Vo ) − βVo o
α1
α2
Ro
<
α2
βLic
Vramp = β Vi
RL ⎤
⎡ 1
+⎢
+
CRO
L ⎥⎦
⎣
(18)
(19)
where
⎛ α1
λ1 = βL⎜
⎝ α2
for
⎧ ⎡
⎫
RL ⎤ α3
⎪Vo ⎢1 −
⎪
⎥+
⎪⎪ ⎢⎣ Ro(max) ⎥⎦ α 2
⎪⎪
Vi(min) ≥ 2 ⎨
⎬ (16)
⎤
⎪⎡ Vref
⎪
LiC
− ic RL ⎪
− Vo ⎥ LC −
⎪⎢
CR
β
⎪⎩⎣
⎪⎭
o(max)
⎦
C
20
15
Load Ro (Ω)
Fig. 5: Plot between Ro and 83
The range of input and loading conditions is
considered and the modified existence condition is
given as:
⎛
⎞
RL ⎞
α ⎛ Vref
⎟
LC 3 ⎜
−Vo ⎟ +Vo ⎜⎜1−
⎟
R
α2 ⎝ β
⎠
⎝
o(max) ⎠
10
5
and
⎛
−
α
R ⎞
1
− L ⎟ , λ2 = 3 LC
RoC
L⎠
α2
λ3 = ⎜ 1 −
⎝
RL ⎞
⎟
R0 ⎠
Variation of 81 and 83 with variations in the load is shown
in Fig. 6 and 5 respectively. These figures show that the
variation of 81 and 83 for 96.77% of load is only -11.15
and 11.65%, respectively. 82 remains constant irrespective
of the variations in the load. Thus, the control signal does
not undergo noticeable changes for variations in the load.
Step 6: Derivation of control equations using
equivalent control method: In the invariance
condition, Ö = 0, substituting â- â eq, we get:
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Res. J. Appl. Sci. Eng. Technol., 4(4): 342-349, 2012
20
26
18V
33V
30V
24V
13V
24
15
22
25
20
10
18
5
16
5.5
6.0
0
0.4
0.2
X10-4sec
0.6
0.8
(a)
Fig. 7: Output response of a PID controlled buck converter for
various inputs
11.86
Inductor current
Capacitor current
2.0
7.0
6.5
0
11.85
1184
11.83
11.82
1.5
1.0
11.81
0.5
11.79
11.8
11.78
0.0
5.5
6.5
6.0
7.0
X10-4sec
-0.5
0
22
24
26
-4
(b)
28
Fig. 9: Dynamic response of the PID controlled buck
converter to step input change from 24 to 18 V (a)
Input voltage (b) Output response
Fig. 8: Inductor and capacitor current waveforms
RESULTS AND DISCUSSION
11.94
PID controller: Figure 7-10 illustrates the results
provided by the computer simulation of a PID controlled
Buck converter using Matlab-Simulink.
Figure 7 shows the output responses of the converter
when it subjected to various input voltages. It can be
noticed that as the input voltage decreases from 33 to 13
V, the peak overshoot as well as the settling time of the
converter decreases. The inductor and capacitor current
waveforms of the converter under continuous conduction
mode are shown in Fig. 8. Figure 9 shows that when the
input voltage is changed from 24 to 18V at 0.6 ms, we can
infer that the system takes 0.09 ms to settle at a new
steady state value which is less than the initial steady state
value by 0.04 V. Figure 10 shows the dynamic response
of the converter for a load step change from 6 to 25S. It
is clear that the system takes 0.058 ms to settle at a new
steady state point which is 0.008 V greater than its steady
state value.
11.92
11.90
11.88
11.86
11.84
11.82
5.8
6.0
6.2
6.4
6.6
6.8
-5
Fig. 10: Dynamic response of the PID controlled buck
converter to load step change from 6 to 25S
waveforms of the converter under continuous conduction
mode are shown in Fig. 12 which is similar to that of the
waveforms of a PID controlled converter. When the input
voltage is changed from 24 to 18 V at 0.4 ms, (Fig. 13),
we can infer that the system takes 0.02 ms to settle at a
new steady state value which is less than the initial steady
state value by 0.6 :V (Fig. 13) which is a very negligible
value when compared to that of the PID controller.
SMC waveforms: Figure 11-15 illustrates the results
provided by the computer simulation of a PID based SM
controlled Buck converter using Matlab - Simulink.
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Res. J. Appl. Sci. Eng. Technol., 4(4): 342-349, 2012
15V
33V
30V
24V
20
13V
12.05
12.04
12.03
15
12.02
25
12.01
10
12.00
11.99
5
11.98
0
0
2
1
3
2.5
X10-4sec
3.5
X10-4 sec
Fig. 14: Dynamic response of the PID based SMC controlled
buck converter to load step change from 6 to 25S
Fig. 11: Output response of a PID based SMC controlled buck
converter for various inputs
PID controller
Inductor current
Capacitor current
2.5
3
20
2.0
SM controller
15
1.5
25
1.0
10
0.5
5
0.0
0
-0.5
0
2.4
2.8
2.6
3.0
0.2
0.4
0.6
X10-4sec
0.8
X10-4sec
Fig. 15: Output response of PID based SMC versus PID
controllers
Fig. 12: Inductor and capacitor current waveforms
26
SMC
PID
12.05
24
O utput voltage (VO)
22
20
18
16
3.2
3.4
3.6
3.8
4.0
4.2
4.4
X10-4sec
12.00
11.95
11.90
11.85
11.80
11.75
(a)
12
11.992
14
16
18 20 22
24
Input voltage (Vt)
26
28
30
Fig. 16: Variation of output with variation of input
11.900
Table 2: Comparison between PID and PID based SMC Buck Converter
Parameters
PID control
PID based SMC
Settling time
4.7×10G4s
1.84×10G4s
Maximum peak overshoot
6.22 V
5.253 V
Steady state error
0.16 V
0.009 V
11.988
11.966
11.964
11.962
3.2
3.4
3.6
3.8
4.0
4.2
When there is a load step change from 6 to 25S, the
system takes 0.035 ms to settle with negligible steady
state error (Fig. 14).
Figure 15 shows the output response of a PID based
SMC versus PID controller. It can be inferred from the
figure that the SMC response has much less settling time
than that of the PID controlled Buck converter response.
4.4
X10-1sec
(b)
Fig. 13: Dynamic response of the PID controlled buck
converter to step input change from 24 to 18 V at 0.4
ms (a) Input voltage (b) Output response
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Res. J. Appl. Sci. Eng. Technol., 4(4): 342-349, 2012
Moreover, the maximum peak overshoot and steady state
error is more for the latter when compared with the
former. When subjected to sudden line and load variation,
the PID based SMC settles at a much less time as
compared to that of a PID controller.
Table 2 gives a comparison of the performance
parameters of the PID controlled Buck converter and PID
based SMC controlled Buck Converter.
Figure 16 shows the variation of output with variation
in input for both converters. It can be inferred that when
there is 56.67% variation in the input, the PID controller
shows a variation of 1.072%, whereas a PID based SMC
shows a variation of only 0.192%.
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Mummadi, V., 2004. Signal flow graph modeling and
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Electr. Syst., 40(1): 259-271.
Perry, G., G. Feng, Y.F. Liu and P.C. Sen, 2007. Design
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Prodic, A.M., 2002. Design of a digital PID regulator
based on look-up Tables for control of high
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CONCLUSION
The design and analysis of a dc-dc Buck converter
operating in continuous conduction mode with
Proportional-Integral-Derivative control and PID based
Sliding Mode Control (SMC) is studied in detail in this
paper. The converter employing these two controllers is
subjected to sudden line variation as well as load
variation. Analysis shows that the PID controller relies
more on the operating point whereas the PID based SMC
is much robust to small-signal and large variation from
the operating point. Moreover the PID based SMC
produces negligible steady state error and settles with a
much less settling time than the conventional linear PID
controller.
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