Tentamen i kursen Datorarkitektur - TDTS 52, 2000-06-06, kl. 8-12

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TEKNISKA HÖGSKOLAN I LINKÖPING

Tentamen i kursen

Datorarkitektur - TDTS 52

2000-06-06, kl. 8-12

Hjälpmedel:

Inga.

Poänggränser:

Maximal poäng är 30. Rapporten om fallstudierna ger maximalt 10 poäng.

För godkänt krävs sammanlagt 22 poäng.

Resultat anslås:

Senast 2000-06-22 på IDAs anslagstavla för tentamensresultat.

Jourhavande lärare:

Erik Larsson, tel 28 4046

Good luck !!!

Tentamen i kursen Datorarkitektur - TDTS 52, 2000-06-06, kl. 8-12

Du kan skriva på svenska eller engelska!

1.

a) b)

Which are the basic elements of a memory hierarchy? Illustrate by a figure.

Show how a memory reference, starting with a virtual address, is solved:

1. How the virtual address is transformed into a physical one?

2. How the memory access is solved, considering a cache memory with direct mapping?

(4p)

2.

What means a master and a slave in the context of system buses? Why do we need bus arbitration?

(2p)

3.

Memory-mapped and isolated Input/Output: what is the difference and how do they work?

(2p)

4.

Consider the following statement (in Pascal, for example):

X := A*B - C*(D + E)

Show how this statement can be coded in assembly language, as a sequence of 3 - address and 2 - address instructions.

(2p)

5.

a) b)

Explain: - indexed addressing;

- indexed addressing with autoincrement and autodecrement.

The following instruction sequence counts the number of non-zero elements in a table which holds N integers:

NEXTEL

MOVE

MOVE

COMP

BEZ

#0, R2

#0, R0

#0, TABLE[R2]

ISZERO initialize table index initialize counter test current element

ISZERO

ADD

ADD

COMP

BNZ

MOVE

#1, R0

#1, R2

R2, N

NEXTEL

R0, NRNONZERO increment counter increment table index end of table?

store counter

Modify the sequence above so that you use indexing with autoincrement.

(3p)

Tentamen i kursen Datorarkitektur - TDTS 52, 2000-06-06, kl. 8-12

Du kan skriva på svenska eller engelska!

6.

The PowerPC has a simple unconditional branch instruction for subroutine call, which saves the return address into a so called “link register”. What is the disadvantage of this simple solution? How is it solved in other architectures?

(2p)

7.

Dynamic branch prediction with a two-bit scheme. How does it work?

Illustrate with the case of a loop like the one below:

LOOP

- - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - -

BNZ LOOP

- - - - - - - - - - - - - - - -

(3p)

8.

Branch history table: what does it contain and how is it used?

(2p)

9.

The design of RISC architectures is based on certain characteristics of currently used programs. Enumerate at least five such characteristics.

(2p)

10. What is register renaming? How does it improve the performance of superscalar computers?

Give an example.

(3p)

11. What is the advantage of a CPU architecture with three internal buses, compared to one with one single internal bus? Demonstrate the advantage by showing how the following operation is executed: R1

R2 + R3.

(3p)

12. What is a vector processor? Draw a block diagram.

(2p)

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