Tentamen i kursen Embedded Systems Design - TDDI08, 2014-03-22, kl.... Du kan skriva på svenska eller engelska! LINKÖPINGS TEKNISKA HÖGSKOLA

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LINKÖPINGS TEKNISKA HÖGSKOLA
Tentamen i kursen
Embedded Systems Design - TDDI08, 2014-03-22, kl. 14-18
Institutionen
för datavetenskap
Du
kan
skriva
på
svenska
eller engelska!
Petru Eles
Tentamen i kursen
Embedded Systems Design - TDDI08
2014-03-22, kl. 14-18
Hjälpmedel:
Supporting material:
Engelsk ordbok.
English dictionary.
Poänggränser:
Points:
Maximal poäng är 30.
För godkänt krävs sammanlagt
16 poäng.
Maximum points: 30.
In order to pass the exam you need a
total of minimum 16 points.
Jourhavande lärare:
Petru Eles, tel. 0703681396
Good luck !!!
Tentamen i kursen Embedded Systems Design - TDDI08, 2014-03-22, kl. 14-18
Du kan skriva på svenska eller engelska!
1.
Consider an application modelled as the task graph below. Each task, when activated, consumes one message on each input edge and generates, at termination, one message on each
output edge. The task graph is executed on the architecture shown in the figure. Execution
times of the tasks, when executed on the corresponding processor, are shown in the table. All
messages transmitted over the bus, between tasks mapped on different processors, consume 2
time units to reach the destination. Communication between tasks mapped to the same processor is considered to not consume any time.
Propose an efficient task mapping (indicate on which processor each task is executed) and a
corresponding static (nonpreemptive) schedule for the application. Illustrate your schedule as
a Gantt chart (similar to the way we captured schedules in Lecture 1&2).
Try to achieve a maximum delay (the time interval between the start of T1 and the finishing
of T7) of 46 time units!
(3p)
WCET
T1
Task
T2
T4
T5
µp1
µp2
Bus
T3
T6
T7
µp1
µp2
T1
5
6
T2
7
9
T3
5
6
T4
8
10
T5
10
11
T6
17
21
T7
10
14
2.
Give an example and show how determinism is lost with a GALS model as opposed to a synchronous FSM.
(2p)
3.
Define Kahn process networks.
Show by an example how determinism is guaranteed with Kahn process networks.
Transform the example and show that a more general dataflow network, which is not a Kahn
process network, does not guarantee determinism.
(3p)
Tentamen i kursen Embedded Systems Design - TDDI08, 2014-03-22, kl. 14-18
Du kan skriva på svenska eller engelska!
4.
Consider the synchronous dataflow graph depicted below.
a) Find the (minimum) number of firings, for each task, during one period.
b) Elaborate a static schedule (a sequence of task executions that can be repeated in a cycle).
A
8
C
2
2
2
1
2
1
D
2
2
B
1
(3p)
5.
a) Are Petri Net models deterministic?
b) Consider the model in Fig 1a). Can the place S eventually be marked? Is it guaranteed to
be marked?
c) Consider the model in Fig. 1b). Starting with the marking in the figure, which is (are) the
possible next state(s) of the system? Can the place S eventually be marked? Is it guaranteed
to be marked?
(3p)
S
Fig. 1a
6.
S
Fig. 1b
Timed automata are a particular (the simplest) form of hybrid automata. Give an example of
a timed automata model of your choice. Explain the model. Specify the same model as
hybrid automata.
Tentamen i kursen Embedded Systems Design - TDDI08, 2014-03-22, kl. 14-18
Du kan skriva på svenska eller engelska!
(3p)
7.
How does a discrete event simulator work?
Illustrate by a flow-graph.
(2p)
8.
Describe a simple design flow for processor specialization. Illustrate also by a figure.
Comment on the design tools you need.
(2p)
9.
We have introduced Systems on Chip with a dynamically reconfigurable datapath; this
datapth can be reconfigured to act as an accelerator for the actual program running on the
processor. What are the main steps for compiling the source code for such a system? What
will result as the outcome of this compilation?
(2p)
10. Illustrate by a diagram the trade-off energy consumption vs. flexibility for ASIC, FPGA,
ASIP, and general-purpose processor.
(2p)
11. What does it mean by IP (core) based design? What types of cores can you choose from?
Comment on each of them.
(2p)
12. a) What is the basic principle for task scheduling on DVS processors?
b) What is the problem if we consider particularities, concerning power consumption, of
individual tasks?
c) How do we solve the problem that only discrete voltage levels are available?
d) Discuss what the problems are if leakage energy is ignored.
(3p)
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