18-447
Computer Architecture
Lecture 6: Multi-cycle Microarchitectures
Prof. Onur Mutlu
Carnegie Mellon University
Spring 2013, 1/28/2013
Reminder: Homeworks

Homework 1



Due today, midnight
Turn in via AFS (hand-in directories)
Homework 2


Will be assigned later today. Stay tuned…
ISA concepts, ISA vs. microarchitecture, microcoded machines
2
Reminder: Lab Assignment 1

Due this Friday (Feb 1), at the end of Friday lab
A functional C-level simulator for a subset of the MIPS ISA

Study the MIPS ISA Tutorial

TAs will continue to cover this in Lab Sessions this week

3
Lookahead: Lab Assignment 2

Lab Assignment 1.5



Verilog practice
Not to be turned in
Lab Assignment 2




Due Feb 15
Single-cycle MIPS implementation in Verilog
All labs are individual assignments
No collaboration; please respect the honor code
4
Lookahead: Extra Credit for Lab Assignment 2




Complete your normal (single-cycle) implementation first,
and get it checked off in lab.
Then, implement the MIPS core using a microcoded
approach similar to what we will discuss in class.
We are not specifying any particular details of the
microcode format or the microarchitecture; you can be
creative.
For the extra credit, the microcoded implementation should
execute the same programs that your ordinary
implementation does, and you should demo it by the
normal lab deadline.
5
Readings for Today

P&P, Revised Appendix C



P&H, Appendix D


Microarchitecture of the LC-3b
Appendix A (LC-3b ISA) will be useful in following this
Mapping Control to Hardware
Optional

Maurice Wilkes, “The Best Way to Design an Automatic
Calculating Machine,” Manchester Univ. Computer Inaugural
Conf., 1951.
6
Lookahead: Readings for A Next Lecture

Pipelining

P&H Chapter 4.5-4.8
7
Review of Last Lecture: Single-Cycle Uarch


What phases of the instruction processing cycle does the
MIPS JAL instruction exercise?
How many cycles does it take to process an instruction in
the single-cycle microarchitecture?


What is the difference between datapath and control logic?


What determines the clock cycle time?
What about combinational vs. sequential control?
What is the semantics of a delayed branch?

Why this is so will become clear when we cover pipelining
8
Review: Instruction Processing “Cycle”



Instructions are processed under the direction of a “control
unit” step by step.
Instruction cycle: Sequence of steps to process an instruction
Fundamentally, there are six phases:

Fetch
Decode
Evaluate Address
Fetch Operands
Execute
Store Result

Not all instructions require all six stages (see P&P Ch. 4)





9
Review: Datapath vs. Control Logic


Instructions transform Data (AS) to Data’ (AS’)
This transformation is done by functional units

Units that “operate” on data

These units need to be told what to do to the data

An instruction processing engine consists of two components

Datapath: Consists of hardware elements that deal with and
transform data signals




functional units that operate on data
hardware structures (e.g. wires and muxes) that enable the flow of
data into the functional units and registers
storage units that store data (e.g., registers)
Control logic: Consists of hardware elements that determine
control signals, i.e., signals that specify what the datapath
elements should do to the data
10
A Note: How to Make the Best Out of 447?

Do the readings





Do the assignments early



P&P Appendixes A and C
Wilkes 1951 paper
Today’s lectures will be easy to understand if you read these
And, you can ask more in-depth questions and learn more
You can do things for extra credit if you finish early
We will describe what to do for extra credit
Study the material and buzzwords daily


Lecture notes, videos
Buzzwords  take notes during class
11
Today’s Agenda

Finish single-cycle microarchitectures

Critical path

Microarchitecture design principles

Performance evaluation primer

Multi-cycle microarchitectures

Microprogrammed control
12
Review: The Full Single-Cycle Datapath
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
Z e ro
bcond
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
Read
d a ta
1
M
u
x
0
32
S ig n
e x te n d
ALU
c o n tro l
ALU operation
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier.
ALL RIGHTS RESERVED.]
13
JAL, JR, JALR omitted
Single-Cycle Control Logic
14
Single-Cycle Hardwired Control

As combinational function of Inst=MEM[PC]
31
21
16
11
6
0
0
rs
rt
rd
shamt
funct
6-bit
5-bit
5-bit
5-bit
5-bit
6-bit
31
26
21
16
0
opcode
rs
rt
immediate
6-bit
5-bit
5-bit
16-bit
31

26
26
0
opcode
immediate
6-bit
26-bit
R-type
I-type
J-type
Consider
 All R-type and I-type ALU instructions
 LW and SW
 BEQ, BNE, BLEZ, BGTZ
 J, JR, JAL, JALR
15
Single-Bit Control Signals
When De-asserted
RegDest
ALUSrc
MemtoReg
RegWrite
When asserted
Equation
GPR write select
according to rt, i.e.,
inst[20:16]
GPR write select
according to rd, i.e.,
inst[15:11]
opcode==0
2nd ALU input from 2nd
GPR read port
2nd ALU input from sign- (opcode!=0) &&
extended 16-bit
(opcode!=BEQ) &&
immediate
(opcode!=BNE)
Steer ALU result to GPR
write port
steer memory load to
GPR wr. port
opcode==LW
GPR write disabled
GPR write enabled
(opcode!=SW) &&
(opcode!=Bxx) &&
(opcode!=J) &&
(opcode!=JR))
16
JAL and JALR require additional RegDest and MemtoReg options
Single-Bit Control Signals
When De-asserted
MemRead
MemWrite
Equation
Memory read disabled
Memory read port
return load value
opcode==LW
Memory write disabled
Memory write enabled
opcode==SW
According to PCSrc2
next PC is based on 26bit immediate jump
target
(opcode==J) ||
next PC is based on 16bit immediate branch
target
(opcode==Bxx) &&
PCSrc1
next PC = PC + 4
PCSrc2
When asserted
(opcode==JAL)
“bcond is satisfied”
17
JR and JALR require additional PCSrc options
ALU Control

case opcode
‘0’  select operation according to funct
‘ALUi’  selection operation according to opcode
‘LW’  select addition
‘SW’  select addition
‘Bxx’  select bcond generation function
__  don’t care

Example ALU operations


ADD, SUB, AND, OR, XOR, NOR, etc.
bcond on equal, not equal, LE zero, GT zero, etc.
18
R-Type ALU
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
1
0
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
1
M
u
x
0
32
S ig n
e x te n d
funct ALU operation
ALU
c o n tro l
0
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
19
I-Type ALU
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
1
0
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
1
M
u
x
0
32
S ig n
e x te n d
opcodeALU operation
ALU
c o n tro l
0
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004
Elsevier. ALL RIGHTS RESERVED.]
20
LW
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
1
0
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
1
M
u
x
0
32
S ig n
e x te n d
Add
ALU
c o n tro l
ALU operation
1
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004
Elsevier. ALL RIGHTS RESERVED.]
21
SW
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
*
M
u
x
1
0
1
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
1
M
u
x
*
0
32
S ig n
e x te n d
Add
ALU
c o n tro l
ALU operation
0
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004
Elsevier. ALL RIGHTS RESERVED.]
22
Branch Not Taken
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
*
1
In s tr u c tio n [1 5 – 0 ]
0
0
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
16
1
M
u
x
*
0
32
S ig n
e x te n d
bcondALU operation
ALU
c o n tro l
0
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004
Elsevier. ALL RIGHTS RESERVED.]
23
Branch Taken
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
*
1
In s tr u c tio n [1 5 – 0 ]
0
0
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
16
1
M
u
x
*
0
32
S ig n
e x te n d
bcondALU operation
ALU
c o n tro l
0
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
24
Jump
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
*
A LU
re s u lt
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
*
1
In s tr u c tio n [1 5 – 0 ]
0
bcond
Z e ro
ALU
0
M
u
x
*
W rite
d a ta
ALU
re s u lt
16
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
1
M
u
x
*
0
32
S ig n
e x te n d
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
0
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
*
ALU
c o n tro l
ALU operation
0
25
What is in That Control Box?

Combinational Logic  Hardwired Control



Idea: Control signals generated combinationally based on
instruction
Necessary in a single-cycle microarchitecture…
Sequential Logic  Sequential/Microprogrammed Control


Idea: A memory structure contains the control signals
associated with an instruction
Control Store
26
Evaluating the Single-Cycle
Microarchitecture
27
A Single-Cycle Microarchitecture

Is this a good idea/design?

When is this a good design?

When is this a bad design?

How can we design a better microarchitecture?
28
A Single-Cycle Microarchitecture: Analysis

Every instruction takes 1 cycle to execute


How long each instruction takes is determined by how long
the slowest instruction takes to execute


CPI (Cycles per instruction) is strictly 1
Even though many instructions do not need that long to
execute
Clock cycle time of the microarchitecture is determined by
how long it takes to complete the slowest instruction

Critical path of the design is determined by the processing
time of the slowest instruction
29
What is the Slowest Instruction to Process?









Let’s go back to the basics
All six phases of the instruction processing cycle take a single
machine clock cycle to complete
Fetch
1. Instruction fetch (IF)
Decode
2. Instruction decode and
register operand fetch (ID/RF)
Evaluate Address
3. Execute/Evaluate memory address (EX/AG)
Fetch Operands
4. Memory operand fetch (MEM)
Execute
5. Store/writeback result (WB)
Store Result
Do each of the above phases take the same time (latency)
for all instructions?
30
Single-Cycle Datapath Analysis

Assume




memory units (read or write): 200 ps
ALU and adders: 100 ps
register file (read or write): 50 ps
other combinational logic: 0 ps
steps
IF
ID
EX
MEM
mem
WB
RF
Delay
resources
mem
RF
ALU
R-type
200
50
100
50
400
I-type
200
50
100
50
400
LW
200
50
100
200
50
600
SW
200
50
100
200
Branch
200
50
100
Jump
200
550
350
200
31
Let’s Find the Critical Path
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
Read
d a ta
1
M
u
x
0
32
S ig n
e x te n d
ALU
c o n tro l
ALU operation
In s tru c tio n [5 – 0 ]
[Based on original figure from P&H CO&D, COPYRIGHT 2004
Elsevier. ALL RIGHTS RESERVED.]
32
R-Type and I-Type ALU
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
100ps
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
100ps
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
Read
a d d re s s
R ea d
re g is te r 1
200ps
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
W rite
d a ta
250ps
0
400ps
M
u
x
1
bcond
Z e ro
ALU
ALU
re s u lt
A d d re s s
350ps
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
Read
d a ta
D a ta
m e m o ry
1
M
u
x
0
32
S ig n
e x te n d
ALU
c o n tro l
ALU operation
In s tru c tio n [5 – 0 ]
[Based on original figure from P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
33
LW
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
100ps
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
100ps
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
Read
a d d re s s
R ea d
re g is te r 1
200ps
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
In s tr u c tio n [1 5 – 0 ]
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
250ps
0
M
u
x
600ps
W rite
d a ta
1
bcond
Z e ro
ALU
ALU
re s u lt
A d d re s s
350ps
W rite
d a ta
16
Read
d a ta
D a ta
m e m o ry
550ps
1
M
u
x
0
32
S ig n
e x te n d
ALU
c o n tro l
ALU operation
In s tru c tio n [5 – 0 ]
[Based on original figure from P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
34
SW
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
100ps
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
100ps
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
Read
a d d re s s
R ea d
re g is te r 1
200ps
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
250ps
0
M
u
x
W rite
d a ta
1
bcond
Z e ro
ALU
ALU
re s u lt
A d d re s s
350ps 550ps
D a ta
m e m o ry
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
Read
d a ta
1
M
u
x
0
32
S ig n
e x te n d
ALU
c o n tro l
ALU operation
In s tru c tio n [5 – 0 ]
[Based on original figure from P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
35
Branch Taken
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
100ps
0
1
200ps
M
u
x
M
u
x
A LU
re s u lt
1
0
Add
Add
4
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
350ps
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
Read
a d d re s s
R ea d
re g is te r 1
200ps
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
350ps
250ps
0
M
u
x
W rite
d a ta
bcond
Z e ro
ALU
ALU
re s u lt
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
Read
d a ta
1
M
u
x
0
32
S ig n
e x te n d
ALU
c o n tro l
ALU operation
In s tru c tio n [5 – 0 ]
[Based on original figure from P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
36
Jump
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
100ps
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
200ps
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
Read
a d d re s s
R ea d
re g is te r 1
200ps
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
Read
d a ta
1
M
u
x
0
32
S ig n
e x te n d
ALU
c o n tro l
ALU operation
In s tru c tio n [5 – 0 ]
[Based on original figure from P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
37
What About Control Logic?

How does that affect the critical path?

Food for thought for you:


Can control logic be on the critical path?
A note on CDC 5600: control store access too long…
38
What is the Slowest Instruction to Process?

Memory is not magic

What if memory sometimes takes 100ms to access?


Does it make sense to have a simple register to register
add or jump to take {100ms+all else to do a memory
operation}?
And, what if you need to access memory more than once to
process an instruction?


Which instructions need this?
Do you provide multiple ports to memory?
39
Single Cycle uArch: Complexity

Contrived


Inefficient




All instructions run as slow as the slowest instruction
Must provide worst-case combinational resources in parallel as required
by any instruction
Need to replicate a resource if it is needed more than once by an
instruction during different parts of the instruction processing cycle
Not necessarily the simplest way to implement an ISA


All instructions run as slow as the slowest instruction
Single-cycle implementation of REP MOVS, INDEX, POLY?
Not easy to optimize/improve performance


Optimizing the common case does not work (e.g. common instructions)
Need to optimize the worst case all the time
40
Microarchitecture Design Principles

Critical path design


Find the maximum combinational logic delay and decrease it
Bread and butter (common case) design

Spend time and resources on where it matters



Common case vs. uncommon case
Balanced design



i.e., improve what the machine is really designed to do
Balance instruction/data flow through hardware components
Balance the hardware needed to accomplish the work
How does a single-cycle microarchitecture fare in light of
these principles?
41
Multi-Cycle Microarchitectures
42
Multi-Cycle Microarchitectures


Goal: Let each instruction take (close to) only as much time
it really needs
Idea


Determine clock cycle time independently of instruction
processing time
Each instruction takes as many clock cycles as it needs to take


Multiple state transitions per instruction
The states followed by each instruction is different
43
Remember: The “Process instruction” Step

ISA specifies abstractly what A’ should be, given an
instruction and A

It defines an abstract finite state machine where



From ISA point of view, there are no “intermediate states”
between A and A’ during instruction execution


State = programmer-visible state
Next-state logic = instruction execution specification
One state transition per instruction
Microarchitecture implements how A is transformed to A’


There are many choices in implementation
We can have programmer-invisible state to optimize the speed of
instruction execution: multiple state transitions per instruction


Choice 1: AS  AS’ (transform A to A’ in a single clock cycle)
Choice 2: AS  AS+MS1  AS+MS2  AS+MS3  AS’ (take multiple
clock cycles to transform AS to AS’)
44
Multi-Cycle Microarchitecture
AS = Architectural (programmer visible) state
at the beginning of an instruction
Step 1: Process part of instruction in one clock cycle
Step 2: Process part of instruction in the next clock cycle
…
AS’ = Architectural (programmer visible) state
at the end of a clock cycle
45
Benefits of Multi-Cycle Design

Critical path design


Bread and butter (common case) design


Can keep reducing the critical path independently of the worstcase processing time of any instruction
Can optimize the number of states it takes to execute “important”
instructions that make up much of the execution time
Balanced design

No need to provide more capability or resources than really
needed


An instruction that needs resource X multiple times does not require
multiple X’s to be implemented
Leads to more efficient hardware: Can reuse hardware components
needed multiple times for an instruction
46
Performance Analysis

Execution time of an instruction


Execution time of a program



Sum over all instructions [{CPI} x {clock cycle time}]
{# of instructions} x {Average CPI} x {clock cycle time}
Single cycle microarchitecture performance



{CPI} x {clock cycle time}
CPI = 1
Clock cycle time = long
Multi-cycle microarchitecture performance

CPI = different for each instruction


Average CPI  hopefully small
Clock cycle time = short
Now, we have
two degrees of freedom
to optimize independently
47
An Aside: CPI vs. Frequency

CPI vs. Clock cycle time

At odds with each other



Reducing one increases the other for a single instruction
Why?
Average CPI can be amortized/reduced via concurrent
processing of multiple instructions


The same cycle is devoted to processing multiple instructions
Example: Pipelining, superscalar execution
48
A Multi-Cycle Microarchitecture
A Closer Look
49
How Do We Implement This?

Maurice Wilkes, “The Best Way to Design an Automatic
Calculating Machine,” Manchester Univ. Computer
Inaugural Conf., 1951.

The concept of microcoded/microprogrammed machines

Realization



One can implement the “process instruction” step as a finite
state machine that sequences between states and eventually
returns back to the “fetch instruction” state
A state is defined by the control signals asserted in it
Control signals for the next state determined in current state
50
The Instruction Processing Cycle






Fetch
Decode
Evaluate Address
Fetch Operands
Execute
Store Result
51
A Basic Multi-Cycle Microarchitecture

Instruction processing cycle divided into “states”


A multi-cycle microarchitecture sequences from state to
state to process an instruction


A stage in the instruction processing cycle can take multiple states
The behavior of the machine in a state is completely determined by
control signals in that state
The behavior of the entire processor is specified fully by a
finite state machine

In a state (clock cycle), control signals control


How the datapath should process the data
How to generate the control signals for the next clock cycle
52
Microprogrammed Control Terminology

Control signals associated with the current state


Act of transitioning from one state to another



Determining the next state and the microinstruction for the
next state
Microsequencing
Control store stores control signals for every possible state


Microinstruction
Store for microinstructions for the entire FSM
Microsequencer determines which set of control signals will
be used in the next clock cycle (i.e., next state)
53
What Happens In A Clock Cycle?

The control signals (microinstruction) for the current state
control





Processing in the data path
Generation of control signals (microinstruction) for the next
cycle
See Supplemental Figure 1 (next slide)
Datapath and microsequencer operate concurrently
Question: why not generate control signals for the current
cycle in the current cycle?



This will lengthen the clock cycle
Why would it lengthen the clock cycle?
See Supplemental Figure 2
54
A Clock Cycle
55
A Bad Clock Cycle!
56
A Simple LC-3b Control and Datapath
57
What Determines Next-State Control Signals?

What is happening in the current clock cycle

See the 9 control signals coming from “Control” block


The instruction that is being executed


IR[15:11] coming from the Data Path
Whether the condition of a branch is met, if the instruction
being processed is a branch


What are these for?
BEN bit coming from the datapath
Whether the memory operation is completing in the current
cycle, if one is in progress

R bit coming from memory
58
A Simple LC-3b Control and Datapath
59
The State Machine for Multi-Cycle Processing

The behavior of the LC-3b uarch is completely determined by




the 35 control signals and
additional 7 bits that go into the control logic from the datapath
35 control signals completely describe the state of the control
structure
We can completely describe the behavior of the LC-3b as a
state machine, i.e. a directed graph of


Nodes (one corresponding to each state)
Arcs (showing flow from each state to the next state(s))
60
An LC-3b State Machine



Patt and Patel, App C, Figure C.2
Each state must be uniquely specified
 Done by means of state variables
31 distinct states in this LC-3b state machine


Encoded with 6 state variables
Examples



State 18,19 correspond to the beginning of the instruction
processing cycle
Fetch phase: state 18, 19  state 33  state 35
Decode phase: state 32
61
18, 19
MAR <! PC
PC <! PC + 2
33
MDR <! M
R
R
35
IR <! MDR
32
RTI
To 8
1011
BEN<! IR[11] & N + IR[10] & Z + IR[9] & P
To 11
1010
[IR[15:12]]
ADD
To 10
BR
AND
DR<! SR1+OP2*
set CC
1
0
XOR
JMP
TRAP
To 18
DR<! SR1&OP2*
set CC
[BEN]
JSR
SHF
LEA
LDB
STW
LDW
STB
1
PC<! PC+LSHF(off9,1)
12
DR<! SR1 XOR OP2*
set CC
15
4
MAR<! LSHF(ZEXT[IR[7:0]],1)
To 18
[IR[11]]
0
R
To 18
PC<! BaseR
To 18
MDR<! M[MAR]
R7<! PC
22
5
9
To 18
0
28
1
20
R7<! PC
PC<! BaseR
R
21
30
PC<! MDR
To 18
To 18
R7<! PC
PC<! PC+LSHF(off11,1)
13
DR<! SHF(SR,A,D,amt4)
set CC
To 18
14
2
DR<! PC+LSHF(off9, 1)
set CC
To 18
MAR<! B+off6
6
7
MAR<! B+LSHF(off6,1)
3
MAR<! B+LSHF(off6,1)
MAR<! B+off6
To 18
29
MDR<! M[MAR[15:1]’0]
NOTES
B+off6 : Base + SEXT[offset6]
PC+off9 : PC + SEXT[offset9]
*OP2 may be SR2 or SEXT[imm5]
** [15:8] or [7:0] depending on
MAR[0]
R
31
R
DR<! SEXT[BYTE.DATA]
set CC
MDR<! SR
MDR<! M[MAR]
27
R
R
MDR<! SR[7:0]
16
DR<! MDR
set CC
M[MAR]<! MDR
To 18
To 18
R
To 18
24
23
25
17
M[MAR]<! MDR**
R
R
To 19
R
LC-3b State Machine: Some Questions

How many cycles does the fastest instruction take?

How many cycles does the slowest instruction take?

Why does the BR take as long as it takes in the FSM?

What determines the clock cycle?

Is this a Mealy machine or a Moore machine?
63