Datorarkitektur I Fö 11- 1 Datorarkitektur I Fö 11- 2 Let’s Have a Look into the CPU I/O n I/O 2 I/O 1 THE CONTROL UNIT System Bus 1. Why is a Control Unit Needed inside the CPU? Main Memory CPU 2. Microoperations and Control Signals 3. The Control Unit - Basic Tasks System Bus IR PC Control Unit Address Bus ALU Data Bus Registers 5. Microprogrammed Control Control Bus CPU 4. Hardwired Control Internal CPU Bus Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH Datorarkitektur I Fö 11- 3 Datorarkitektur I Fö 11- 4 Instruction Execution Let’s Have a Look into the CPU (cont’d) • • The CPU executes a sequence of instructions. The execution of an instruction is organized as an instruction cycle: it is performed as a succession of several steps; The question that has to be answered: • How are the elements inside the CPU and the interface to the external datapath controlled in order to work properly? Fetch instruction Execute instruction To perform this control, that’s the task of the Control Unit Petru Eles, IDA, LiTH • Each step is executed as a set of several microoperations. • The task performed by any microoperation falls in one of the following categories: - Transfer data from one register to another; - Transfer data from a register to an external interface (system bus); - Transfer data from an external interface to a register; - Perform an arithmetic or logic operation, using registers for input and output. Petru Eles, IDA, LiTH Datorarkitektur I Fö 11- 5 Datorarkitektur I Microoperations and Control Signals Instruction Execution (cont’d) Control signals PCin Status&Cond. Flags PC Control unit PCout MARin System bus MAR IRin MBRin Clock R0in Yin Examples: b) signals for adding content of Y to that of R0 (result in Z): R0out, Add, Zin IRout MBRout In order to allow the execution of a microoperation, one or several control signals have to be issued; they allow the corresponding data transfer and/or computation to be performed. a) signals for transferring content of register R0 to R1: R0out, R1in IR MBR Clear Y Fö 11- 6 c) signals for reading a memory location; address in R3: R3out, MARin, Read R0 Y R0out • Yout Add • XOR ALU Rn-1in Carry-in Zin Rn-1 The CPU executes an instruction as a sequence of control steps. In each control step one or several microoperations are executed. One clock pulse triggers the activities corresponding to one control step ⇒ for each clock pulse the control unit generates the control signals corresponding to the microoperations to be executed in the respective control step. Z Rn-1out Zout Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH Datorarkitektur I Fö 11- 7 Datorarkitektur I Fö 11- 8 Microoperations and Control Signals (cont’d) Microoperations and Control Signals (cont’d) instruction: ADD R1,R3 R1 ← R1 + R3 instruction: BR 1 2 3 4 5 6 PCout, MARin, Read, Clear Y, Carry-in, Add, Zin Zout, PCin MBRout, IRin R1out, Yin R3out, Add, Zin Zout, R1in, End instruction: ADD R1,(R3) fetch ins. PC←PC+1 Petru Eles, IDA, LiTH unconditional branch (with relative addressing - see lect. 5) 1 2 3 4 5 6 PCout, MARin, Read, Clear Y, Carry-in, Add, Zin Zout, PCin MBRout, IRin PCout, Yin (displacement-field)IRout, Add, Zin Zout, PCin, End R1 ← R1 + [R3] control steps and control signals: 1 2 3 4 5 6 7 target control steps and control signals: fetch ins. PC←PC+1 fetch ins. PC←PC+1 control steps and control signals: PCout, MARin, Read, Clear Y, Carry-in, Add, Zin Zout, PCin MBRout, IRin indirect addressing R3out, MARin, Read R1out, Yin MBRout, Add, Zin Zout, R1in, End Comments: • The first (three) control steps are identical for each instruction; they perform instruction fetch and increment the PC. The following steps depend on the actual instruction (stored in the IR). • If a control step issues a read, the value will be available in the MBR after one additional step. • Several microoperations can be performed in the same control step if they don’t conflict (for example, only one of them is allowed to output on the bus) Petru Eles, IDA, LiTH Datorarkitektur I Fö 11- 9 Datorarkitektur I Control Unit Control Unit (cont’d) The control unit is driven by the processor clock. The signals to be generated at a certain moment depend on: - the actual step to be executed; - the condition and status flags of the processor; - the actual instruction executed; - external signals received on the system bus (e.g. interrupt signals). IR Control unit Control signals on system bus Signals from system bus Clock • Petru Eles, IDA, LiTH Control signals internal to the CPU Status&Cond. Flags The basic task of the control unit: - for each instruction the control unit causes the CPU to go through a sequence of control steps; - in each control step the control unit issues a set of signals which cause the corresponding microoperations to be executed. • Fö 11- 10 Techniques for implementation of the control unit: 1. Hardwired control 2. Microprogrammed control Petru Eles, IDA, LiTH Datorarkitektur I Fö 11- 11 Datorarkitektur I Fö 11- 12 Hardwired Control Hardwired Control (cont’d) • In this case, the control unit is a combinatorial circuit; it gets a set of inputs (from IR, flags, clock, system bus) and transforms them into a set of control signals. IR Instruction decoder I2 I3 In T1 T2 Zin = T1 + T5 ⋅ (ADDreg + BR) + T6 ⋅ ADDreg_ind + . . . Generation of signal End: - step 6 of ADD with register addressing - step 7 of ADD with register-indirect addressing - step 6 of BR - ------------------End = T6 ⋅ (ADDreg + BR) + T7 ⋅ ADDreg_ind + . . . End Tn From system bus Encoder block (combinatorial signal generator) Status&Cond. Flags Clock Reset Step counter and decoder I1 Generation of signal Zin: - first step of all instructions (fetch instruction) - step 5 of ADD with register addressing - step 5 of BR - step 6 of ADD with register-indirect addressing - ------------------- Control signals Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH Datorarkitektur I Fö 11- 13 Datorarkitektur I Fö 11- 14 Control signals Control unit • Hardwired control provides highest speed. • RISCs are implemented with hardwired control. • If the instruction set becomes very complex (CISCs) implementing hardwired control is very difficult. In this case microprogrammed control units are used. Clock IR PC R0 In order to allow execution of register-to-register operations in a single clock cycle, RISCs (and other modern processors) use three-bus CPU structures (see following slide). Rn-1 ALU • Status&Cond. Flags Hardwired Control (cont’d) MBR MAR System bus Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH Datorarkitektur I Fö 11- 15 Datorarkitektur I Microprogrammed Control • • Microprogrammed Control Unit Status&Cond. Flags IR Address generator (AG) µPC Control store (CS) Microprogrammed control - basic idea: • All microroutines corresponding to the machine instructions are stored in the control store. • The control unit generates the sequence of control signals for a certain machine instruction by reading from the control store the CWs of the microroutine corresponding to the respective instruction. gen. addr INCR • Control word (CW): a sequence of Nsig bits, where Nsig is the total number of control signals; each bit in a CW corresponds to one control signal. Each control step during execution of an instruction defines a certain CW; it represents a combination of 1s and 0s corresponding to the active and nonactive control signals. Microroutine: a sequence of CWs corresponding to the control sequence of a machine instruction. An individual CW in a microroutine is called a microinstruction. Fö 11- 16 Clock The control unit is implemented just like another very simple CPU, inside the CPU, executing microroutines stored in the control store. Sequencer Signals from system bus IAB: Internal Address Bus Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH IAB Control buffer/ decoder (CB/D) end, end-fetch branch Control signals Datorarkitektur I Fö 11- 17 Datorarkitektur I Fö 11- 18 Control Store Organization Microroutine Executed for Conditional Branch Addr-fetch Addr-interr. Addr-instr0 Addr-instr1 Addr-instrn Control store ----------------------------------------end-fetch Fetch instruction ----------------------------------------branch addr-fetch Interrupt routine ----------------------------------------end Execute instr. code 0 ----------------------------------------end Execute instr. code 1 ----------------------------------------end Execute instr. code n A_fetch +1 +2 +3 A_CB +1 +2 +3 +4 +5 • • • The control store contains the microprogram (sometimes called firmware). Petru Eles, IDA, LiTH Fö 11- 19 Summary • • • • • • • • The control unit is in charge of coordinating the activities inside the CPU and the interaction with the outside. It is doing this by issuing in each clock cycle the appropriate control signals. A set of control signals activates the microoperations which have to be executed in a given control step. Control units can be implemented hardwired or microprogrammed. A hardwired control unit is a combinatorial circuit which gets a set of inputs and transforms them into a set of control signals. A microprogrammed control unit is implemented like another CPU inside the CPU. It executes microprogrammes stored in the control store. Each instruction of the microprogram practically represents the set of signals which the control unit has to issue in the respective control step. Hardwired controllers are faster then microprogrammed ones. They are used in all RISCs. If the instruction set is complex, hardwired controllers become too complicated. Therefore CISCs are implemented with microprogrammed controllers. Petru Eles, IDA, LiTH The microroutines contain, beside CWs, also branches which have to be interpreted by the microprogrammed controller. The sequencer is controlling the right execution sequence of microinstructions. The sequencer is a small control unit of the control unit. Petru Eles, IDA, LiTH Datorarkitektur I PCout, MARin, Read, Clear Y, Carry-in, Add, Zin Zout, PCin MBRout, IRin end-fetch this produces the jump to A_CB -------------branch to A_CB+2 if N set end PCout, Yin (displacement-field)IRout, Add, Zin Zout, PCin end