Topic 1
(3 students)
Hardware/Software Codesign of Embedded Systems: Specific Issues and Research Topics
Readings:
1. W. Wolf, “Hardware-Software Codesign of Embedded Systems”, Proceedings of the IEEE,
V82, No7, 1994.
2. G. De Micheli, R.K. Gupta, “Hardware-Software Codesign”, Proceedings of the IEEE, V85,
No3, 1997.
3. R. Ernst, “Codesign of Embedded Systems: Status and Trends”, IEEE Design&Test of Computers, V15, No2, 1998.
4. W. Wolf, “A Decade of Hardware/Software Codesign”, IEEE Computer, V36, No4, 2003.
5. A. Sangiovanni-Vincentelli, “Electronic-system design in the automobile industry“, IEEE
Micro, Volume 23, Issue 3, May-June 2003, Page(s):8 - 18.
Topic 2
(3 students)
Basic Models of Computation. A Comparative Study
Readings:
1. Luciano Lavagno, Alberto Sangiovanni-Vincentelli, Ellen Sentovich, “Models of Computation
for Embedded System Design”, Ahmed A. Jerraya and Jean Mermet eds.: System Level Synthesis, Kluwer 1999.
2. Edward Lee, Alberto Sangiovanni-Vincentelli, “A framework for Comparing Models of Computation”, IEEE Transactions on CAD, V17, No12, 1998
3. M. Sgroi, Luciano Lavagno, Alberto Sangiovanni-Vincentelli, “Formal models for embedded
system design”, IEEE Design & Test of Computers, Volume 17, Issue 2, April-June 2000,
Page(s):14 - 27.
4. K.D. Muller-Glaser et al., “Multiparadigm modeling in embedded systems design”, IEEE
Transactions on Control Systems Technology, Volume 12, Issue 2, March 2004 Page(s):279 292.
Topic 3
(3 students)
System Specification Languages. Multilanguage Specifications.
Readings:
1. Ahmed A. Jerraya, M. Romdhani, et al., “Multilanguage Specification for System Design”,
Ahmed A. Jerraya and Jean Mermet eds.: System Level Synthesis, Kluwer 1999.
2. Carlos Delgado Kloos, Simon Pickin, et al., “High-level Specification Languages for Embedded System Design”, Ahmed A. Jerraya and Jean Mermet eds.: System Level Synthesis, Kluwer 1999.
3. Bran Selic, “Turning clockwise: using UML in the real-time domain”, Communications of the
ACM, October, 1999.
4. P.G. Paulin, et al., “Parallel programming models for a multiprocessor SoC platform applied to
networking and multimedia”, EEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 14, Issue 7, July 2006 Page(s): 667 - 680.
5. K.D. Muller-Glaser et al., “Multiparadigm modeling in embedded systems design”, IEEE
Transactions on Control Systems Technology, V. 12, Issue 2, March 2004, Page(s):279 - 292.
Topic 4
(3 students)
Formal Verification Techniques with Emphasis on Model Checking
Readings:
1. Stephen Edwards, Luciano Lavagno, Edward Lee, Alberto Sangiovanni-Vincentelli, “Design of
Embedded Systems: Formal Models, Validation, Synthesis”, Proceedings of the IEEE, Vol85,
No3, 1997.
2. J.R. Burch, E.M.Clarke, K.L. McMillan, “Sequential Circuit Verification Using Symbolic
Model Checking”, Proc. DAC, 1990.
3. E.M. Clarke, O. Grumberg, D.A. Peled, “Model Checking”, MIT Press, 2000.
4. R. Alur, C. Courcoubetis, D. Dill, “Model-Checking for Real-Time Systems”, Proc 5th Symp.
on Logic in Comp. Science, 1990.
5. E.M. Clarke, J. M. Wing, “Formal methods: state of the art and future directions”, ACM Computing Surveys, Volume 28, Issue 4, 1996.
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Topic 5
(4 students)
Processors and Architectures for Embedded Systems
Readings:
1. Manfred Schlett, “Trends in Embedded Microprocessor Design”, IEEE Computer, August ‘98.
2. M.F. Jacome, “Design Challenges for New Application-Specific Processors”, IEEE Design &
Test of Computers, April-June 2000.
3. J.A. Fisher, “Customized Instruction-Sets for Embedded Processors”, Proc. DAC, 1999.
4. Yanbing Li, et al., “Hardware-Software Codesign of Embedded Reconfigurable Architectures”,
Proc. DAC, 2000.
5. M. Kaul, R. Vemuri, “Temporal Partitioning Combined with Design Space Exploration for
Latency Minimization of Run-Time Reconfigured Designs”, Proc. DATE 1999.
6. L. Benini, L, G. De Micheli, “Networks on chips: a new SoC paradigm”, IEEE Computer, Volume 35, Issue 1, Jan. 2002, Page(s):70 - 78.
7. L. Benini, and D. Bertozzi, “Network-on-chip architectures and design methods”, IEE Proceedings-Computers and Digital Techniques, V. 152, Issue 2, March 2005, Page(s):261 - 272.
Topic 6
(3 students)
Component and Platform-based Design
Readings:
1. K. Keutzer, et al. “System level Design: Orthogonalization of Concerns and Platform-Based
Design”, IEEE Transactions on CAD, V19, N12, 2000.
2. J Rowson, A Sangiovanni-Vincentelli, “Interface-based Design”, Proc. DAC, 1997.
3. A.M. Rincon et al.: “Core-Design and System-on-a-Chip Integration”, IEEE Design & Test of
Computers, October-December 1997.
4. A. Sangiovanni-Vincentelli, A. and G. Martin, “Platform-based design and software design
methodology for embedded systems“, IEEE Design & Test of Computers, Volume 18, Issue 6,
Nov.-Dec. 2001, Page(s):23 - 33.
5. A. Mihal, et al., “Developing architectural platforms: a disciplined approach“, IEEE Design &
Test of Computers, Nov.-Dec. 2002.
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Topic 7
(4 students)
Software Execution Time Estimation and Real-Time Scheduling
Readings:
1. Y.-T. S. Li, S. Malik, A. Wolfe, “Performance Estimation of Embedded Software with Instruction Cache Modeling”, ACM Transactions on Design Automation of Electronic Systems, V4,
N3, 1999.
2. J. Engblom, A. Ermedahl, M. Sjödin, J. Gustafsson, H. Hansson, “Worst-case execution-time
analysis for embedded real-time systems,” International Journal on Software Tools for Technology Transfer, vol. 4, nr. 4, pp. 437-455, 2003.
3. L. Thiele, R. Wilhelm, “Design for Timing Predictability,” Real-Time Systems, vol. 28, nr. 2/3,
pp. 157-177, 2004.
4. F. Balarin, L. Lavagno, L., et al. “Scheduling for embedded real-time systems”, IEEE Des. Test
Comput. V.15, issue 1, 1998.
5. G. Butazzo, “Rate monotonic vs. EDF: Judgment day”, Real-Time Syst. V. 29, No. 1, 2005.
6. N. Audsley, A. Burns, et al. “Fixed priority preemptive scheduling: an historical perspective”,
Real-Time Systems, Volume 8, Numbers 2-3 / March, 1995.
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Topic 8
(5 students)
System-Level Power/Energy Optimization
Readings:
1. G. De Micheli, L. Benini, A. Bogliolo, “Dynamic Power Management of Electronic Systems”,
Ahmed A. Jerraya and Jean Mermet eds.: System Level Synthesis, Kluwer 1999.
2. L. Benini, G. De Micheli, “System-Level Power Optimization: Techniques and Tools”, ACM
Transactions on Design Automation of Electronic Systems, V5, N2, 2000.
3. W. Fornaciari, P Gubian, et al., “Power Estimation of Embedded Systems: A Hardware/Software Codesign Approach”, IEEE Transactions on VLSI Systems, V6, N2, 1998.
4. T. Ishihara, H. Yasuura, “Voltage Scheduling Problem for Dynamically Variable Voltage Processors”, Proc. Int. Symp. on Low Power Electronics and Design, 1998
5. T. Okuma, T. Ishihara, H. Yasuura, “Real-Time Task Scheduling for a Variable Voltage Processor”, Proc. Int. Symp. on System Synthesis, 1998.
6. T. Okuma, T. Ishihara, H. Yasuura,, “Software Energy reduction Techniques for Variable-Voltage Processors”, IEEE Design & Test of Computers, March-April, 2001.
7. O.S. Unsal, I. Koren, “System-Level Power Aware Design Techniques in Real-Time Systems”,
Proceedings of the IEEE, V91, No7, 2003.
8. V. Venkatachalam, M. Franz, “Power reduction techniques for microprocessor systems“, ACM
Computing Surveys, Volume 37, Issue 3, 2005.
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Topic 9
(4 students)
Hardware/Software Codesign Environments
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•
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•
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The Cosyma System
The SpecSyn Environment
The POLIS Environment
The CoWare Environment
UltraSONIC Codesign Environment
Metropolis environment
Readings:
1. W. Wolfe, “Hardware/Software Co-synthesis Algorithms”, Ahmed A. Jerraya and Jean Mermet
eds.: System Level Synthesis, Kluwer 1999.
2. A. Österling, T. Benner, R. Ernst, et al., “The Cosyma System”, Jorgen Staunstrup and Wayne
Wolf eds.: Hardware/Software Co-Design: Principles and Practice, Kluwer 1997.
3. D. Gajski, et al.: “SpecSyn: An Environment Supporting the Specify-Explore-Refine Paradigm
for Hardware/Software System Design”, IEEE Transactions on VLSI Systems, V6, N1, 1998.
4. M. Chiodo, et al., “A Case Study in Computer-Aided Co-design of Embedded Controllers”,
Design Automation for Embedded Systems, V1, N1-2, 1996.
5. D. Verkest, et al.: “CoWare - A design environment for heterogeneous hardware/software systems”, Design Automation for Embedded Systems, V1, N4, 1996.
6. L. Benini, et al.: “SystemC Cosimulation and Emulation of Multiprocessor CoC Designs”,
IEEE Computer, V36, No4, 2003.
7. T. Wiangtong, et al.: “Hardware/software codesign: a systematic approach targeting data-intensive applications”, IEEE Signal Processing Magazine, Volume 22, Issue 3, May 2005
Page(s):14 - 22.
8. F. Balarin, et al.: “Metropolis: an integrated electronic system design environment“, IEEE
Computer, Volume: 36, Issue: 4, page(s): 45- 52, April 2003.
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