Analysis and Synthesis of
Communication-Intensive Heterogeneous
Real-Time Systems
Paul Pop
Computer and Information Science Dept.
Linköpings universitet
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Outline
è Introduction
§ System-level design and modeling
§ Conditional process graph
§ The system platform
§ Time-driven vs. event-driven systems
§ Communication-intensive heterogeneous real-time systems
§ Time-driven systems
§ Scheduling and bus access optimization
§ Incremental mapping
§ Event-driven systems
§ Schedulability analysis and bus access optimization
§ Incremental mapping
§ Multi-Cluster Systems
§ Schedulability analysis and bus access optimization
§ Frame packing
§ Summary of contributions
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Embedded Systems
General purpose systems
Microprocessor
market shares
Embedded systems
99%
1%
Communication-intensive
heterogeneous
real-time systems
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Embedded Systems Characteristics
§ Dedicated functionality (not general purpose computers)
§ Embedded into a host system
§ Complex architectures
§ Embedded systems design constraints
§ Correct functionality
§ Performance, timing constraints: real-time systems
§ Development cost, unit cost, size, power, flexibility, time-toprototype, time-to-market, maintainability, correctness, safety, etc.
§ Difficult to design, analyze and implement
§ System-level design
§ Reuse and flexibility
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System-Level Design
System
specification
In this thesis
System-level
design tasks
§
§
§
Software
model
Hardware
model
Software
generation
Hardware
synthesis
Software
blocks
Hardware
blocks
Scheduling
Bus access optimization
Mapping
Prototype
Fabrication
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Application Modeling #1
P0
PP11
PP22
C
C
PP44
D
PP12
K 12
K
PP66
PP88
PP99
PP14
14
PP15
15
PP13
13
PP16
16
PP17
17
PP10
10
n First processor
n Second processor
n ASIC
D
PP33
C
PP55
PP77
PP11
11
P18
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Application Modeling #2
Subgraph corresponding to
D∧C∧K
P
P00
P
PP111
P
PP222
C
C
PP44
D
P
PP12
12
K 12
K
P
PP666
PP55
PP77
P
PP999
P
PP14
14
14
PP15
15
PP13
13
P
PP16
16
16
P
PP17
17
17
P
PP10
10
10
n First processor
n Second processor
n ASIC
D
P
PP333
C
P
PP888
P
PP11
11
11
P
P18
18
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Hardware Platform
...
Cluster:
one network
...
Gateway
I/O Interface
RAM
CPU
ROM
ASIC
Comm. controller
...
Time Triggered Protocol (TTP)
§
§
Controller Area Network (CAN)
Bus access scheme:
time-division multiple-access (TDMA)
Schedule table located in each TTP
controller: message descriptor list (MEDL)
S0 S1
Slot
S2
SG
S0 S1
S2
§
§
§
Priority bus, collision avoidance
Highest priority message
wins the contention
Priorities encoded in the frame identifier
SG
TDMA Round
Cycle of two rounds
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Distributed Safety-Critical Applications
...
§ Distributed applications
§ On a single cluster
§ On several clusters
§ Motivation
...
§ Reduce costs:
use resources efficiently
§ Requirements:
close to sensors/
actuators
§ Distributed applications are difficult to...
§ Analyze (e.g., guaranteeing timing constraints)
§ Design (e.g., efficient implementation)
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Event-Driven vs. Time-Driven Systems
§ Event-driven systems
§ Activation of processes is done at the occurrence of significant events
§ Scheduling event-triggered activities
§ Fixed-priority preemptive scheduling
§ Response time analysis:
calculate worst-case response times for each process
§ Schedulability test: response times smaller than the deadlines
§ Time-driven systems
§ Activation of processes is done at predefined points in time
§ Scheduling time-triggered activities
§ Static cyclic non-preemptive scheduling
§ Building a schedule table:
static cyclic scheduling (e.g., list scheduling)
10
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Outline
§ Introduction
§ System-level design and modeling
§ Conditional process graph
§ The system platform
§ Time-triggered vs. event-triggered
§ Communication-intensive heterogeneous real-time systems
è Time-driven systems
§ Scheduling and bus access optimization
§ Incremental mapping
§ Event-driven systems
§ Schedulability analysis and bus access optimization
§ Incremental mapping
§ Multi-Cluster Systems
§ Schedulability analysis and bus access optimization
§ Frame packing
§ Summary of contributions
11
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Scheduling and Bus Access Optimization
§ Input
§ Safety-critical application: set of conditional process graphs
§ The worst-case execution time of each process
§ The size of each messages
§ The system architecture and mapping are given
§§ Output
Time-driven systems
§§
§
§
Design
implementation
Single-cluster
architecture
such that the application is schedulable
Time-triggered protocol
and execution delay is minimized
Non-preemptive
static cyclic scheduling
§ Local schedule tables for each node
§ The sequence and size of the slots in a TDMA round
§ The MEDL (schedule table for messages) for each
TTP controller
Time-driven systems
Communication
infrastructure
parameters
12
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Scheduling and Optimization Example
P1
P4
P3
P2
24 ms
S1
Round 1
m3
m1
m2
Round 2
Round 3
S0
m4
Round 4
P1
P4
P3
P2
22 ms
S0
Round 5
S1
Round 1
m1
m2
Round 2
m3
Round 3
Round 4
P4
P2
S0
S1
Round 1
Time-driven systems
m1 m2
Round 2
m2
m4
P1
20 ms
m1
P
P11
P
P22
P
P33
m3
m4
P3
m3 m4
P
P44
Round 3
13
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Scheduling and Optimization Strategy
§ List scheduling based algorithm
§ The scheduling algorithm has to take into consideration the TTP
§ Priority function for the list scheduling
§ Bus access optimization heuristics
§ Greedy heuristic, two variants
§ Greedy 1 tries all possible slot lengths
§ Greedy 2 uses feedback from the scheduling algorithm
§ Simulated Annealing
§ Produces near-optimal solutions in a very large time
§ Cannot be used inside a design space exploration loop
§ Used as the baseline for comparisons
§ Straightforward solution
§ Finds a schedulable application
§ Does not consider the optimization of the design
Time-driven systems
14
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Can We Improve the Schedules?
Cost function: schedule length
Average Percentage Deviation [%]
60
50
§ Case study
40
Straightforward
§ Vehicle cruise
controllersolution
Greedy 1 the thesis
§ Used throughout
30
Greedy 2
20
Baseline:
Simulated Annealing
10
0
80
160
240
320
400
Number of processes
Time-driven systems
15
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“Classic” Mapping and Scheduling Example
N1
P1
P4
P2
P3
P1
N1
P4
P3
P2
N2
Bus
N2
S1
S0
Round 1
Time-driven systems
m1
m2
Round 2
Round 3
m3
Round 4
m4
Round 5
16
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Incremental Design Process
§ Start from an already existing system with applications
§ In practice, very uncommon to start from scratch
§ Implement new functionality on this system (increment)
§ As few as possible modifications of the existing applications,
to reduce design and testing time
§ Plan for the next increment:
It should be easy to add functionality in the future
Time-driven systems
17
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Future
applications
Do not exist yet
at Version N!
Current
applications
Map and schedule
so that the
future applications
will have a chance
to fit
Existing
applications
Minimal
modifications
are performed to
the existing
applications
N-1
N
Version N+1
Incremental Mapping and Scheduling
Time-driven systems
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Incremental Mapping and Scheduling
§ Input
§ A set of existing applications modeled using process graphs
§ A current application to be mapped modeled using process graphs
§ Each process graph in an application has its own period and deadline
§ Each process has a potential set of nodes to be mapped on and a WCET
§ Characteristics of the future applications
§ The system architecture is given
§ Output
§ A mapping and scheduling of the current application, such that:
§ Requirement (a)
constraints of the current application are satisfied
and minimal modifications are performed to the existing applications
§ Requirement (b)
new future applications can be mapped on the resulted system
Time-driven systems
19
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Mapping and Scheduling Example
Future
application
Current
application
Existing
application
(a)
The future application
does not fit!
(b)
Time-driven systems
20
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Mapping and Scheduling Strategies
§ Design optimization problem
§ Design criteria reflect the degree to which a design
supports an incremental design process
§ Design metrics quantify the degree to which the criteria are met
§ Heuristics to improve the design metrics
§ Ad-hoc approach
§ Little support for incremental design
§ Mapping Heuristic
§ Iteratively performs design transformations that improve the design
Time-driven systems
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Can We Support Incremental Design?
% of future applications mapped
Are the mapping strategies proposed facilitating
the implementation of future applications?
100
90
80
70
60
50
40
30
20
10
0
MH
AH
Future
application
Current
application
Existing
application
40
80
160
240
Number of processes in the current application
existing applications: 400, future application: 80
Time-driven systems
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Outline
§ Introduction
§ System-level design and modeling
§ Conditional process graph
§ The system platform
§ Time-triggered vs. event-triggered
§ Communication-intensive heterogeneous real-time systems
§ Time-driven systems
§ Scheduling and bus access optimization
§ Incremental mapping
è Event-driven systems
§ Schedulability analysis and bus access optimization
§ Incremental mapping
§ Multi-Cluster Systems
§ Schedulability analysis and bus access optimization
§ Frame packing
§ Summary of contributions
23
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Scheduling and Bus Access Optimization
§ Input
§ Safety-critical application: set of conditional process graphs
§ The worst-case execution time of each process
§ The size of each messages
§ The system architecture and mapping are given
§§ Output
Event-driven systems
Worst-case
response
times (schedulability analysis)
Single cluster
architecture
Design
implementation
Time-triggered
protocol
such that the application is schedulable
§ Fixed-priority preemptive scheduling
and execution delay is minimized
§§
§§
§ The sequence and size of the slots in a TDMA round
§ The MEDL (schedule table for messages) for each
TTP controller
Event-driven systems
Communication
infrastructure
parameters
24
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Conditional Process Graph Scheduling
P
P00
27 P
P11
C
C
30 P
P22
P
P99
30 P
P66
CPG
25 P
P33
24 P
P44
22 P
P77
19 P
P55
Not considering Considering
conditions
conditions
32 P
P11
11
25 P
P10
10
P
P12
12
Worst Case Delays
G1
120
100
G2
82
82
G2
P
P88
G1
Event-driven systems
Deadline: 110
25
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Scheduling of Messages using the TTP
messages are dynamically produced by the processes
frames are statically determined by the MEDL
m1
S0
m2
Round 1
S1
m3
m4
Round 2
m5
Round 3
1. Single message per frame, allocated statically:
Static Single Message Allocation
2. Several messages per frame, allocated statically:
Static Multiple Message Allocation
3. Several messages per frame, allocated dynamically:
Dynamic Message Allocation
4. Several messages per frame, split into packets, allocated dynamically
Dynamic Packets Allocation
Event-driven systems
26
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Compartison…
Average Percentage Deviation [%]
Cost function: degree of schedulability
16
Single Message
12
8
Dynamic Messages
4
Dynamic Packets
0
Multiple Messages
80
160
240
320
400
Number of processes
Event-driven systems
27
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Optimizing Bus Access (Static Allocation)
Process P2 misses its deadline!
P1
P2
P3
m1
m2
P1
P2
P3
Swapping m1 with m2:
all processes meet their deadlines.
m2
P1
P2
P3
m1
Putting m1 and m2 in the same slot:
all processes meet their deadline,
the communication delays are reduced.
m1 m2
Event-driven systems
28
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Outline
§ Introduction
§ System-level design and modeling
§ Conditional process graph
§ The system platform
§ Time-triggered vs. event-triggered
§ Communication-intensive heterogeneous real-time systems
§ Time-driven systems
§ Scheduling and bus access optimization
§ Incremental mapping
§ Event-driven systems
§ Schedulability analysis and bus access optimization
§ Incremental mapping
è Multi-Cluster Systems
§ Schedulability analysis and bus access optimization
§ Frame packing
§ Summary of contributions
29
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Schedulability Analysis and Optimization
§ Input
§
§
§
§
An application modeled as a set of process graphs
Each process has an worst case execution time, a period, and a deadline
Each message has a known size
The system architecture and the mapping of the application are given
Output
§§ Multi-cluster
systems
§§
§§
Worst case response
times and bounds on the buffer sizes
Two-cluster
architecture
Design implementation
Time-triggered
cluster
such that the application is schedulable and buffer sizes are
... minimized
§ Time-triggered protocol
§ Schedule table for TT processes
§ Non-preemptive static cyclic scheduling
§ Priorities for ET processes
§ Event-triggered cluster
§ Schedule table for TT messages
§ Controller area network protocol
Communication
§ Priorities for ET messages
infrastructure
§ Fixed-priority preemptive scheduling
§ TT bus configuration
parameters
(TDMA slot sequence and sizes)
Multi-cluster systems
System
...configuration
parameters
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Multi-Cluster Scheduling
§ Scheduling cannot be addressed separately for each type of cluster
§ The inter-cluster communication creates a circular dependency:
§ TTC static schedules (offsets) ⇒ ETC response times
§ ETC response times ⇒ TTC schedule table construction
TT Bus
Configuration
Static
Scheduling
Application,
Mapping,
Architecture
Response
Times
Offsets
Priorities
Response
Time
Analysis
Multi-Cluster Scheduling
Schedule
Tables
Multi-cluster systems
Offset
earliest possible
start time for an
event-triggered
activity
Response Bounds
on the
times
buffer sizes
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...
Optimization Example #1
...
N1
TTP
P4
P1
SG
S1
SG
m1m2
m3
S1
SG
NG
CAN
O2
N2
O3
Multi-cluster systems
P2
P3
Deadline
missed!
32
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...
Optimization Example #2
...
N1
TTP
P4 P4
P1
S
SG1
S
SG1
m1m2 m1m2
SS
G1
m3
SS
G1
SG
m3
SG
NG
CAN
O2
N2
O3
P2
P3
P3
P2
Deadline
missed!
met
Transformation: S1 is the first slot, m1 and m2 are sent sooner
Multi-cluster systems
33
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...
Optimization Example #3
...
N1
TTP
P4
P1
S
SG1
S
SG1
m1m2 m1m2
SS
G1
m3
SS
G1
SG
m3
SG
P4 P4
m3
SG
NG
CAN
O2
N2
O3
P2
P3
P2
P3
P2
P3
Deadline
missed!
met
Transformation:
Transformation:
S1 is Pthe
the slot,
high m
priority
process
on Nsooner
2 isfirst
1 and m
2 are sent
2
Multi-cluster systems
34
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Optimization Strategies
§ OptimizeSchedule
§ Synthesizes the communication and assigns priorities
to obtain a schedulable application
§ Based on a greedy approach
§ Cost function: degree of schedulability
§ OptimizeBuffers
§ Synthesizes the communication and assigns priorities
to reduce the total buffer size
§ Based on a hill-climbing heuristic
§ Cost function: total buffer size
§ Straightforward solution
§ Finds a schedulable application
§ Does not consider the optimization of the design
Multi-cluster systems
35
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Can We Improve Schedulability?
Average Percentage Deviation [%]
Cost function: degree of schedulability
Straightforward
solution
120
Does not perform optimizations
100
80
60
OptimizeSchedule?
40
OptimizeSchedule
20
0
80
160
240
320
Number of processes
Simulated Annealing
400 Near-optimal values for
the degree of schedulability
36
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Can We Reduce Buffer Sizes?
Cost function: total buffer size
Average total buffer size [k]
10k
OptimizeSchedule
8k
Does not optimize the
total buffer size
6k
OptimizeBuffers?
OptimizeBuffers
4k
Simulated Annealing
2k
0
80
Near-optimal values for
the total buffer size
160
240
320
400
Number of processes
Multi-cluster systems
37
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Outline
§ Introduction
§ System-level design and modeling
§ Conditional process graph
§ The system platform
§ Time-triggered vs. event-triggered
§ Communication-intensive heterogeneous real-time systems
§ Time-driven systems
§ Scheduling and bus access optimization
§ Incremental mapping
§ Event-driven systems
§ Schedulability analysis and bus access optimization
§ Incremental mapping
§ Multi-Cluster Systems
§ Schedulability analysis and bus access optimization
§ Frame packing
è Summary of contributions
38
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Thesis Contributions
§ Time-driven systems
§ Static scheduling strategy
§ Optimization strategies for the synthesis of the bus access scheme
§ Mapping and scheduling within an incremental design process
§ Event-driven systems
§ Schedulability analysis
§ Optimization strategies for the synthesis of the bus access scheme
§ Mapping and scheduling within an incremental design process
§ Multi-cluster systems
§ Schedulability analysis for multi-cluster systems
§ Optimization heuristics for system synthesis:
minimal buffer sizes needed to run a schedulable application
§ Frame-packing optimization heuristics
39
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