Design Optimization of
Multi-Cluster Embedded Systems
for Real-Time Applications
Paul Pop, Petru Eles, Zebo Peng, Viaceslav Izosimov
Embedded Systems Lab (ESLAB)
Linköping University, Sweden
Magnus Hellring, Olof Bridal
Dept. of Electronics and Software
Volvo Technology Corp., Göteborg, Sweden
1 of 1/20
14
Heterogeneous Networks
Distributed Heterogeneous System
...
NoCs
...
...
...
...
Factory Systems
Heterogeneous Networks
Multi-Cluster Systems
Automotive Electronics
2 of 2/20
14
Distributed Safety-Critical Applications
...
§ Applications distributed over
the heterogeneous networks
Gateway
...
§ Reduce costs:
use resources efficiently
§ Requirements:
close to sensors/actuators
§ Applications distributed over heterogeneous networks are difficult to...
§ Analyze (guaranteeing timing constraints)
§ Design (partitioning, mapping,
bus access optimization)
[DATE’03]
This paper!
3 of 3/20
14
Outline
§ Motivation
èSystem architecture and application model
§ Scheduling for multi-clusters [DATE’03]
§ Design optimization problems
§ Partitioning
§ Mapping
§ Bus access optimization
§ Optimization strategy
§ Experimental results
§ Contributions and Message
4 of 4/20
14
Hardware Architecture
...
Time-triggered cluster
...
Gateway
§ Static cyclic scheduling
§ Time-triggered protocol
Event-triggered cluster
§ Fixed priority preemptive scheduling
§ Controller area network protocol
Time Triggered Protocol (TTP)
§
§
Controller Area Network (CAN)
Bus access scheme:
time-division multiple-access (TDMA)
Schedule table located in each TTP
controller: message descriptor list (MEDL)
S0 S1
Slot
S2
SG
S0 S1
S2
§
§
§
Priority bus, collision avoidance
Highest priority message
wins the contention
Priorities encoded in the frame identifier
SG
TDMA Round
Cycle of two rounds
5 of 5/20
14
...
Software Architecture
...
Gateway
Time-triggered cluster
N2 CPU
CAN Controller
NG CPU
CAN Controller
N1 CPU
OutCAN
m3
T
T
m1
m1m2
P2
MBI
TTP Controller
TTP Controller
OutN2
P4
OutTTP
P1
m3
MBI
P
3
Event-triggered cluster
SG
S1
SG
S1
Round2
6 of 6/20
14
Multi-Cluster Scheduling [DATE’03]
Application,
Partitioning,
TT Bus
Mapping,
Configuration Architecture Priorities
Static
Scheduling
Response
Times
Offsets
Response
Time
Analysis
Multi-Cluster Scheduling
Schedule
Tables
Response
times
§ MultiClusterScheduling algorithm
§ Schedulability analysis: communication delays through the gateway
§ Scheduling: cannot be addressed separately for each cluster
7 of 7/20
14
Problem Formulation
§ Input
§ System architecture
§ Application
§ Partial partitioning and mapping,
based on the designer’s experience
§ Output
§ Design implementation
such that the application is schedulable
...
§ Partitioning for each un-partitioned process
Partitioning
and
...
§ Mapping for each un-mapped process
mapping
§ Priorities for ET messages
Communication
Application:
process graphs
Architecture:
Multi-cluster
infrastructure
§ TDMA set
slotofsequence
and sizes for the TT bus
§ Priorities for ET processes
Scheduling
information
§ Schedule table for TT messages
8 of 8/20
14
Motivational Example #1/1
In which cluster to place process P4?
Deadline
for P5
N1
P1
(faster) N2
(slower) N3
P1
P2
P3
P4
P5
P6
Deadline
for P6
P4
P2
N1
P1 70
P2 X
P3 X
P4 X
P5 X
P6 X
N2
X
X
50
70
X
40
N3
X
40
X
90
40
X
P3
P6
Missed
P5
CAN
TTC
N1
N2
Met
ETC
N3
TTP
9 of 9/20
14
Motivational Example #1/2
In which cluster to place process P4?
Deadline
for P5
N1
(slower) N3
P1
P2
P3
P4
P5
P6
Preemption
not allowed
P1
(faster) N2
P4
P2
N1
P1 70
P2 X
P3 X
P4 X
P5 X
P6 X
Deadline
for P6
P43
P6
Preempted Missed
P5
MetP5
N2
X
X
50
70
X
40
P4P3
N3
X
40
X
90
40
X
CAN
TTC
N1
N2
Met
ETC
N3
TTP
10 of10/20
14
Motivational Example #1/3
In which cluster to place process P4?
Deadline
for P5
N1
(slower) N3
Preemption
not allowed
P1
(faster) N2
P4
P2
Deadline
for P6
P4P3
P43
Met
Missed
Preempted
P4
P5
P6P6
Met
PMet
4 P5
Preempted
P1
P2
P3
P4
P5
P6
N1
P1 70
P2 X
P3 X
P4 X
P5 X
P6 X
N2
X
X
50
70
X
40
N3
X
40
X
90
40
X
CAN
TTC
N1
N2
ETC
N3
TTP
11 of11/20
14
Motivational Example #2/1
Where to map process P2?
Deadline
N3
N2
P1
S2 S3
SG
S2 S3 S1
SG
m2
TTP
P2
m1
N1
Missed
P3
S3 S1
SG
NG
CAN
N4
P1
m1
P2
m2
P3
P1
P2
P3
N1 N2 N3 N4
20 X X X
X 40 X 50
X X 20 X
CAN
TTC
N1
N2
N3
NG
ETC
N4
TTP
12 of12/20
14
Motivational Example #2/2
Where to map process P2?
Deadline
N3
N2
NG
P2
m2
P3
SG
S2 S3 S1
SG
T
m1
N4
m1
S2 S3 S1
T
CAN
P1
SG
m2
S2 S23
m2
P1
m2
TTP
P2
m1
N1
Met
Missed
P3 P3
P2
P1
P2
P3
N1 N2 N3 N4
20 X X X
X 40 X 50
X X 20 X
CAN
TTC
N1
N2
N3
NG
ETC
N4
TTP
13 of13/20
14
Motivational Example #3/1
What are the priorities on ETC?
Which slot should come first on the TTC?
Deadline
TTP
S1
SG
m1
NG
SG
m2
T
m1
T
SG
CAN
N2
T
P2
m1 P 1 m2
P2
P3
m3
m4
P4
S1 m3
Missed
P4
Round 4
S1 m4
S1
SG
T
m4
P1
m3
m2
N1
P3
CAN
P1
P2
P3
P4
N1
20
X
X
40
N2
X
40
20
X
TTC
N1
ETC
N2
TTP
14 of14/20
14
Motivational Example #3/2
What are the priorities on ETC?
Which slot should come first on the TTC?
Deadline
TTP
S1
Missed
Round 4
SG
m1
NG
SG
m2
T
m1
T
SG
CAN
N2
m1 P 1 m2
P2
P3
m3
m4
P4
Missed
P4
S1 m3 m4 S1 m4SG
TT
P2
P4
S1
SG
TT
m4
m4
P1
m23
m32
N1
P3P3
CAN
P1
P2
P3
P4
N1
20
X
X
40
N2
X
40
20
X
TTC
N1
ETC
N2
TTP
15 of15/20
14
Motivational Example #3/3
What are the priorities on ETC?
Which slot should come first on the TTC?
Deadline
Missed
P4
Round 4
P1
Round 1
T
T
m42
T
CAN
N2
P3
m1 P 1 m2
P2
P3
m3
m4
P4
SG1
m
S13 m3S1m4 SG1 m4SG
TTTT
m2
m1
m1
m4
NG
SG1
PP2 2
PMet
4
Missed
P4
S1
SG
TT
m4
m4
TTP SG1 m1SGm2 m
SG1
m3
m23
m32
N1
P3P3
CAN
P1
P2
P3
P4
N1
20
X
X
40
N2
X
40
20
X
TTC
N1
ETC
N2
TTP
16 of16/20
14
Optimization Strategy
§
Multi-Cluster Configuration
1. Initial Partitioninig and Mapping
§
§
Determines an initial partitioning and mapping
List scheduling-based greedy approach
§
Priority of ready processes: critical path
2. Partitioning and Mapping Heuristic
§
§
Iteratively improves on the initial partitioning and mapping
Intelligent design transformations that improve schedulability
§
Based on feedback from MultiClusterScheduling
3. Bus Access Optimization
§
§
§
Determines the slot sequence and lengths on the TTC,
message priorities on the ETC
Greedy optimization heuristic
Straightforward solution
§
§
Partitioning and mapping that balances the utilization of processors and buses
Could be produced by a designer without optimzation tools
17 of17/20
14
Experimental Results
Percentage schedulable applications [%]
Can we increase the number of schedulable applications?
100%
90%
80%
70%
Bus Access
Optimization
60%
50%
Partitioning and
Mapping Heuristic
40%
30%
Initial Partitioning
and Mapping
20%
10%
0%
50
100
150
200
Number of processes
250
Straightforward
solution
18 of18/20
14
Experimental Results, Cont.
Average execution time [hours:minutes]
How time-consuming is our optimization strategy?
5:20
5:00
4:40
4:20
4:00
3:40
3:20
3:00
2:40
2:20
2:00
1:40
1:20
1:00
0:40
0:20
0:00
Multi-Cluster
Configuration
Partitioning and
Mapping Heuristic
Initial Partitioning
and Mapping
Bus Access
Optimization
50
100
150
200
Number of processes
250
19 of19/20
14
Contributions and Message
§ Contributions
§ Addressed design problems characteristic to multi-clusters
§ Partitioning
§ Mapping
§ Bus Access Optimization
§ Proposed heuristics for design optimization
Analysis and optimization methods are
needed for the efficient implementation of
applications distributed over interconnected
heterogeneous networks.
20 of20/20
14