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Size-depth-alternation tradeoffs for circuits
Jeffrey Finkelstein
October 16, 2014
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• u = w0
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A Boolean circuit is a directed acyclic graph with some designated input
gates of fan-in zero and one designated output gate of fan-out zero in which all
non-input nodes are labeled with or, and, or not. All or and and gates have
fan-in two, and all not gates fan-in one. We assume that the gates of a Boolean
circuit are arranged in layers; each layer consists of gates whose inputs come
only from the previous layer and whose outputs feed only the following layer.
The depth, or layer number, of a gate is the length of the shortest path from any
input node to the gate; the depth of the circuit is the depth of the output gate.
The input gates are in the first layer and the output gate is in the last layer. We
assume that the first layer after the input layer consists of only not gates, and
no not gates appear anywhere else.
A configuration of a Boolean circuit is a triple (1n , i, w), where n is the
number of inputs, i is the layer number (in binary), and w is the contents of the
wires after layer i (given as a single binary string). If C is a circuit, configuration
(1n , i, u) yields configuration (1n , i + 1, v) if layer i + 1 of the circuit produces
output bits v when provided with input bits w. Configuration (1n , i, u) yields
configuration (1n , i + t, v) within t steps of there is a sequence of binary strings
w0 , . . . , wt such that
• (1n , i + k, wk ) yields (1n , i + k + 1, wk+1 ) for all k ∈ {0, . . . , t − 1}
• wt = v
W
or
A family of circuits {Cn }n∈N is L-uniform if there is a Turing machine M
such that M (1n ) halts within O(log n) space and outputs Cn .
Definition 1. A language L is decided by a Σk circuit family {Cn }n∈N if for
any input string x,
x ∈ L ⇐⇒ ∃w1 ∀w2 · · · Qk wk : Cn (x, w1 , . . . , wk ) = 1,
where Qk is ∃ if k is odd and ∀ if k is even.
Copyright 2014 Jeffrey Finkelstein ⟨jeffreyf@bu.edu⟩.
This document is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License, which is available at https://creativecommons.org/licenses/by-sa/4.0/.
The LATEX markup that generated this document can be downloaded from its website at
https://github.com/jfinkels/sizedepth. The markup is distributed under the same license.
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Definition 2. Σk SDG(s, d, g) is the class of languages that are decidable by
an L-uniform Σk circuit family of size s(n), depth d(n), and g(n) existential or
universal bits at each quantifier.
Lemma 3. Let n be a natural number and let An be a circuit on n inputs of size
s and depth d. The problem of deciding whether configuration Ci of circuit An
yields configuration Cj within t layers is in SD((n + s + log d) + t(d + s), t + log s).
Proof. The circuit that decides this problem simulates An for t layers, then
checks if any of those layers matches the target configuration Cj . Suppose
Ci = (1n , i, wi ) and Cj = (1m , j, wj ). The circuit we construct will check that
• n=m
• j <i+t
• If layer k of circuit An is denoted Lk , then at least one of the layers
Li , . . . , Li+t , when given wi as input, should output wj
Assuming m is in O(n), checking the equality of n and m requires a circuit of
size O(n) and depth O(log n). TODO finish me. . .
An increased number of alternations can simulate a circuit that would normally have greater depth. This is the circuit complexity analog of the corresponding result for Turing machines, described in [4, Lemma 2.7], therein attributed
to [2, Theorem 5.1]. (The Σk algorithm in those works is given as a recursive
alternating Turing machine algorithm; in this work, we have unwrapped the
recursion so that it more closely matches the definition of Σk SDG.)
Lemma 4. For all b, k, s, and d,
SD(s, d) ⊆ Σk SDG(s0 , d0 , g 0 )
where
• s0 = kb(n + s + log d) +
d
(d
bk−1
+ s)
d
+ log s))
• d0 = O(max(log bk(n + s + log d), bk−1
• g 0 = b(n + s + log d)
Proof. Let L be a language in SD(s, d), and let {An }n∈N be the L-uniform circuit
family that decides it. Suppose M is the O(log n) space Turing machine that
outputs An on input 1n . First we show a Σ2k circuit family that decides L, then
we modify it to provide a Σk circuit family.
Let n be an arbitrary natural number and let x be a binary string of length
n. Suppose C0 is the initial configuration of An with input x and Cd+1 is the
accepting configuration. Consider the Σ2k formula
∃C k ∀rk · · · ∃C 1 ∀r1 : Bn (x, C k , . . . , C 1 , rk , . . . , r1 ) = 1,
2
(1)
where each C i is a vector of b circuit configurations and each ri is a binary
integer in {1, . . . , b}. The Boolean circuit Bn computes the conjunction of the
following three formulas.
C0 = C1k ∧ Cbk = Cd+1
k
^
(2)
Crii = C1i−1 ∧ Cbi−1 = Crii +1
(3)
i=2
Cr11 yields Cr11 +1 within
d
layers
bk−1
(4)
The first formula ensures that the initial configuration and the accepting configuration of the circuit are correctly guessed as the first and last configurations.
The second formula ensures that the guessed sequence of configurations is a
valid sequence. The third formula ensures that one of the guessed sequences of
configurations correctly computes the original circuit An . Let us prove that this
is an L-uniform Σ2k SDG(s0 , d0 , g 0 ) circuit family that decides the language L.
First, we must prove L-uniformity. (TODO show L-uniformity. . . )
Next, let’s determine the size and depth of the circuit. Each configuration
requires O(n + s + log d) bits to describe; let S denote this value. Selecting
Crii from the sequence C i requires a multiplexer in which each input has O(S)
bits, there are b such inputs, and the selector rj has dlog be bits. This can be
implemented by O(S) single-bit multiplexers working in parallel. A multiplexer
for b input bits can be implemented by a circuit of size O(b) and depth O(log b) [3,
Lemma 2.5.5]. Thus the full multiplexer requires size O(bS) and depth O(log b).
Formula (2) contains two equality checks and requires two multiplexers.
Checking equality of two configurations requires a tree of and gates of size O(S)
and depth O(log S). It can therefore be implemented with a circuit of size O(bS)
and depth O(log b + log S), or more simply O(log bS).
Formula (3) contains O(k) equality checks, multiplexers, and increments of ri .
Computing ri + 1 from ri requires a circuit of size O(log b) and depth O(log log b).
Each equality check, multiplexer, and increment can be performed in parallel,
and the conjunction of these O(k) bits can be computed by a tree of and gates
of size O(k) and depth O(log k). Therefore, this formula can be implemented
with a circuit of size O(kbS) and depth O(log b + log S + log k), or more simply
O(log bkS).
By Lemma 3, formula (4) can be implemented by a circuit of size O(S +
d
d
(d + s)) and depth O( bk−1
+ log s). Combining the three formulas with a
bk−1
conjunction requires only O(1) more and gates so the overall size of the circuit
Bn is the sum of the sizes of the circuits computing the three formulas above,
and the depth of the circuit is the maximum of the three depths. Therefore, the
d
d
size of Bn is O(kbS + bk−1
(d + s)) and the depth is O(max(log bkS, bk−1
+ log s)).
Furthermore, each existential quantifier guesses O(bS) bits and each universal
quantifier guesses O(log b) bits, so the number of bits guessed at each quantifier
is bounded by O(bS).
(TODO show correctness. . . )
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Now we must eliminate half the alternations in formula (1). To do this, we
“negate” every other pair of quantifiers, along with the corresponding equality
checks in the circuit Bn . (TODO explain why this is possible. . . ) Two quantifiers
of the same type that appear next to one another can be collapsed to a single
quantifier of that type; the number of bits guessed at each quantifier remains
O(bS). So in the case that k is even, formula (1) becomes
∃C k ∀rk ∀C k−1 ∃rk−1 · · · ∃C 2 ∀r1 ∀C 2 ∃r1 : Bn0 (x, C k , . . . , C 1 , rk , . . . , r1 ) = 1, (5)
where Bn0 represents Bn with the following two modifications. First, whenever i is
even in formula (3), replace Cbi−1 = Crii +1 with its negation. Second, if k is even,
replace formula (4) with its negation. These modifications will not affect the
size or depth of the circuit, except by small constant factors. Thus formula (5)
represents a Σk SDG(s0 , d0 , g 0 ) circuit that correctly decides L, concluding the
proof.
Our goal is to choose b in order to minimize the depth d0 of the Σk circuit.
d
We wish to minimize d0 , so we consider log kbS and bk−1
+ log s as functions of
b, where S = s + n + log d as in the previous lemma. The former function is
monotonically increasing and the latter monotonically decreasing. The smallest
value of the maximum of the two functions is achieved when the two functions
d
have the same value. Solving the equation log kbS = bk−1
+ log s for b yields the
equation b = . . .. This choice of b yields complicated expressions for the values
of s0 , d0 , and g 0 , and is ultimately uninformative (to me). In order to find a
simpler expression for d0 , we relax the depth d0 from the maximum to the sum.
Corollary 5. For all k, s, and d,
SD(s, d) ⊆ Σk SDG(s0 , d0 , g 0 )
where
1
d+s
• s0 = kS(d(k − 1)) k−1 + k−1
1
• d0 = log kS(d(k − 1)) k−1 +
1
k−1
+ log s
1
• g 0 = S(d(k − 1)) k−1
Proof. Let S = n + s + log d as in the previous lemma. We know that
max(log kbS,
d
d
+ log s) ≤ log kbS + k−1 + log s
bk−1
b
as long as all the variables are positive, so any circuit with depth given by the
left side of the inequality can be simulated by a circuit with depth given by
the right side (by padding with the appropriate number of layers computing
d
the identity function). If we view log kbS + bk−1
+ log s as a function of b, the
1
−k
minimum is achieved when b + d(1 − k)b , the first derivative respect to b, is
1
zero. Since b is positive, this occurs exactly when b = (d(k − 1)) k−1 . This setting
of b yields the following values for s0 , d0 , and g 0 .
4
1
d+s
• s0 = kS(d(k − 1)) k−1 + k−1
1
• d0 = log kS(d(k − 1)) k−1 +
1
k−1
+ log s
1
• g 0 = S(d(k − 1)) k−1
Corollary 6.
P ⊆ Σ2 SDG(poly, log n, poly).
Proof. P is exactly the class of languages decidable by L-uniform polynomial
size circuits [1, Theorem 6.15]. In other words, P = SD(poly, poly). By the
previous corollary, SD(poly, poly) ⊆ Σk (poly, log, poly) for any k ≥ 2. Thus
P ⊆ Σ2 SDG(poly, log n, poly).
Unfortunately, this corollary is weaker than already known results:
P ⊆ NP ⊆ NNC1 (poly) ⊆ Σ1 SDG(poly, log n, poly) ⊆ Σ2 SDG(poly, log n, poly)
(The second inclusion comes from [5, Theorem 2.2].) The limiting factor in this
technique is the size of a configuration of the circuit. The number of gates in a
single layer may be O(s(n)), and s(n) is assumed to be a polynomial in n (in
the worst case). If there were some sub-polynomial upper bound on the width
of each layer of the circuit being simulated, then we could potentially improve
the unsatisfying Corollary 6.
References
[1] Sanjeev Arora and Boaz Barak. Computational Complexity: A Modern
Approach. 1st ed. Cambridge University Press, 2009. isbn: 0521424267.
[2] Lance Fortnow and Dieter van Melkebeek. “Time-Space Tradeoffs for Nondeterministic Computation”. In: Proceedings of the 15th Annual IEEE
Conference on Computational Complexity. COCO ’00. Washington, DC,
USA: IEEE Computer Society, 2000, pp. 2–13. isbn: 0-7695-0674-7. doi:
10.1109/CCC.2000.856730.
[3] John E. Savage. Models of Computation: Exploring the Power of Computing.
Addison-Wesley, 1998.
[4] Ryan Williams. “Inductive Time-Space Lower Bounds for SAT and Related
Problems”. In: computational complexity 15.4 (2006), pp. 433–470. issn:
1016-3328. doi: 10.1007/s00037-007-0221-1.
[5] Marty J. Wolf. “Nondeterministic circuits, space complexity and quasigroups”. In: Theoretical Computer Science 125 (1994), pp. 295–313.
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