%! ! ("# !& " +*
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The RW_IO block runs at 120 MHz and interfaces the master memory
controller chip’s 60-MHz core with the 120-MHz processor bus drivers. A
design approach using standard cells, automatic place and route tools,
and a powerful database management and build tool was used to
construct the RW_IO block. This approach was chosen over a full custom
or data-path solution because of its reduced risk and the flexibility of the
design tools.
) "$& )!
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D
Q
120 MHz
Pad
Q
DoutA
CKRW
120 MHz
60 MHz
Synchronous
I/O Driver
D
120 MHz
Q
60 MHz
*,10 (+$& +# 0%" (+ '
D
8.33 ns
1*" "3("007 '.! +1.*(
DoutB
CK1X
60 MHz
16.66 ns
4.16 ns
"(0&+*/%&, +# 0%" 76 (+ ' 0+ 0%" 76 (+ '
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$$, .$)(& .,(-! , 1$.# !-. *.#
( '/&.$*& 2$(" !), , -( .
RWI2BS
RWI3BS
RWIOBS
RWIOVBS
4.16 ns
CKRW
120 MHz
CK1X
60 MHz
Register 60-MHz
Core Data
Transfer Fast Path Data
to Processor Bus Driver
-. *.# .$'$("
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Fast Path
From
Core
Logic
D
D0
Q
60 MHz
Q
D1
HOLDAB
EN
Y0
120 MHz
Y1
D0
MUX
A
Q
D1
HOLDCD
EN
DMUXCTL
120 MHz
120 MHz
Y0
Y1
From
Core
Logic
60 MHz
D
D0
Q
Y0
MUX
Y1
A
EN
Y0
120 MHz
Y1
D0
Synchronous
I/O Driver
Pad
A
Q
D1
HOLDCD
MUX
RWMUXCTL_1
RWMUXCTL_0
120 MHz
120 MHz
120 MHz
MUX
A
Q
D1
HOLDAB
120 MHz
EN
DMUXCTL
120 MHz
/.*/. &)"$ )! .# &)% RWADIOBS !/(.$)(
/( 1& ..5%, )/,(&
Clock Signal
Bit Slices
Bit Slices
Bit Slices
Standard Cells
Bit Slices
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%7561/+<'& 75+0) 52'%+(+% '.. %1//#0&5
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† GDSII and CDL are industry-standard formats for data interchange.
Processor Bus I/O Drivers
Bit Slices
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Bit Slices
Bit Slices
+456 8'45+10 1( 6*' !"
$.1%-
70' '9.'66=#%-#4& 1740#.
Processor Bus I/O Drivers
TAP
Controller
RW_IO block redesigned
for area conservation and incluĆ
sion of little endian functionality.
Processor Bus I/O Drivers
TAP
Controller
RW_IO block with
relocated power rails.
Makefiles were generated to optimize the overall construcĆ
tion process and to allow for efficient rebuilding if necessary.
ClearMake's parallel distributed building capabilities greatly
improved the efficiency of the build process by parallelizing
the construction of the independent sections and distributing
the build processes across the networked machines. During
all build steps ClearMake performs auditing of the build proĆ
cesses. ClearMake keeps track of all the files read and writĆ
ten during the build and creates an audit trail called a conĆ
figuration record which is kept with the built object (derived
object). The configuration records are used by future builds
to determine if the object is out of date and needs to be
rebuilt. ClearMake examines the versions of all the elements
referenced in the configuration record to determine if a reĆ
build is necessary. It does not rely on the dateĆtimeĆmodiĆ
fied" of the object. The configuration records can be examĆ
ined by the developer and used as a source of history
information regarding any derived object.
During the course of the master memory controller chip deĆ
sign the RW_IO block went through many changes. The
initial specification required that the block be long and narĆ
row and cover the entire side of the chip that interfaces with
the processor bus (see Fig. 6).
Later in the project, area became critical, and it was necesĆ
sary to reduce the size of the block. An additional requireĆ
ment on the master memory controller chip was that it had to
support little endian byte order (leastĆsignificant byte is byte
0). The structure of the RW_IO block was ideally suited to
implement the little endian functionality which required byte
swapping the data returned from memory before delivering
it to the processor bus (see Fig. 7).
The original specifications called for the main power and
ground buses to pass through the center of the RW_IO
block. Toward the end of the chip development the power
buses changed and the VDD bus had to be moved. This
again required reconstructing the RW_IO block (see Fig. 8).
The use of standard cells and automatic place and route
tools for the construction of the RW_IO block proved to be
very advantageous. Because of the speed and flexibility of
the tools the design team was not hindered when making
changes to the highĆspeed interface block as they might
have been if a full custom approach had been pursued. The
most complex change to the block, which required rebuildĆ
ing all of the bit slices and resizing and reconstructing the
block, took only three days to complete, at which time the
block was fully verified.
The design approach of using standard cells and semicustom
layout techniques was favored over a dataĆpath or full custom
implementation because of its reduced risk. However, GDT
schematics were generated for documentation purposes as
well as a fallback position if a dataĆpath solution had been
required. The combination of standard cells, custom Cell3
layout, and accurate static timing analysis proved to be an
effective solution for the RW_IO highĆspeed interface block.
1. S. Clayton, et al, The Automation of Standard Cell Block Design
for HighĆPerformance Structured Custom Integrated Circuits," Mentor Graphics is a trademark of Mentor Graphics Corporation in the U.S.A. and other
countries.
June 1995 HewlettĆPackard Journal