International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 3 - May 2014
Implementation of Switching System for High Speed
Data Transmission using VHDL
Yogendra Singh Yadav, Shailendra Kumar, Prof. (Dr.) S.H.Saeed
M.Tech Student, Jr.Associate Professor, Professor and Head of Department ECE, Integral University Lucknow ,
Integral University , Dasauli , Kursi Road , Lucknow-226026,India
Abstract—Switching system is used for data transmission
between two communicating Channels. This transmission can be
done via trunks or it can be fully wireless, technically termed as
Telephone Switching and Mobile switching, respectively. The
implementation of the switching system using VHSIC hardware
description language is more reliable and efficient than the
previous switching system [1]. It converts entire bulky switching
unit which consists of routers, multiplexers, decoders, counters in
to a single integrated circuit . Simulation results are presented
for transfer of data from input subscriber to the output
subscriber using sequential write / random read mode with the
timing diagram[2]. To verify the transfer of data from input
subscriber to the output subscriber a 32 bit op-code is assumed
in which each bit represents a specific function. In our Paper we
have worked on Switching System for two different channels
using VHDL, each channel have 16 users. They can communicate
either intra channel or inter channel. We are also providing
Caller ID facility. The incoming data through the inlets are
written into the data memory and later read out to the
appropriate outlets. The incoming and outgoing data are usually
in serial form whereas the data are written into and read out of
the memory in parallel form. That’s why it is necessary to
perform serial to parallel conversion and parallel to serial
conversion at the inlets and outlets respectively. We have selected
32 bit op-code for communication among these channels because
its ability to define all the functions. This 32 bit op-code is
responsible for caller id and transmission and reception of
particular data. I have implemented my work with the help of
Xilinx ISE and Modelsim 10.2a.
Keywords—VHDL, control memory, op-code, switching system,
signaling.
I. INTRODUCTION
Telegraphy was introduced in 1837 in Great Britain and in
1845 in France. In March 1876, Alexander Graham Bell
invented telephone set and the possibility of telephony, i.e.
long distance voice transmission [3]. Graham Bell
demonstrated a point-to-point telephone connection. The
network using point to point connection is shown in fig 1.In
general case with n entities, there are {N(N-1)/2} links,
therefore the number of links required with moderate or
higher values of n to have fully connected system becomes
very large. Consequently, practical use of bell’s invention on
every scale demanded not only the telephone sets and the
wires pairs, but also the switching system. As per switching
system, the subscribers are not connected directly to one
another; instead they are connected to the switching system.
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Y1
Y6
Y2
Y5
Y3
Y4
Fig.1 The Network with Point to Point Links
II. BASICS OF SWITCHING SYSTEM
The major component of the switching system is the input and
output circuits called inlets and outlets. Primary function of
this system is to establish path between inlet and outlet. If
there are N inlets and M outlets, when N=M network is called
symmetrical network. Inlets and outlets can be connected to
local subscriber or trunk from / to other exchanges .When all
inlets and outlets are connected to subscriber lines the logical
connection appears. In this case the output lines are folded
back to input and hence called the folded network.
Four types of connections are:
1. Local call connection between two subscribers
`in
system.
2. Outgoing call connection between an incoming trunk and
local subscriber.
3. Incoming call connection between an incoming trunk and
local subscriber.
4. Transit calls connection between an incoming trunk and an
outgoing trunk.
A. Point-to-Point Channel
Point to Point channel was designed to implement the
communication link between the transmitter and receiver
models. The basic design consists of a transmitter model, a
receiver model, noise model, compare model and a model
showing the data transfer medium called digital channel and
can be modelled wired [4]. In this paper, we have focused on
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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 3 - May 2014
wireless networks. Fig.2 shown the Basic Block diagram of a
wireless communication system consisting of two nodes.
Fig.2 Block diagram of a wireless communication system consisting of two
nodes
B. Point-to-Multipoint Channel
The multi-port and/or port array feature of VHDL with second
parameter of sc_port, the array size parameter can be set. Here
the idea is to provide a number of like-defined ports. Here we
assumed that our system has a no. of interfaces with the same
connectivity and a no. of N devices connected to it. By using
dynamic changeable feature of the modules and dynamic
channel binding for multiport interface of the transmitter we
can generate as much as we desire from this system.
II BASIC COMPONENT OF SWITCHING SYSTEM
A. Principle of Switching System
The data coming from inlets are stored into the data memory
and later read out from appropriate outlets. The incoming and
outgoing data are usually in series whereas the data are written
into and read out from memory in parallel form. It therefore is
necessary to perform serial to parallel conversion and vice
versa at the inlets and outlets respectively.
For convenience, the in and out data of the MDR are
shown separately for data memory. Since there is only one
MDR a gating mechanism is necessary to connect the required
inlet/outlet to MDR and has done by in gate and out gate units.
Information is not transferred in real time but first stored in
the memory and later transferred to outlet. A time delay
occurs between the acquisition of a sample from inlet and its
delivery to the corresponding outlet. This switching system
can be controlled by given three ways:
III WORKING SPECIFICATIONS OF SWITCHING
SYSTEM
A.








Features
Dual way 32 user support
Sequential Input Random Read
Caller Id Facility
Inter and Intra exchange
16 Bit data transfer
In band Signalling
Synchronization clock
Reset features
Fig.4 32-bit OPCODE
The opcode assumed is of 32 bit and each bit is having
some specific function. Starting from right hand side, the bit 0
to 15 represents data, bit 16-21 are zero, bit 22-25 represent
source subscriber, bit 26-29 represent destination subscriber,
bit 30 represent whether the call is interexchange or
intraexchange and bit 31 represent whether the subscriber is
enabled or disabled.
B. Inter Exchange
1. Sequential write/Random read.
2. Random write/Sequential read.
3. Random input/Random output.
In first two methods, the sequential / random read /
write operations refer to the read / write operations associated
with the data memory. In these cases, the inlets and outlets are
scanned sequentially but in last case the inlets and outlets
were scanned randomly and data memory was accessed
sequentially.Fig.3 is shown the Basic structure of dual way
switching system.
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Fig. 3 Dual Way Structure of Switching System
For inter exchange value of we will be 1 in that case 16 users
in each exchange can communicate with each other. Exchange
1 have 16 user and Exchange 2 have 16 user if we are working
on Inter exchange then 16 user of exchange 1 can
communicate with 16 users of exchange 2 and also 16 user of
exchange 2 can communicate with 16 users of exchange 1.
C.
Intra Exchange
For intra exchange value of we will be 0 in that case 16 users
in one exchange can communicate with each other. Exchange
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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 3 - May 2014
1 have 16 user and Exchange 2 have 16 user if we are working
on Intra exchange then 16 user of exchange 1 can
communicate with 16 users of exchange 1 only they cannot
communicate with exchange 2 users and also 16 user of
exchange 2 can communicate with 16 users of exchange 2
only they cannot communicate with exchange 1 users.
D.
Data Memory
We have 17 bit of std_logic type data memory for 16 locations
i.e. we can have 16 bit of data which we can transfer for intra
exchange exchange1 to exchange1 all users and exchange 2 to
exchange 2 all users. In case of Inter Exchange we can
transfer 16 bit of data exchange 1 to exchange 2 all 16 users
and exchange 2 to exchange 1 all 16 users.
E.
Control Memory
We have 16 locations of integer type for control memory. It
decide all the function of whole system i.e. which exchange of
caller want to communicate which exchange user. It will
decide by caller id of all users and they have what data all
information is passing through control memory.
F.
Caller ID
We have 32 location 16 locations for source and 16 locations
for destination. For intra exchange source and destination
exchange will be same, in this caller Id will decide that which
location will receive the data and also inform to destination
that which location transmits this data.
IV WORKING OF SWITCHING SYSTEM
Phase 1: Input Subscribers in both the exchanges are scanned
sequentially. It takes 16 clock cycles to scan 32 subscribers in
order to know their status, that is they want to transmit or not.
This is called a sequential scanning. The date to be transmitted
is stored in data memory in sequential order. The information
relating to the called subscriber is stored in control memory in
sequential order and caller id number is stored in the caller id
memory in the sale way. Thus I can say system is sequential
write.
Phase 2: When all the scanning is finished the location of the
data memory is read according to the corresponding location
of the control memory. For example, if first location of data
memory has data ‘d’ and corresponding location in control
memory is 2, this means that ‘d’ will be communicated to the
2nd user of the exchange, thus I can say the system is random
read. To decide where the data will be communicated I use a
bit in my opcode as ‘I’ bit. If ‘I’ =1, then it is interexchange,
i.e. the read out data will be given to user of other exchange.
Thus communication between the subscriber of two
exchanges can be made possible and hence the name
interexchange. If ‘I’ = 0, then it is called as interexchange, i.e.
the read out data, will be given to the user of the same
exchange. Thus communication between subscribers of the
same exchange is made possible, and hence the name
Intraexchange.The exchange between caller id memories is
done only if the particular user is enabled. Same is the case
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with data memory. A particular user is enabled if its opcode
16th bit is 1 and disabled if it is 0.So caller must be enabled
and called must be disabled in order to make a call successful.
The communication means just to transfer the data ( 0- 15 bits
of opcode) between entities and is shown by overwriting the
data bits if called subscriber. Caller id facility enables the
called user to see who is calling by checking his relevant bits
of opcode (25 to 22) fig 3.2 shows the structure of switching
system.
V
RESULTS
A. Simulation Result
There are two exchange centres’ which taken as ‘din’ and
‘dout’. Our work has been implemented for inter exchange
and Intra exchange both. If we take ‘I’ is one then our design
will work for inter exchange. If we take ‘I’ is zero then our
design will work for Intra exchange. Our design is depend on
some more inputs clock, reset and enable. If reset is high then
our design will not perform any function, all functions
performed on low reset and positive edge of clock. If enable is
zero then there is no exchange of data. Our exchanges are
work on high enable bit.
In this case we shows the inter exchange for first
exchange. Here we take enable bit 1, I as 1, source address is
0101, and destination address is 0110 data for transmission is
“AD01”. We receive that data on second exchange dout on 6th
address. In this case we shows the intra exchange for first
exchange. Here we take enable bit 1, I as 0, source address is
0110, and destination address is 0101 data for transmission is
“AD01”. We receive that data on first exchange din on 5th
address shown in fig 5.
Fig. 5 Simulation result for First Exchange (Inter Communication)
In this case we have shown the intra exchange for second
exchange. Here we take enable bit 1, I as 0, source address is
1100, and destination address is 0010 data for transmission is
“1234”. We receive that data on same exchange dout on 2nd
address shown in fig.6
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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 3 - May 2014
VI CONCLUSION
Fig.6 Simulation result for Second Exchange (Inter Communication)
B.
Synthesis Results
Previous paper used only 16 users (each exchange
has 8 users) and 16 bit opcode. But in our work, I have
worked on 32 users (each exchange has 16 users) and 32 bit
opcode which is comparatively more efficient, have higher
user capacity and have effective low power requirements. It
will also be more reliable because of 32 bit opcode generate
comparatively larger encrypted bits. In contrast we have tried
to make this whole system digital to increase the efficiency,
lower the power requirement and reduce the delay. VHDL has
been used to write all the programs for the ICs because of its
user-friendly nature and thus modifications if required for
further development shall not prove to be an obstacle. As we
know, the process of making ICs is time consuming and an
expensive venture so we must be sure about the working
results of the ICs in advance as we can’t accept errors later.
Fig.7 shown the Main RTL of our code, 8 shown the Internal
RTL of our code and 9 shown the devices utilized in our work.
ACKNOWLEDGEMENT
First of all I am grateful to God, The most beneficent
and merciful who provides me confidence and
determination in accomplishing this work. I wish to
express my deep sense of gratitude and profound
thanks to Mr. Shailendra Kumar (Jr. Associate
Professor), Integral University, Lucknow for
providing me the opportunity to work on this topic
under his guidance. The encouragement and support
he provided throughout, despite his busy schedule,
was invaluable and truly acknowledgeable. His
feedback, constructive criticism and encouragement
were the driving force behind the successful
completion of this dissertation. I would also like to
offer my thanks to Head of The Department Prof (Dr.)
S.H. Saeed, Department of ECE, Integral University
for their throughout guidance and support whenever
required. I would also grateful to the author and
scholars whose work I have referred as a guiding
stone in my dissertation. Finally I would like to
express my sincere Gratitude to my friends, seniors,
parents, family and well wishers for extending help to
carry out the dissertation work.
Fig.7 Main RTL
REFERENCES
[1]
Fig.8 Internal RTL
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Prashant Rai,” VHDL Implementation of a prototype switching
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Thiagarajan Viswanathan.,” “Telecommunication Switching
Systems and Networks”.
Ibrahim Aref,” System Level Modeling of a Digital
Communication Channel Based on SystemC”, International
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Xilinx inc, “Xilinx foundation series user reference guide”.
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William I Fletcher, “An Engineering Approach to Digital
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Theodore s. rappaport, “Wireless communications”, second
addition, Prentice Hall of India.
Fig.9 Device Utilization of our code
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