International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 2 - May 2014
Common Mode Voltage Reduction in DCMLI
M.S.Raghavendra Reddy, G.Sri Harsha, B.Nishanth, E.Sai Prateek Reddy
1234
Dept. of EEE, KLUniversity, Vaddeswaram, Guntur, A.P, India
Abstract: This paper presents modulation strategies to
reduce common mode voltage in diode clamped multilevel
inverter. During operation of diode clamped inverter it
produces common voltage which is not zero, this causes
significant impact on the motor. The carrier pulse width
modulation strategies are implemented for five level diode
clamped multilevel inverter and the variation of common
mode voltage is observed and presented using SIMULINK.
Keywords: common mode voltage, diode clamped, carriers
pwm
I.
INTRODUCTION
The concept of multilevel converters has been
introduced since 1975 [1]. The term multilevel began
with the three-level converter [2]. Subsequently, several
multilevel converter topologies have been developed.
However, the elementary concept of a multilevel
converter to achieve higher power is to use a series of
power semiconductor switches with several lower
voltage dc sources to perform the power conversion by
synthesizing a staircase voltage waveform. Capacitors,
batteries, and renewable energy voltage sources can be
used as the multiple dc voltage sources. The
commutation of the power switches aggregate these
multiple dc sources in order to achieve high voltage at
the output; however, the rated voltage of the power
semiconductor switches depends only upon the rating of
the dc voltage sources to which they are connected. A
multilevel converter has several advantages over a
conventional two-level converter that uses high
switching frequency pulse width modulation.
II.
Fig1. Illustration of CMV
Because of 12 switches in the Neutral Point Clamped or
Diode clamped inverter shown in Fig. 1, They produce
19 output voltage vectors including a zero voltage
vector. If sum of the output voltages is not zero, a
common-mode voltage results. An example of
waveforms of phase voltages and the resulting commonmode voltages are shown in Fig.2
COMMON MODE VOLTAGE
CMV is defined as the voltage at the star point of the
load and the system ground. The magnitude of the CMV
depends on grounding system.[1]
Vcom = 1/3(Va + Vb + Vc)
(1)
Fig. 2 Phase output voltage & common mode voltage of
Neutral Point clamped or Diode clamped inverter
The Neutral Point (NP) voltage variations cause the
added variations of three-phase output voltage and
induce some harmonics in thee output.
Va = V sin(wt) + Vnp
Vb = V sin(wt-1200) + Vnp
Vc = V sin(wt-1200) + Vnp
ISSN: 2231-5381
http://www.ijettjournal.org
Page 54
International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 2 - May 2014
Vcom = 1/3(V’a + V’b + V’c)
Finally, the NP voltage variations generate commonmode voltage at three times the fundamental output
frequency, which occurs even if the high frequency and
high dv/dt switching common-mode voltage is mitigated
by some techniques such as filtering. When the
common-mode voltage and resulting shaft voltage
caused by the NP voltage variation are large enough to
break the oil film insulation in the bearings, bearing
currents are generated, which by erosion may cause
premature failures of the motor bearings. Hence the NP
voltage control is important not only for the Neutral
Point Clamped or Diode Clamped inverter operation but
also for common-mode voltage mitigation [2]. The shaft
voltage is measured between the motor shaft and the
motor frame, which is usually grounded. It is generated
by the common-mode voltage coupling through the path
that consists of the motor stator windings, rotor
windings and the distributed capacitance between them.
Its magnitude is dependent on not only the magnitudes
of the common-mode voltage but also the coupling
impedance[6].
III.
MULTI-CARRIERPULSE WITH
MODULATION
Fig.3 Comparision of reference wave and phase
disposition carrier waves for five level
Phase Opposition Disposition Pwm
All the carriers above the zero reference are in phase
and carriers below the zero reference are also in phase
but are phase shifted by 180° with respect to that above
zero reference. The significant harmonics are located
around the carrier frequency, for both the phase and
line-to-line voltage waveform.
This section of the chapter extends the principles of
carrier-based PWM that are used for multilevel inverter.
There are three alternative PWM strategies with
differing phase relationships:
3.1 Phase Disposition (PD)
3.2 Phase Opposition Disposition (POD)
3.3 Alternative Phase Opposition Disposition (APOD)
3.1 PHASE DISPOSITION PWM (PDPWM)
The carriers are in phase across all the bands .The zero
reference is placed in the middle of the carrier sets. For
this technique, significant harmonic energy is
concentrated at the carrier frequency, but since it is a
cophasal component, it doesn't appear in the line-to-line
voltage.
Fig.4 Comparison of reference wave and phase
opposition disposition carrier waves for five level
ALTERNATE PHASE OPPOSITION DISPOSITION
Carriers in adjacent bands are phase displaced by 180°.
With this method, the most significant
harmonics are centered as side bands around the carrier.
ISSN: 2231-5381
http://www.ijettjournal.org
Page 55
International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 2 - May 2014
Fig.5 Comparison of reference wave and alternate phase
opposition disposition carrier waves for five level
IV.
Fig.8 Three phase line voltages of five level DCMLI
SIMULATION RESULTS
Fig.9 Common mode voltage for phase opposition
disposition scheme
Fig.6 Three phase line voltages of five level DCMLI
Fig.8 Three phase line voltages of five level DCMLI
Fig.7 Common mode voltage for phase disposition
scheme
ISSN: 2231-5381
http://www.ijettjournal.org
Page 56
International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 2 - May 2014
width modulation strategies like phase disposition,
phase opposition disposition, alternate phase opposition
disposition are implemented for these fivel level diode
clamped mli. The common voltage is reduced by these
techniques and supported by Simulink results
REFERENCES
Fig.11 Common mode voltage for alternate phase
opposition disposition scheme
PWM Technique
Phase disposition
Phase
opposition
disposition
Alternate phase opposition
disposition
V.
Common Mode Voltage
42
37
[2]
[3]
[4]
31
CONCLUSION
In this paper five level diode clamped multilevel
inverter is simulated by SIMULINK. The different pulse
ISSN: 2231-5381
[1]
[5]
R. H. Baker and L. H. Bannister, “Electric Power
Converter,” U.S. Patent 3 867 643, Feb. 1975.
A. Nabae, I. Takahashi, and H. Akagi, “A New Neutralpoint Clamped PWM inverter,” IEEE Trans. Ind. Applicat.,
vol. IA-17, pp. 518-523, Sept./Oct. 1981.
R. H. Baker, “Bridge Converter Circuit,” U.S. Patent 4 270
163, May 1981.
Akash A. Chandekar, R.K.Dhatrak Dr.Z.J..Khan
“MODELLING AND SIMULATION OF DIODE CLAMP
MULTILEVEL INVERTER FED THREE PHASE
INDUCTION MOTOR FOR CMV ANALYSIS USING
FILTER, Vol.2,Issue 8,2013.
F.X. Edwin Deepak, R.Ranjitha “A Comparison Of Multi
Carrier Pwm Techniques Using Z-Source Five Level Diode
Point Clamped Inverter, Vol.9 Issue 1.2014,pp14-19
http://www.ijettjournal.org
Page 57