International Journal of Engineering Trends and Technology (IJETT) – Volume 12 Number 3 - Jun 2014
Design of a 3.0 MSPS, 2.5V, 0.25 µm, 4-Bit Flash
ADC Based on TIQ Comparator
Rajesh Kumar Nagar#1, UBS Chandrawat*2,
1#
PG Scholar, Department of Electronics and Communication Engineering, SVCE, Indore, India
*2
Prof. Departments of Electronics and Communication Engineering, SVCE, Indore, India
generate corresponding digital output. In this comparator
Abstract— This paper deals with the high speed and low power threshold voltage is used as an internal reference voltage
design of 4-bit flash Analog to Digital Convertor (ADC) using which consequently eliminates the need of resistor ladder
Threshold Inverter Quantization (TIQ) based comparator circuit from flash ADC. Flash ADC requires 2N-1 different size
design. It introduces Threshold Inverter Quantization (TIQ)
comparators for the generation of thermometer code. Here
comparator and multiplexer (MUX) based design. ADC is a
TIQ comparators are designed which uses two cascading
major building block governing the power and speed
specification in flash ADC. Here TIQ comparator is used in the inverters as a voltage comparator. The voltage comparators
design to reduce the size of the circuit. MUX based design is used compare the input voltage with internal reference voltages,
to generate the output in lesser number of clock cycles, thereby which are determined by the transistor sizes of the inverters
increasing the speed. The proposed design is simulated on tanner [3]. Hence, we do not need the resistor ladder circuit used in a
tool with 0.25 µm technology to evaluate the performance of this conventional flash ADC. The second stage inverter is the gain
architecture. This designed architecture of 4-bit flash ADC is booster, which makes a sharper threshold for comparator
found to consume 1.9mW power and the sampling rate of this outputs and provides full digital output voltage swing. In a
ADC is found to 3.0 MS/S. The comparator block is found to conventional flash ADC, reference voltage is generated using
consume 355 µW power from 2.5 V supply.
a resistor ladder circuit. Due to resistor ladder circuit the size
of comparator is large and also consumes more power.
Keywords—TIQ Comparator, Thermometer encoder, Flash
ADC, High Speed, Low-power.
I. INTRODUCTION
ADC designs these days needs architecture having high speed
operation and less power consumption. Various architectures
of ADC have been proposed by researchers now days with
different resolutions, sampling rates, power consumptions and
temperature ranges. These ADCs are used in different
applications from mobile communication devices to measure
equipment [1]. Since the performance parameters like
sampling rate, resolution, and power consumption of an ADC
is basically determined by its architecture, one single ADC
type cannot cover all applications. Therefore, it is important to
choose a proper ADC for each particular application. One of
the commonly used ADC is flash type ADC because of the
better tradeoff between its performance metrics. For instance,
flash type ADC architecture is mainly used for high speed and
low resolution applications [2]. A block diagram of 4-bit flash
ADC is shown in figure. A flash ADC comprises of two basic
building blocks: comparators and encoder. Comparator block
is used for comparing the input signal with the reference
signal and generated thermometer code value and encoder is
used for converting thermometer codes in to digital output.
Flash ADC is not efficient for the resolution of more than 8bit. As long as resolution level is kept large, the comparator
count will be reasonable. Therefore the comparator is more
critical part of flash ADC. In this paper author proposes small
size and low power consumed TIQ comparator. TIQ
comparator uses two cascading CMOS inverter for comparing
input analog signal with internal reference voltage and
ISSN: 2231-5381
Fig. 1 Block diagram of 4-bit flash ADC
II. FLASH ADC ARCHITECTURE
The above Fig.1 shows architecture of a flash ADC. For a "4"
bit converter, the circuit employs 24-1= 15 comparators. The
reference voltage for each comparator is one least significant
bit (LSB) greater than the reference voltage for the
comparator immediately below it. Each comparator produces
a "1" when its analog input voltage is higher than the
reference voltage applied to it. Otherwise, the comparator
output is "0". This Flash ADC comprises of following two
blocks:
A.
TIQ
COMPARATORThreshold
inverter
quantization (TIQ) is a good way to realize a comparator for a
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International Journal of Engineering Trends and Technology (IJETT) – Volume 12 Number 3 - Jun 2014
high speed CMOS flash ADC. The TIQ CMOS inverter
design is based on systematic transistor sizing. It eliminates
the resistor array implementation of flash ADC design. The
TIQ comparator consist of one PMOS (M0) and one NMOS
(M1) transistors connected in series, with the inverter
switching threshold voltage depending upon the transistor
sizes. By varying its transistor sizes, the threshold voltage
(reference voltage) Vth can be changed. The approximately
Vth is given by following equation 1 [4]. The sizes of NMOS
and PMOS transistors in a comparator are same and are
different for different comparators. The length of NMOS and
PMOS transistors are fixed where as width of NMOS and
PMOS varies [5].
V
− V
+V
β
β
V =
β
1 + β
=
.
=
.
…..(1)
…..(2)
…..(3)
MOS logic styles. This multiplexer has characteristics of high
speed with minimum power compared with other realizations
like dynamic and pass-transistor logic styles [6]. Logic
expression for multiplexer output is given below.
F = A′ X1 + AX2
…..(4)
Where, X1 and X2 are the inputs, A is the select lines and F is
the output.
III. DESIGN AND IMPLEMENTATION
This section deals with implementation of three components
as discussed in section II.
A.
TIQ COMPARATOR- TIQ comparator designing
using two back to back connected inverters. The TIQ consists
of two cascaded CMOS inverters as shown in Fig. The analog
input signal quantization level is set in the first stage by
changing the voltage transfer curve (VTC) by means of
transistor sizing. Since the transistor channel length, L, is
more effective than the channel width, W, in controlling the
performance (fTα1/L2), L is kept constant and only W is
changed during the design process. Figure.3. shows the
schematic view of the TIQ comparator. Threshold inverter
quantization (TIQ) is a good way to realize a comparator for a
high speed CMOS flash ADC. The TIQ CMOS inverter
design is based on systematic transistor sizing. It eliminates
the resistor array implementation of flash ADC design [4].
B.
ENCODER - Thermometer - to - Binary encoders has
become bottleneck in the ultra-high speed flash ADCs. The
combination of having medium power consumption, low
transistor count, more regular structure and shorter critical
path makes the multiplexer-based encoder is suitable for
efficient flash ADC design. Figure 4.7 show the symbol of 2:1
multiplexer.
Fig. 2 Block diagram of 4-bit flash ADC
A 2-to-1 multiplexer is the leaf cell in the encoder. We have
analyzed a 2-to-1 multiplexer circuit using complementary
ISSN: 2231-5381
Fig. 3 Schematic view of the TIQ comparator
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International Journal of Engineering Trends and Technology (IJETT) – Volume 12 Number 3 - Jun 2014
Figure.4. shows the schematic of comparator block which
contained combination of 15 comparators and in figure 5.4
shown symbol of this comparator block.
Fig. 5 Schematic view of the Encoder Block
TABLE I
Truth table for 4bit encoder
Fig. 4 Schematic view of the Comparator Block
B.
ENCODER- The encoder is used to convert
thermometer code into binary code. There are many
techniques to design an encoder. The combination of having
medium power consumption, low transistor count, more
regular structure and shorter critical path makes the
multiplexer-based encoder which is suitable for efficient, high
speed and low power flash ADC design. This multiplexer has
implemented by pass-transistor logic. Multiplexer is an
important device for the design of flash ADC. Thermometer to - Binary encoders has become bottleneck in the ultra-high
speed flash ADCs. The combination of having medium power
consumption, low transistor count, more regular structure and
shorter critical path makes the multiplexer-based encoder is
suitable for efficient flash ADC design.
ISSN: 2231-5381
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International Journal of Engineering Trends and Technology (IJETT) – Volume 12 Number 3 - Jun 2014
TABLE III
Table for Parameter Values
Fig. 6 Schematic view of the 4-bit flash ADC
IV. SIMUATION RESULTS
This Section clearly discuss about the simulation results of
above said two important blocks of flash ADC, the work is
carried out on Tanner Tool 13.0 and the simulation is
completed on 250 nm technology file. The schematic of TIQ
comparator and encoder are simulated. The integrated flash
ADC is operated at 4-bit precision with analog input voltage
range of 0.46V to 1.64V at supply voltage of 2.5V. This
designed architecture of 4-bit flash ADC is found to consume
1.9mW power and the sampling rate of this ADC is found to
3.0 MS/S.
Sr. No.
Parameter
1
Architecture
Results by Proposed
design
flash
2
Technology
0.25 µm
3
Resolution
4-bits
4
Supply Voltage
2.5V
5
Sampling rate
3.0 MSPS
6
Power consumption
1.9mW
V. COCLUSION
A fast and small size flash ADC architecture that uses two
cascaded CMOS inverter as a comparator, called threshold
inverter quantization technique has been proposed. The
MUX based encoder has been used here to increase the
speed of the design. The schematic of TIQ comparator and
encoder are simulated. The integrated flash ADC is
operated at 4-bit precision with analog input voltage range
of 0.46V to 1.64V at supply voltage of 2.5V. This
designed architecture of 4-bit flash ADC is found to
consume 1.9mW power and the sampling rate of this ADC
is found to 3.0 MS/S. In this architecture less no of
transistors are used and which makes die area of the design
small. The ADC is design and implemented in standard
0.25µm CMOS technology using Tanner tool.
REFRENCES
[1]. Syed Mohammed Askari Naqvi “Overview of Digital Calibration of
ADCs for Wireless Applications” Department of Electronics, Computer
and Software Systems (ECS) School of ICT KTH-Royal Institute of
Technology, Stockholm. March 2006.
[2]. G. Zhang, “A Low-Power Pipeline ADC with Front-End Capacitor
Sharing”, Master of Applied Science thesis University of Toronto, Ch-3,
pp-17-26.
[3]. M.J. Demler, “High speed Analog-to-Digital Conversion”, Academic
Press, Inc.-1991, Ch-1, pp-1-19.
[4]. Ali Tangel and Kyusun Choi “The CMOS Inverter” as a Comparator in
ADC Designs”. Analog Integrated Circuits and Signal Processing, 2004
Kluwer Academic Publishers.
[5]. Prof. S.S. Khot, Dr. P. W. Wani, Dr. M S Sutaone, Shubhang Tripathi
“Design of a 45nm TIQ Comparator for High Speed and Low Power 4Bit Flash ADC”. ACEEE Int. J. on Electrical and Power Engineering,
Vol. 02, No. 01, Feb 2011.
[6]. Arunkumar. P. Chavan, Rekha. G, P. Narashimaraja “Design of a 1.5-V,
4-bit Flash ADC using 90nm Technology”. International Journal of
Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958,
Vol. 2, Issue-2, December 2012.
Fig.7 Output waveform of 4bit ADC
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