International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue7- July 2013
Design of Dual Cryptography Encoder
SHAMBHULINGAIAH C. M1, RAVI SIMHA B. N2, Dr. M Z KURIAN3
1
2
PG Student, Sri Siddhartha Institute of Technology, Tumkur, Karnataka, India
Asst. professor, Dept of ECE Sri Siddhartha Institute of Technology, Tumkur, Karnataka, India
3
HOD, Dept of ECE, Sri Siddhartha Institute of Technology, Tumkur, Karnataka, India
The traditional methods of Cryptography engine involve
usage
of single Cryptography algorithm. This has lead to
Abstract - Data hiding has been used for thousands of years to
chances
of data being leak to the intruder, which has created
transmit data without being intercepted by unwanted viewers,
therefore security becomes increasingly important for many lot of mishaps. In order to avoid this, to increase the data
applications, such as video surveillance, confidential transmission, security, the Cryptographic level or Encryption level has been
military and medical etc. In November 2001 NIST published increased to an extent where such mishaps are not possible. In
Rijndael as the proposed Algorithm for AES (Advanced Dual cryptosystem, the asymmetric key is used to encrypt the
Encryption Standard), it enhancing the higher level of security secret key and the secret key is used to encrypt the actual
by utilizing the strongest 128 bit. AES encryption algorithm is message.
used to encode and authenticate the data. In the year of 2001,
National Security Agency (NSA) was designed and announced
SHA stands for Secure Hash Algorithm. SHA 256 is a member of
SHA-2, which is a set of cryptographic hash functions (SHA-224,
SHA-384, and SHA-512). SHA 256 is a novel hash functions
computed with 32-words. But, in the year of 2005, some security
flaws were identified in SHA-1, so that indicating a stronger hash
function would be desirable. Although SHA-256 bears some
similarity to the SHA-1 algorithm, these attacks have not been
extended to SHA-256. This hash function can be used to encrypt
the key, which is better than SHA-1 in terms of performance and
security. The goal of design SHA 256 core is to make an
implementation more cost efficient.
Keywords: - Cryptography, SHA 256, AES 128.
I. INTRODUCTION
The term Cryptography is usually referred as "the study of
secret", nowadays it is most attached to the definition of
encryption. The term encryption is a process of converting
plain text "unhidden" to a cryptic text "hidden" to secure it for
against data thieves. The term decryption is reverse process of
encryption, where cryptic text needs to be decrypted on the
other end to be understood. In cryptographic systems, the term
key refers to a numerical value used by an algorithm to alter
the information so, making that information more secure and
visible only to those who have the corresponding key to
recover that information. The cryptography can be divided in
to mainly two types. 1. Public key cryptography 2. Secret key
cryptography. The Secret key cryptography is also called as
symmetric key cryptography. Here both the sender and the
receiver must know the same secret code, called as key.
Messages can be encrypted by the sender using the key and
decrypted by the receiver using the same key code. The Public
key cryptography also referred as asymmetric key
cryptography, which uses a two keys or pair of keys for
encryption and decryption process. With the public key
cryptography, keys work in pairs of matched private and
public keys.
ISSN: 2231-5381
II. SYSTEM ARCHITECTURE
A. AES-128 Structure
The AES algorithm is a symmetric-key cipher, in which a
single key is used by both the sender and the receiver for
encoding and decoding process. The data block size is fixed to
be 128 bits, while the key length can be 128, 192, or 256 bits,
respectively. In addition, the AES is an iterative cryptographic
algorithm. One iteration can be called as a round, and the total
number of rounds is 10, 12, or 14, when the key length is 128,
192, or 256 bits, respectively. The 128-bit data is divided into
16 bytes. These bytes are mapped in to a 4*4 array form
called the State, and all the internal operations of the AES
algorithm are performed on the State. Each round in AES,
except the last round, consists of four transformations:
SubBytes, ShiftRows, MixColumns, and AddRoundKey. The
last round does not have the MixColumns operation. The
figure 1 shows the AES 128 core structure.
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Figure 1. AES-128 Core
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International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue7- July 2013
B. SHA-256 Structure
The block diagram of SHA-256 core is shown in figure 2
[10]. The secure hash algorithm is a one-way hash function
that can process a message to produce a condensed
representation called a message digest. This algorithm can be
used to determination of message integrity: This property is
useful in the generation and verification of digital signatures
and message authentication codes. The function of SHA-256
can be divided in to four modules. Message pad, Data blocks
expansion, Round Calculation and Output process modules.
Actually SHA-256 algorithm can be portioned in to two stages:
Pre-processing stage and Hash computation stage. Preprocessing involves padding a message in to m-bit blocks
means each message has 512 bits and containing a message
length information. Before the hash computation starts these
messages shall be padded. This function is performed by
message padding. The SHA-256 takes 64 rounds to calculate
the result; this is done by Dates count. The message expands
and round operations are the two major critical modules that
influence cores area and speed.
through PCI port. In Encoding process, plain text is converted
in to cipher text, which is an output of AES Encryption. To
encode the data, the key used is also encoded by SHA-256
cryptographic algorithm. For SHA-256, a 32-bit key is given
as an input. This SHA-256 algorithm gives the encoded key.
This key is used to encode the data in AES-128 algorithm.
Finally, the output of AES 128 algorithm produces the
encoded data of 128-bit.
IV. RESULT
The Dual Cryptography Encoder was implemented using
Verilog hardware description language. These descriptions
were then processed by standard Xilinx ISE 13.4 design tool
suite, which performed synthesis, placement, and routing and
bit stream (FPGA physical programming information)
generation. The bit stream generated was dumped on to
XC4VFX12 device of Xilinx Vertex 4 family for physical
testing.
Figure 4. Simulation Result
Figure 2. SHA-256 core Block Diagram
III. HARDWARE IMPLEMENTATION
Figure 4 shows the simulation result of Dual
Cryptography Encoder. Here the data is of 128-bit and key is
of 32-bit both of these are applied to the AES 128 algorithm,
which gives 128-bit encoded data. This 128-bit of encoded
data waveform has shown in above figure.
Figure 3. Dual Cryptography Encoder
Figure 3 shows the block diagram of Dual Cryptography
Encoder. The whole system is built up on a FPGA board and
the core of the system is cryptographic cores implementing
different cryptographic algorithm such as AES 128 and SHA
256. The cryptographic Engine is connected to computer
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Figure 5. FPGA output
Figure 5 shows the FPGA output of implemented
design. For FPGA implementation, 8-bit of data is considered
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International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue7- July 2013
instead of 128-bit and key size is of 32-bit. In figure 5, data_in
is input to the encoder; text_i is key and enc_data is the
encoded data.
V. CONCLUSION
In this paper, we implement a FPGA encoder engine with
SHA-256 and AES-128 IP cores. This Dual cryptography
encoder uses SHA-256 algorithm to encrypt key and AES-128
algorithm is used to encrypt the data. This implementation
shows that hardware implementation has better performance
in terms of speed and power than software implementation.
Also the use of SHA-256 Cryptographic algorithm for
enhancing the Security has been proposed.
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