International Journal of Engineering Trends and Technology- Volume4Issue2- 2013
Multicore: Move to the Future
Nikhil Srivastava1, Vineet Pandey2, Ruchi Pathak3, Abhishek Pandey4
1
Department of ECE
PIT Jaunpur, India
2
Computer Science Deptt.
RBMI Bareilly, India
3
Computer Science Deptt.
SRMS Bareilly, India
4
Department of ECE
JIIT, Noida
Abstract— : In the last decade in processor the multicore
technology has become prominently a basic reference.
Multicore processors combine a steadily rising number of
independent compute units, called cores, on one chip allowing
them to do multiple calculations simultaneously. One constant
in computing is that the world’s hunger for faster performance
is never satisfied and therefore the technology takes a further
and further move. This paper describes about some challenges
and future prospects of multicore technology.
Keywords-Multicore, Microarchitecture, Starvation, Smart
Cache, Memory Accessing
I.
INTRODUCTION
In recent years, multi-core processors and multiprocessor networks have grown in popularity due to its
features high clock speed, power consumption, process
technology and have changed the definition of HPC (high
performance computing). Single core processors have a
limitation regarding the trend of achieving higher
performance by increasing a processor's clock rate and
fabrication process scaling. This leads to higher power
consumption due to the physical limitations of integrated
circuits. Multicore processors provide a solution to these
limitations. In multicore algorithm power consumption and
heat dissipation become a concern and is simulated before
layout for best floorplan which distributes heat across the
chip.
Two smaller processor cores, instead of a large
monolithic processor core, can potentially provide 70-80%
more performance, as compared to only 40% from a large
single core. Intel have launched processor upto 8 cores.
Recently Intel’s i7 with 6 cores and Xeon with 8 core have
given a revolution to further multicore. Projections suggest
that future processors may carry many more cores–10’s or
even 100’s of cores within a single chip. This trend is
accelerated by the unprecedented technology advances and
the limited single core scalability.
II.
MULTICORING
Multicore processors have several benefits. Each
processor core can be individually turned on or off, thereby
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saving power. The power consumption so reduced very
much. Each processor core can be run at its own optimized
supply voltage and frequency. This makes it easier to load
balance among processor cores to distribute heat across the
die. It can potentially produce lower die temperatures
improving reliability and leakage.
In Multi-core processor multiple core are able to run at a
lower frequency, dividing among them the power normally
given to a single core. The result is a big performance
increase over a single core processor. The following Intel
illustration—based on Intel’s lab experiments with
commonly used workloads—illustrates this key advantage.
Figure 1. Relative single-core frequency and Vcc
III.
IS MULTICORING ENOUGH?
Two smaller processor cores, instead of a large
monolithic processor core, can potentially provide 70-80%
more performance, as compared to only 40% from a large
single core. Multicore processors have a several benefits as
each processor core may posses its own optimized supply
voltage and frequency, power consumption is reduced as
each processor core can be individually turned on or off,
easier to manage heat sink across the die and reliability and
leakage current is improved. If the technology gets to scaled
further transistor performance may not get suitable and
required increment due to subthreshold and leakage current
resulting in unreasonable power consumption, here it’s
needed to go beyond the present multicore system and go
towards a several cores chip upto 10000 cores as
presictions.
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International Journal of Engineering Trends and Technology- Volume4Issue2- 2013
IV.
CORE ARCHITECTURE
Building on the foundation of Intel Core
microarchitecture, Intel is establishing a new cadence that
will speed up the delivery of products featuring superior
performance and energy-efficiency for years to come. Many
key features are entitled in multicore architecture especially
in Intel Microarchitecture. It greatly enhances energy
efficiency with many leading edge microarchitectural
advancements.
A. Execution
Combining different techniques such as data flow
analysis, speculative execution, out of order execution, and
super scalar , the Intel’s microarchitecture has enabled the
wide dynamic execution. i.e. enabling delivery of more
instructions per clock cycle to improve execution time and
energy efficiency. Intel Wide Dynamic Execution also
includes a new and innovative capability called
Macrofusion. Macrofusion combines certain common x86
instructions into a single instruction that is executed as a
single entity. This increases the peak throughput of the
engine to five instructions per clock.
B. Memory Accessing
In it architecture facilitates to ensure that data can be
used as quickly as possible. The data is required is be
located as close as possible to where it’s needed to minimize
latency. This improves efficiency and speed. It includes a
new capability called memory disambiguation, which
increases the efficiency of out-of-order processing by
providing the execution cores with the built-in intelligence.
C. Cache
The architecture facilitates for multi-core optimized
cache that improves performance and efficiency by
increasing the probability that each execution core of a dualcore processor can access data from a higher-performance,
more efficient cache subsystem. It also enables obtaining
data from cache at higher throughput rates for better
performance.
D. Power Handling
This feature manages the runtime power consumption of
all the processor’s execution cores. It includes an advanced
power-gating capability that allows for an ultra fine-grained
logic control that turns on individual processor logic
subsystems. A set of capabilities for reducing power
consumption and device design requirements are introduced.
V.
ISSUES
A. Design
 Requirement of visibility for Test & Debug is the
major issue because of design complexity.
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
Power delivery, overall power and thermal density
previsualization is a need for the design because if
this goes beyond the limitation whole design is
ruined.
B. Architectural
 Shared resource management provides some
limitations. Different complex observation and
approaches are needed which is a never ending
improvement process.
 Bandwidth means maximum data travelling in a
particular time. On and Off-chip bandwidth
requirements also provides some limitations.
 Different latency time reduction is also a big
hurdle. These latencies may be in execution, cache,
and memory.
 Memory coherence or consistency and multiple
domains in clocking, voltage, reset also needed to
be considered.
 Partitioning resources, and fault tolerance at
device, storage, execution, core level may be other
issues
C. Memory System, System Bus, and Interconnections
A multicore design has a larger memory requirement.
With cores now using 64-bit addresses the amount of
addressable memory is almost infinite. Extra memory will
be useless if the amount of time required for memory
requests doesn’t improve as well. This gives an
improvement in system bus and interconnections. lower
latency in intercore communication and memory
transactions is needed for a faster network.
D. Data Starvation
If a single threaded application run on multicore
processor then if an algorithm isn’t developed correctly for
multicore then another idle core may stave for data. This
requires a rejoining of all the basic partitioning. This is an
extreme case but may create the problems.
E. Homogeneous and Hetrogeneous
Homogeneous cores are easier to produce since the same
instruction set is used across all cores and each core
contains the same hardware. But they may be inefficient
sometimes. Although there’s not a specific answer about the
preference between them but heterogeneous core are proven
tremendously very efficient in some applications. Each core
in a heterogeneous environment could have a specific
function and run its own specialized instruction set. A
compromise between them may be solution and better
approach in near future.
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VI.
FUTURE MULTICORE PREDICTIONS
The ever widening processor-memory speed gap as well
as the severely limited chip bandwidth exacerbates the
dependence of program performance on the on-chip
memory hierarchy design and management in a future
multicore processor.
They will have many general-purpose processor cores
supplemented by special-purpose cores, onchip peripherals.
They must be multithreaded at the core level, because
hardware multithreading is relatively cheap and doesn’t
require application programmers to write explicitly
multithreaded code.
Many processor architects predict that future multicore
chips will integrate numerous specialized engines for dataplane processing. These engines will supplement, not
replace, the general purpose cores dedicated to control-plane
processing.
A new technology CMOS integrated nanophotonics may
make the multicore more dynamic and efficient,reducing
losses. It’ll use photons instead of electrons for
communication purpose in the chip as in waveguides IBM
heralded silicon nanophotonics as the enabler for future
exascale processors that can execute a million trillion
operations per second (1,000-times faster than today's
petascale supercomputers).
VII. CONCLUSION
Think of a time a decade or so from now when the full
power of high performance computing and parallel
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processing is available to computer users everywhere, and it
might be possible to hold the power of a computer with
hundreds of execution cores in the palm. Multi-core
processors are the future of computing.
ACKNOWLEDGMENT
The authors thank the assistance provided by Sapan
Kumar Gupta of JIIT Noida, Aditya Pathak of YLM Tube
Solutions&Service India Pvt. Ltd. Additional thanks go to
Ragini Rai, Sangam Gupta, Vishwajeet Sahu, Saurabh
Bajpai and Pushkar Mishra for their great effort and inspiring
me for this paper.
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