International Journal of Engineering Trends and Technology- Volume4Issue3- 2013
Delay Optimization for 32 Division PFD
Elamurugan.C#1, Samson Immanuel.J*2,
ECE Department, Karunya University, Coimbatore
PG Scholar, Assistant Professor
Abstract— The frequency divider is an essential block in the high
speed integrated circuit. Frequency Divider is the important
block in the communication system. A Dual modulus prescaler
divides the frequency of the Voltage controlled oscillator and
prescaler circuit of 32 or 33. Main signals of Modulus control is
the signal for the Programmable divider. Dual modulus prescaler
is prescaler is of two counters of the architecture in Counter
operation of the power consumption is working parallel. the dual
modulus prescaler is reduced in the modulus control signal
generator. The frequency input is given to dual modulus
prescaler for getting the output signal.
Keywords— Power Factor, Delay Factor, MDR.
I. INTRODUCTION
The frequency is according to the application works in the
changes the division ratio of the division 5 to division 4 And
second rising edge changes the division ratio clock moving of
the states in the dividing factor the dual modulus prescaler [2]
of the precharged and discharged with clock transitions of the
toggling of the glitches in the internal stage of the node in the
power consumption. The design of high moduli the critical
path delay and the speed of the D-flip-flop in the
asynchronous counter at the cost of the additional loading to
the synchronous counter which results in the degraded
performance. The intrinsic division ratio of the divider is[5]
still an integer, the quantization noise is introduced and
contributes the wide locking range and the low voltage
operation are performed by adding the injection nmos
between the supply of the divider running frequency of the
incident power and the current mode interface between the
down conversion mixer output and donate the common mode
Feedback of the mixer switches low voltage techniques are
employed to enhance the mixer second order and third order
linearity to the dynamic matching technique of the common
mode feedback of the standard process options of the radio
frequency frontend of the mixer linearity of the critical path
delay in the degraded performance[5,6,7] of the synchronous
counterHigh moduli of the states of the current mode in the
incident power of the frequency of the minimization of the
delay of the Critical path of the design in the architecture of
the power in the clock moving of the path in the delay of the
asynchronous counter of the phase noise.the frequency divider
is low power consumption of the design in the performance of
the architecture of the loading transistors are different in the
pseudo pmos of the flip-flop of the phase noise and prescaler
of the clock moving of the integer division mode of the speed
of the pmos and the prelayout simulation of the minimation
delay of the frequency in the use of the dual oxide of the rmcs
generator of the counter in the path of the delay in the
matching technique of the programmable integer.
II. EFFICIENT PROGRAMMABLE DIVIDER
ARCHITECTURE
The Dual Modulus prescaler contains the input signal Fin
of N or N+1 by the modulus control signal and produces and
changed into N=16.The upcounter is increases on the rising
edge. The Modulus control signal is low and the multiplexer is
‘s’ and[4] upcounter counts the rising edge of from S value
and S Modulus control values, multiplexer selected the P
value.upcounter counted the rising edge upto P value,if the P
values are equal, it operates Reset signal of zero.upcounter
counting from zero.
Fig.1. Efficient PD Block Diagram
The proposed Programmable divider contains dual modulus
prescaler and the modulus control is low. The up counter
improved and the rising edge and reset is high. the s and up
counter counted the rising edge [4] .the value and s values of
the dual modulus prescaler changed the division-17 to
division-16.upcounter counted the rising edge of the P value.
D = N * P + S
DFF3, Two logic gates are obtained in the scaler of N=4.The
upcounter is increases on the rising edge. The Modulus
control signal is low and the multiplexer is ‘s’ and upcounter
counts the rising edge of D multiplexer selected the P
value.upcounter counted the rising edge upto P value The 4/5
signal catches the division ratio by the signal.4/5 Control is
low. the ratio is 16 is connected by the reduced module
control signal generator of the input in the upcounter.the dual
modulus prescaler is connected to the up counter and value is
goes to the reduced module Control signal generator. The mux
values are equal to the MC.The signal in the programmable
divider of the upcounter is giving the input values to the
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International Journal of Engineering Trends and Technology- Volume4Issue3- 2013
circuit in the flip flop s value.
Fig.2. N=16 Efficient PD Block Diagram
of the control in the reset signal in the dividing factor of the
counter in the generator of the reset of the multiplexer value
of the signal of the dividing factor of the signal in the input
of the counter of the divider The 4/5 signal catches the
division ratio by the signal.4/5 Control is low. The ratio is 16.
The generator is having the Equality detector of s and p
signal. The architecture of the low power in the multistandard Reset and reduced module control signal
generator.the design of the reduced module control signal
generator of the different gates Of xor with or gate in the dflip-flop of the modulus control of the generator in the
equality detector of the inputs given to the Detector of the
control signal in the upcounter of the dual modulus prescaler
of the three D flip-flops of the modulus control in the nand
gates of the prescaler in the programmable Divider detector
of N=4 in the input frequency of the flip-flops.
III. N VALUES OF DUAL MODULUS
PRESCALER
Fig.3. N=32 Efficient PD Block Diagram
The generator is having the Equality detector of s and p
signal. the architecture[3] of the low power in the multistandard Reset and reduced module control signal generator
The circuit of 2 counters of the clock moving of the states in
the dividing factor[8] . The generator is having the Equality
detector of s and p signal. Main signals of Modulus control
and reset signal for the Programmable divider. The
programmable counter contains the reduced module control
signal generator of the generator of the circuit in the dividing
factor. The reset IC connected to the upcounter and the
multiplexer value is connected to the efficient programmable
Divider of the dividing factor of the upcounter in the reduced
Module signal generator of the counters in the reset signal.
that value is connected by the reduced module signal
generator of the modulus control of the upcounter in the
circuit of the two counters of the multiplexer of the reset
module of the dividing factor of the counter of reset signal
in the dual modulus prescaler of the counters of the generator
of ths programmable counter of the clock of the dual modulus
Prescaler of the input signal of the multiplexer in the modulus
control of the frequency input of the reduced modulus control
Signal generator of the three bit in the upcounter of the
multiplexer of the modulus control of the input in the
frequency of the value of the multiplexer of the input values
The dual modulus prescaler of N=16 contains the many flip
flops with different feedback logic section of the
asynchronous divider in the different gates of the synchronous
core of the modulus control.the dual modulus prescaler of the
modulus control signal in the modulus prescaler in the core of
the control signal in the flip-flops of the nand gates in the
control of the architectture of the gate in the control signal of
the detector in the flip-flops’.. The synchronous divider of the
modulus control of the nand gates in the architecture of the
modulus control.the frequency input is connected to the dual
modulus prescaler 32/33 of the reduced module signal
generator. The output is connected to the upcounter for
counting the values. The Values in the upcounter is connected
to the reduced module control signal generator .the
multiplexer is connected to The reduced module control
signal generator the three bits are Used and the modulus
control is connected from the dual modulus control of the
upcounter in the reset signal[1]. the reset signal is connected
to the upcounter for counting the values in the generator.the
generator of the module control in the programmable divider
in the multiplexer of the given frequency input of the divider
in the modulus control of the signal of the equality detector of
the signal in the gates of the dividing factor of the reset signal
in the counter of the clock of the upcounter of the dividing
factor of the power in the delay of the factor of the
programmable divider in the frequency synthesizers of the
counter with the maximum dividing factor Of the counters in
the generator in the upcounter in the efficient programmable
divider and new modified programmable divider.the power is
decreased in the signal of the factor of the control in the
control signal of the nand gates Of the maximum division
ratio.the maximum division ratio is increased by the each
divider circuits.the delay is decreased in the divider to the
upcounter of the frequency of the power in each divider circuit
of the divider in the factor of the counters in the generator of
the divider in the frequency input of the factor of the different
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International Journal of Engineering Trends and Technology- Volume4Issue3- 2013
values of the control of the gates in the feedback section of the
comparison of the delay and power in the each circuits in the
divider of the maximum division ratio in the factor of the
counter in the dividing ratio of the divider in the values of the
feedback section of synchronous core.
IV. RESULTS AND DISCUSSIONS
The input is giving to the dual modulus prescaler N=4 and the
Output is going to the upcounter and giving Reduced module
control signal generator .the multiplexer is connected to the
reduced module control signal generator.by giving the input
values to the fin and the output
Fig.6. N=32 Waveform of programmable frequency divider
TABLE I. COMPARISON OF DIVIDER CIRCUITS.
Divider
Circuit
Power
Maxim
um
Division
Ratio(
MDR)
Delay
PD(N=4)
366mW
26
2.695ns
PD(N=16)
354mW
98
1.048ns
PD(N=32)
366mW
194
0.959ns
Fig.4. N=4 waveform of programmable frequency divider
The input is giving to the dual modulus prescaler N=16 and
the output is taken as the reduced module control signal
generator contains the mux signal in the input values.the
output of the frequency is divided by the given input signal.
Fig.5. N=16 waveform of programmable frequency divider
The input from dual modulus prescaler of the input signal of
N=32 and is taken from the reduced control signal Generator
by the mux values.the signal value is changing according to
the given input values to the frequency input of the dual
modulus prescaler.the dual modulus prescaler contains the
divider in the multiplexer values of the output in the signal of
the frequency of the signal in the generator of modulus
prescaler in the signal of the frequency in the generator of the
signal of the inputs in the frequency of the generator of the
frequency in the multiplexer of the divider.
Table I shows the comparison of the divider circuits with
different power and different maximum division ratios with
the different delays .the delay is decreasing for the divider
circuits. The delays are varying in the different divider circuit
Of the power in these maximum ratios the delay in the delay
of the divider circuits [9] in the comparison of the circuits.the
power is varied in the different divider circuits and Delay also
varying in the different divider circuits. The power is varied
according to the divider circuits of the delay in the Different
delay of the power in the maximum divider ratio of different
delay in the power of the comparison of the delay of the
circuits in the power and maximum division ratio of the
Comparison of the divider circuits.
V.CONCLUSION
The circuit of PD N=4, N=16, N=32 is varied according to the
consumption. The value is Division 16.upcounter counted the
rising edge of the programmable divider.Two circuit of two
counters of the clock moving of the states in the dividing
factor.the programmable divider contains the multistandard
frequency circuit synthesizer of the counter of the divider in
the generator of the divider.any factor will be decreased in the
each divider circuits of the programmable divider for finding
the ratio.
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International Journal of Engineering Trends and Technology- Volume4Issue3- 2013
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