International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 1- March 2016
Analysis and Design of Positive Feedback
Adiabatic Logic (PFAL) Based Universal
Gates
Sowmiya.M1, Darwin.S2, Sindhuja.D3, Sheela Merlin.M4
1,3,4
PG Student, 2 Asst.Prof, Electronics Department,
Dr.Sivanthi Aditanar College of Engineering, Tiruchendur, Tamilnadu, India.
Abstract
This paper presents positive feedback
adiabatic logic that employs the principle of
adiabatic charge recovery. The low power PFAL
apply a sinusoidal power supply with magnitude
Vdd. Dynamic power contributes large power in
hardware design. So the design of a circuit with
less power consumption for low power application
has become critical concern. More energy is
dissipated during the switching events. PFAL
circuit dramatically reduces power dissipation by
reducing switching activity. This paper also
analysis the design of NAND, NOR, NOT logic gate
based on PFAL topology. The simulation result is
obtained using Tanner EDA Tools. Positive
Feedback Adiabatic Logic contributes the best way
to reuse the energy stored at the output node
capacitor instead of discharging it to the ground
node.
Keywords
Adiabatic logic, dynamic power, PFAL, low
power, switching activity.
1. INTRODUCTION
Now a day‟s Power dissipation is more
important problem in compact electronic devices.
This power dissipation causes the low battery
backup. So energy efficiency has become main
concern in the portable equipments to get better
performance with less power dissipation. As the
power dissipation in a device increases then extra
circuitry is necessary to cool the device and to
protect the device from thermal breakdown which
also results in increase of total area of the device.
In order to overcome these problems the power
dissipation of the circuit is to be reduced by
adopting different low power techniques [8], [9].
The present paper focuses on a novel energy
efficient technique called adiabatic logic which is
based on energy recovery principle. In this
technique instead of discharging the consumed
energy is recycled back to the power supply
thereby reducing overall power consumption. In
this paper the performance of universal gates is
evaluated in different adiabatic logic styles and
ISSN: 2231-5381
their results were compared with the conventional
CMOS design. As universal gates plays vital role in
most of the digital circuits, the present paper
mainly concern on its design. The performance of
this device was evaluated using Positive Feedback
Adiabatic Logic (PFAL). This paper analyzed the
universal logic gates with the help of PFAL styles
and their results were compared.
1.1. ADIABATIC LOGIC
Adiabatic” is a term of Greek origin that
has spent most of its history associated with
classical thermodynamics. It refers to a system in
which a transition occurs without energy (usually
in the form of heat) being either lost to or gained
from the system. In the context of electronic
systems, rather than heat, electronic charge is
preserved. Thus, an ideal adiabatic circuit would
operate without the loss or gain of electronic
charge.
Because of the Second Law of
Thermodynamics, it is not possible to completely
convert energy into useful work. However, the term
“Adiabatic Logic” is used to describe logic families
that could theoretically operate without losses. The
term “Quasi-Adiabatic Logic” is used to describe
logic that operates with a lower power than static
CMOS logic, but which still has some theoretical
non-adiabatic losses [1], [5], [6]. In both cases, the
nomenclature is used to indicate that these systems
are capable of operating with substantially less
power dissipation than traditional static CMOS
circuits.
Adiabatic circuits are low power circuits
which use "reversible logic" to conserve energy.
Adiabatic circuits are those circuits which work on
the principle of adiabatic charging and discharging
and which recycle the energy from output nodes
instead of discharging it to ground. Conventional
CMOS circuits achieve a logic „1‟ or logic „0‟ by
charging the load capacitor to supply voltage Vdd
and discharging it to ground respectively. As such
every time a charge-discharge cycle occurs, an
amount of energy equal to V2dd C is dissipated.
Unlike the conventional CMOS circuits, in
adiabatic circuits energy is recycled [3]. Instead of
http://www.ijettjournal.org
Page 4
International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 1- March 2016
discharging the capacitor to ground, the charge is
discharged to the power supply. Since the charge
has to be discharged to supply, the supply in
adiabatic circuits is a time varying one called the
power clock. It has been observed that among the
different waveforms for charging or discharging the
load capacitor, a ramp is more efficient and as such
trapezoidal power clocks have been used in many
adiabatic circuit styles [2]. Many adiabatic logic
circuits which dissipate less power than static
CMOS logic circuits have been introduced as a
promising approach in low power circuit design.
2.2 PFAL BASED NOT GATE
The inverter (NOT circuit) performs the
operation called inversion or complementation. The
NOT operation changes one logic level to the
opposite logical level. When the input is Low, the
output is high. When the input is high, the output is
low. The inverter changes one logic level to the
opposite level. In terms of bits, it changes a 1 to a 0
and 0 to 1. When a High level is applied to an
inverter input, a low level will appear on its output.
When a low level is applied to its input, a High will
appear on its output. PFAL based NOT gate is
shown in Figure 2.
2. MATERIALS AND METHODOLOGY
2.1 POSITIVE FEEDBACK ADIABATIC
LOGIC
The partial energy recovery circuit
structure named Positive Feedback Adiabatic Logic
(PFAL) has been used, since it shows the lowest
energy consumption if compared to other similar
families, and a good robustness against
technological parameter variations. It is a dual-rail
circuit with partial energy recovery [4], [10]. The
general schematic of the PFAL gate is shown in
Figure 1.
The core of all the PFAL gates is an
adiabatic amplifier, a latch made by the two PMOS
M1-M2 and two NMOS M3-M4, that avoids a
logic level degradation on the output nodes out and
/out. The two n-trees realize the logic functions.
This logic family also generates both positive and
negative outputs.
Figure 1 Basic structure of Positive Feedback
Adiabatic Logic (PFAL).
Figure 2 Structure of PFAL based NOT gate
2.3 PFAL BASED NAND GATE
NAND gate is an electronic circuit which
has two or more inputs but only one output. The
NAND gate is the natural implementation for the
simplest and fastest electronic circuits [7]. The
output is HIGH if at least one of its inputs is LOW.
The output is LOW only when all the inputs are
HIGH. The term NAND is a contraction of NOTAND. The NAND gate is a combination of an
AND gate followed by NOT gate. For 2 input
NAND gate, two NMOS transistors connected in
series is taken as pull down network and two
PMOS transistors connected in series is taken as
pull up network.
PFAL based NAND gate structure is
shown in Figure 3. This circuit works similar to
CMOS technology based circuit and also reduces
power by recycling the energy instead of
discharging it to ground.
The functional blocks are in parallel with
the PMOSFETs of the adiabatic amplifier and form
a transmission gate. The two n-trees realize the
logic functions. This logic family also generates
both positive and negative outputs.
Figure 3 Structure of PFAL based NAND gate
ISSN: 2231-5381
http://www.ijettjournal.org
Page 5
International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 1- March 2016
2.4 PFAL BASED NOR GATE
The NOR gate, like the NAND gate, NOR
gate is also useful logical element because it can
also be used as a universal gate. NOR gate can be
used in combination to perform the AND, OR and
Inverter operations.
NOR Gate is the combination of NOT gate
at the output of OR gate, hence NOR gate is type of
NOT-OR gate. NOR gate has two or more input
and only one output. The Output of NOR gate is
high when all inputs are low otherwise the output is
low.
PFAL based NOT gate is shown in Figure
4 which has similar operation to CMOS technology
with less power consumption.
Figure 4 Structure of PFAL based NOR gate
3. RESULTS AND DISCUSSION
The Positive Feedback Adiabatic Logic
based NAND, NOR, NOT gates are designed and
simulated using TANNER EDA Tools.
The schematic diagram for PFAL based
NAND gate is shown in Figure 5.
The schematic diagram for PFAL based NOR
gate is shown in Figure 7.
The transient analysis of PFAL based NAND
gate is shown in the Figure 8.
The schematic diagram for PFAL based NOT
gate is shown in Figure 9.
The transient analysis of PFAL based NAND
gate is shown in the Figure 6.
ISSN: 2231-5381
http://www.ijettjournal.org
Page 6
International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 1- March 2016
The transient analysis of PFAL based NOT
gate is shown in the Figure 10.
7)
www.slideshare.net/satyaJoshi1/logic-gates-and-or-notnor-nand-xor-xnor-gates-35078548?qid=8f8afd9a-74154e83-b2b6-dcabda54efc8&v=&b=&from_search=1
8) W.C. Athas, L.J. Svensson, J.G. Koller, N.Tzartzains, and
E. Y-C. Chou, “Low-power digital systems based on
adiabatic-switching
principles,”Very
Large
Scale
Integration. (VLSI) Syst., IEEE Transaction on, Vol.2,
Issue4, Dec., 1994, pp.398-407.
9) Sonal Jain, Prof. Monika Kapoor,” Design and Analysis of
CMOS and Adiabatic 4-Bit Binary Multiplier”
International Journal of Engineering Trends and
Technology (IJETT) – Volume 7 Number 2 - Jan 2014
10) B. Dilli Kumar, M. Bharathi “Design of Energy Efficient
Arithmetic Circuits Using Charge Recovery Adiabatic
Logic” International Journal of Engineering Trends and
Technology- Volume4Issue1- 2013
Table 1: Performance Analysis
GATES
NOT
NAND
NOR
POWER(mW)
BASIC
PFAL
87.694
83.79
87.5
50.05
92.31
64.3
4. CONCLUSION
We conclude that the proposed adiabatic
logic circuit is advantageous to ultra low power
applications. This paper shows the simulation result
of universal gates and also compares the power
values using Tanner EDA. The NOT gate, NOR
gate and NAND gate achieves power reduction of
23%, 36.1% and 42.8% respectively. Among three
gates, NAND gate consume less power. Hence it
proves that positive feedback adiabatic logic based
NAND gate can be used for ultra low power
circuits.
REFERENCES
1) Prasad D Khandekar, Shaila Subbaraman, and Abhijit V.
2)
3)
4)
5)
6)
Chitre Implementation and Analysis of Quasi-Adiabatic
Inverters International conference of engineers and
computer Scientist 2010 Vol II IMECS 17-19-201 Hong
Kong
Arsalan, Shams, “Charge-recovery power clock generators
for adiabatic logic circuits”, 18th International Conference
on VLSI Design, pp. 171- 174, 3-7 January 2005.
Indermauer.T and Horowitz.M, “Evaluation of Charge
Recovery Circuits and Adiabatic Switching for Low Power
Design, “Technical Digest IEEE Sym.Low Power
Electronics, San Diego, pp. 102-103, Oct. 2002.
Mukesh Tiwari, Jai karan Singh, Yashasvi Vaidhya
“Adiabatic Positive Feedback Charge Recovery Logic for
low power CMOS Design” IJCTEE, Volume 2, Issue 5,
October 2012.
Prof Mukesh Tiwari, Prof Jaikaran Singh, Mr Yashasvi
Vaidhya “Adiabatic Improved Efficient Charge Recovery
Logic for low power CMOS logic ” International journal
of Electronic Communication and Computer Engineering
pp 350-354 Vol 1 issue 5.
Samik Samanta Power Efficient VLSI Inverter Design
using Adiabatic Logic and Estimation of Power dissipation
using VLSI-EDA Tool Special Issue of IJCCT Vol. 2 Issue
2, 3, 4; 2010 for International Conference [ICCT-2010],
3rd-5th December 2010
ISSN: 2231-5381
http://www.ijettjournal.org
Page 7