International Journal of Engineering Trends and Technology- Volume3Issue4- 2012
Processor Technological Advancement
Revolution has come or yet to come?
Sapan kr. Gupta, Manuj Gupta, and Rahul Pandey
M.Tech ,Microelectronics and Embedded Technology JIIT Noida
Abstract—During the last decade Intel has introduced several
technologies for different generation processors. Different
architectures are added featuring enhanced energy efficiency,
power management, affordable performance, fast execution,
multitasking demands, optimized multithreading, CPU
performance boost, higher data throughput, improved
virtualization performance, smart security. This paper
provides insight into recently added technologies and
architectures. This paper discusses about the features enabled
by the latest technologies along with the current issues and
future prospects. This paper also deals with some constraints
and limitations of these technologies highlighting the upcoming
solution and the options.
Keywords-22nm technology,Tri-state transistor, MMX, Hyper
Threading,turbo boost
I.
INTRODUCTION
The revolution of the Internet, embedded systems and
almost all the technologies is powered by ever-faster systems
demanding high performance of processor. To keep up with
this demand we cannot rely entirely on traditional
approaches to processor. Therefore a lot of new
technological aspects are introduced.
These different technologies are playing an important
role in specified industries and have become the necessity of
the increased usage. These technologies leaders are Intel,
IBM, National Instruments and many other corporations
which are continuously working to resolve the issues related
to it. These technologies are enabling various features to the
users which they always wanted to have. A shape to the
dreams, it is!
The recently added technologies are lithography which
results into lower cost, hyper threading for fast execution,
Turbo boost for power management, anti-theft for security
issues, MMX technology for video and graphics
enhancement. These latest technologies and the issues related
to these technologies are discussed in the paper.
II.
breakthrough of 22nm technology for the providing an
unprecedented combination of improved performance and
energy efficiency, working further up to 10 nm logic
technology for the processor.
This technology uses Tri-Gate transistors. This journey
of Lithography from 2nd generation SiGe strained silicon to
this 22nm Tri-Gate technology includes the High-k Metal
gate revolution.
Unlike bulk transistor, partially depleted SOI and fully
depleted SOI, Tri-Gate transistors form conducting channels
on three sides of a vertical fin structure, providing “fully
depleted” operation. Full depletion is achieved with relaxed
body dimensions over other fully-depleted transistor
structures
To increase the total drive strength these transistors may
have multiple fins connected together for higher
performance. Examination of layout issues shows that the
fin-doubling approach from using a spacer printing technique
results in an increase in drive current of 1.2 times that of a
planar device for a given width, though the shape of the
allowed Tri-Gate fins has certain restrictions.
B. Hyper Threading Technology:
Hyper-Threading Technology makes a single physical
processor appear as multiple logical processors. In this, there
is one copy of the architecture state for each logical
processor, and the logical processors share a single set of
physical execution resources.
From a software point of view, this means operating
systems and user programs can schedule processes to logical
processors. From a software perspective, once the
architecture state is duplicated, the processor appears to be
two processors. The number of transistors to store it is an
extremely small in comparison to total. The die area cost of
this implementation was less than 5% of the total die area.
\
RECENT PROCESSOR TECHNOLOGIES AND
ARCHITECTURES
A.
22nm Transistor Technology
One of the fundamental issues facing scaling of CMOS
transistors is the ability to control the transistor leakage
current (Ioff), while at the same time maintaining high drive
current. To resolve such issues, switching from 32nm
technology Intel has now introduced a technological
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Figure 1.
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Processor with Hyper Threading Technology
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A logical processor may be temporarily stalled for a
variety of reasons, including servicing cache misses,
handling branch mispredictions, or waiting for the results of
previous instructions. No logical processor can use all the
entries when two active software threads2 were executing.
This is resolved by partitioning or limiting the number of
active entries each thread can have.
C. Turbo Boost Technology
Turbo Boost technology automatically allows processor
cores to run faster than the base operating frequency if the
processor is operating below rated power, temperature, and
current specification limits. For this technology the software
used to calculate the operating core frequency needs to be
updated frequently. For this also this technology provides a
frequency calculating algorithm. To monitor the current
behavior of core in the processor, concept of core states
comes into the limelight.
State
Representation
C0
(Active Core)
C1
(Active Core)
C3
(Inactive Core)
C6
(Inactive Core)
Behavior
Active state, instructions are
being executed
Halt State, no instructions are
being executed
Core PLLs are turned off, and all
the core caches are flushed
The core PLLs are turned off, the
core caches are flushed and the core
state is saved to the Last Level Cache.
Table A. State Representation
Turbo Boost technology can be engaged with any
number of cores or logical processors enabled and active,
resulting the increased performance in single and multithreaded loads. If two cores are off, the remaining active
cores can run at a higher frequency while the processor
package stays within the overall power and thermal limits.
The maximum frequency is dependent on the number of
active cores and varies based on the specific configuration on
a per processor number basis. The amount of time the
processor spends in this technology state will depend on
workload and operating environment.
D. Anti-theft Technology
In the healthcare industry, keeping patient data secure is
not just a challenge, it is a legal necessity. It secures the
system even if the OS is re-imaged, the hard drive is
replaced, or the boot order is changed to a different device
(such as a USB key, CD, DVD, or another hard drive). When
activated, the anti-theft responses block the boot process
regardless of the boot device, and render the laptop a “brick”
without destroying the data. This protects the system while
retaining the data. To reactivate a system that was locked
down, the user simply enters a strong, one-time passphrase in
the preboot reactivation screen, and the system is returned to
its normal working state. Rapid response and recovery is a
key advantage for healthcare professionals.
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E. MMX Technology
In Before going to the MMX technology, it is necessary
to understand the SIMD(Single Instruction Multiple Data)
which is a class of Flynn’s Taxonomy. In accordance with
it, a computer which exploits multiple data streams against a
single instruction stream to perform operations which may
be naturally parallelized.GPU (Graphics processing unit)
represents the best use of SIMD. Closely related to vector
processing, the basic idea is to operate the same instruction
sequence simultaneously on a large number of discrete data
sets.
When designing a SIMD machine, the primary factors to
consider
are
processing
element
selection,
communications/network topology, instruction issue.
Although SIMD machines are very effective for certain
classes of problems (namely embarrassingly parallel
problems with very high parallelism), they do not perform
well universally. SIMD architectures typically do not scale
down in competitive fashion when compared to other style
multiprocessor architectures.
The MMX architecture has extended the general purpose
processor architecture, to provide the benefits of SIMD for
media applications. It adopts this existing architecture
efficiently with a great compatibility.
The definition of MMX technology was guided by
priorities like substantially improve the performance of
multimedia, communications, and emerging Internet
applications. Using advanced computer-aided profiling
tools, the common characteristics of key code sequences are
found as Small, native data types (for example, 8-bit
pixels,16-bit audio samples), Regular and recurring memory
access patterns, Localized, recurring operations performed
on the data Compute-intensive.
For media applications and SIMD, the basic orientation
must posses packed data format, Conditional execution,
saturating arithmetic and wrap-around arithmetic, fixedpoint arithmetic, repositioning data elements within packed
data format, data alignment. MMX technology features
include:
 New data types with small data elements together
into one register.
 An enhanced instruction set that operates on all
independent data elements in a register, using a
parallel SIMD fashion.

New MMX registers
F. Demand Based Switching (DBS)
In DBS is used for power management in which the
applied voltage and clock speed of a microprocessor are kept
at the minimum necessary levels for optimal performance of
required operations. DBS enables a processor to be operated
at a reduced voltage and clock speed until more processing
power is required. This is achieved by monitoring the
processor’s use by application-level workloads. The CPU
speed is reduced when it’s running idle and increased
whenever the load increases. The process steps for this are:
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



DBS is made enabled.
The workload is monitored. If the processor
utilization is reduced then go further else wait
If workload reduced then downshift voltage for
processor, this’ll further reduce the clock speed.
The heat generated is reduced, cooling need are
reduced efficiently.
III. ISSUES AND FUTURE ASPECTS
In all the technologies discussed in the paper are now
available in the Intel core i5/core i7 processor except DBS
enabling, which is soon going to be enabled in it. Some
constraints and the future aspect of these technologies are as
follows
A. 22 nm Technology
The majority of the industry is working on a 22nm
process at present, including Intel's recently-launched Ivy
Bridge processors. 10 nm resolution is difficult to achieve in
a polymeric resist, even with electron beam lithography. In
addition, the chemical effects of ionizing radiation also limit
reliable resolution. The company has a big hurdle ahead of it,
as smaller the process, the larger the challenge. As the
component size decreases and the gaps between components
get smaller, numerous issues raise their heads. The biggest of
these, current leakage, calls for a radical rethink to how
semiconductors are designed in order to smash what has
been termed the '10nm physical gate length barrier’.
According to the research and development pipeline
espoused by the company's slides, 2015 will see the
production of semiconductor components based on a 10nm
process size, quickly followed by 7nm and 5nm parts.
B. Hyper Threading Technology
To take advantage of hyper-threading performance, serial
execution can not be used. In this threads are nondeterministic and involve extra design and the threads have
increased overhead. Major sharing schemes in this
technology are partition, threshold, full Sharing. In these
schemes also the conflicts occurs. More recently HyperThreading has been criticized as being energy inefficient. For
example, specialist low power CPU design company ARM
has stated SMT can use up to 46% more power than dual
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CPU designs. Furthermore, they claim SMT increases cache
thrashing by 42%, whereas dual core results in a 37%
decrease.
C. Power Management
The processor shows some power saver modes,in turbo
boost it is needed to be a core idle but if the processor
continue processes the data,it may be inefficient.In this case
battery life can be pro-longed with the help of Enhanced
SpeedStep technology, which reduces processor voltage and
frequency and the power consumption is reduced
IV. CONCLUSION
As microprocessors have evolved from simple singleissue architectures to the more complex multiple-issue
architectures, many more resources have become available to
the microprocessor with a lot of new features. We are
convinced that the Intel has made a maximum of these
technological utilization. In these architectures and
technology innovation a lot of new perspective are yet to be
added and many issues to be resolved.
ACKNOWLEDGMENT
The authors thank the assistance provided by Rahul
Singh M.P.E.C.Kanpur and Aditya Pathak of YLM Tube
Solutions&Service India Pvt. Ltd. Additional thanks go to
Himanshi Sharma,Ragini Rai and Pushkar Mishra for their
great effort and inspiring me for this paper.
REFERENCES
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Compliance with New Healthcare Rules”
Intel Architectural Server White Paper “Power Management in Intel®
Architecture Servers”
Mark Bohr
and Kaizad Mistry Intel White Paper “Intel’s
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Intel Technology Journal,Volume 06,Issue 01,Published February 14,
2002,ISSN 1535766X “Hyper-Threading Technology”
Millind Mittal, Alex Peleg and Uri Weiser Intel White Paper
“MMX™ Technology Architecture Overview”
Intel White Paper November 2008 “Intel® Turbo Boost Technology
in Intel® Core™ Microarchitecture (Nehalem) Based Processors”
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International Journal of Engineering Trends and Technology- Volume3Issue4- 2012
Figure 2.
Figure 3.
Traditional Planner Transistor andTri-state transistor with multiple finns
Transistor Operation:Transistor “101”current voltage characteristics and fully depleted characteristics of Tri-state Transistor
Figure 4.
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Power variation with P-state change and CPU utilization, without turbo mode and with turbo mode
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International Journal of Engineering Trends and Technology- Volume3Issue4- 2012
Figure 5.
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Performance from Hyper Threading Technology on an OLTP workload and webserver benchmark
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