International Journal of Engineering Trends and Technology- Volume3Issue2- 2012
Modeling and Analysis of User-DefinedConstant-Switching Frequency DSTATCOM
for Three Phase Four Wire Distribution System
S. SURESH1, Dr. DEVARAJAN2,N.VIDHYA3,V. RAJASEKARAN4
1
S. SURESH ,Assistant Professor/ EEE , Kalaignar Karunanidhi Institute of Technology, Coimbatore, India
Dr. DEVARAJAN2, Professor/EEE, GCT, Coimbatore, India
3
N.VIDHYA , EEE,KalaignarKarunanidhi Institute of Technology, Coimbatore, India
V. RAJASEKARAN4, EEE, Kalaignar Karunanidhi Institute of Technology, Coimbatore, India
Abstract - This paper deals with modeling and analysis of
User Defined Constant Switching (UDCS) frequency
current-controlled based four-leg DSTATCOM. The first
three-phase legs are operated in hysteresis current tracking
mode, and the neutral is operated by fixed switching square
pulses of desired frequency. Consequently, the first three
legs get tuned to the fourth leg’s user defined frequency.
Analytical expressions arederived to specify the range of
frequency
at
which
the
scheme
functions
effectively. Design procedure for selection parameter of the
four leg inverter such as hysteresis band, DC link voltage,
DC link capacitor and inductor are suggested, and
simulations are done to value the design procedure for a
UDCS-controller based DSTATCOM. Comparison is made
between the performance of the UDCS controlled
DSTATCOM and conventional hysteresis-controlled
DSTATCOM and presented.
Index terms- Active power filter, constant switching
frequency, current control, design, voltage source
inverter (VSI).
I.INTRODUCTION
Out of many control strategies for voltage source
inverters, the one which is mostly used is hysteresis
current control method. Due to its simplicity, fast
response and robustness, it is been preferred. But its
main disadvantage is that it gives variable switching
frequency. In case of four-leg topology, this scheme
requires high switching frequency to track the
reference neutral current. Many methods have been
proposed to attain the constant switching frequency
for inverter. The easiness in filter design forms the
greater advantage. Many attempts are made in
reduction of the switching frequency to reduce the
electromagnetic
interference
and
switching
ISSN: 2231-5381
losses.The variable hysteresis band methods used to
achieve constant switching frequency [7]–[12] are
quite computation intensive.In the proposed ramp
comparison technique in [3], choice of carrier signal
frequency is very important. The predicted current
control in [15]–[17] is also computation exhaustive.
The error drift in the currents helps to achieve
reduction in switching frequency [18]. Spacevector
modulation with its variants results in complexity
inits operation and also in hardware implementation
as it requires thedefinition and sequencing of the 3-D
space vectors [19]–[21].
The authors had proposed a novel scheme calledas
user-defined constant switching (UDCS) frequency
currentcontrol method for three phase four wire
distribution network that achievethe fixed switching
frequency by exploiting the zero vectorstates [22],
[23].Provided, this scheme allows theuser to set the
switching frequency forall the switches of the
inverter.Reduction in switching frequency can also be
obtained.These objectives are parallely obtained by a
simplecontrol method, which is free from additional
computation,circuitry,or
modulation.Analytical
expressions are derived thatgive guidelines for the
user to choose suitable switching frequency(fsw) to
get advantage of zero-vector states. The designof
other inverter parameters, such as dc-link voltage
(Vdc),dc-link capacitor (Cdc), interface inductor (Lf),
and hysteresisband (h) are also detailed. It is shown
that the effective operationof this controller requires
the dc-link voltage to be above aminimum limit
specified by the design.
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International Journal of Engineering Trends and Technology- Volume3Issue2- 2012
II. UDCS CONTROLLER FOR FOUR-LEG
DSTATCOM
A four-leg VSI-based DSTATCOM is shown in Fig.
1. Eachpower switch has an anti-parallel diode (not
shown in the figure for sake of clarity). The block
diagram of UDCS current control strategy is given in
Fig. 2. The current error signals efa, efb,and efcare
generated for the legs a, b, and c by comparing
thefilter currents if a,if b, and if cwith their respective
referencecurrents ifaref, ifbref, and ifcref. The hysteresis
controller thengenerates the required switching
signals A1,A2, B1, B2, C1,and C2 so as to track the
filter currents within a hysteresis band.Unlike the
conventional scheme, tracking of leg-n is
avoided,and a switching pulse of fixed user-defined
frequency with 50%dutycycle and its complement
are used as switching pulses D1and D2 .It is
confirmed that for every switching cycle two UC
states (UC-1 and UC-0) occur, where UC-1 signifies
the state when switches A1 ,Bn , C1 , andD1 are ON
and UC-0 refers to the state when all are OFF.
Similarly, ifthe instant t2 gets delayed such that it
overlaps instant t3, it results in maximum possible UC
state, giving the minimum switching frequency limit.
Fig. 3. Switching signals for top switches of four legs
of inverter.
Fig 4.Equivalent circuit for switching state (1 0 0 0).
III. ANALYSIS OF UDCS CONTROLLER
Fig 1.Four leg VSI based DSATCOM
Onepossible snapshot of the switching pulses of the
top switchesof the four legs is shown in Fig. 3. At the
instants t2 and t4, the UC state is alwaysfragmented
by the variation in the state of the user-defined
switchingpulse of leg-n. It can be detected thatthe
other legs follow this change one by one. Thus, all
theswitches operate at constant frequency as set by
the user forthe fourth leg. From the figure, it can be
realized that lowerthe user-defined frequency, more
is the duration of UC stateand vice versa. Thus, the
selection of the user-defined frequencyshould be
within a range,constrained limits.The upper limit of
frequency is obtained when instant of statuschange of
leg-n, say t2 occurs earlier such that it overlaps t1
.Thus, the duration of UC state reduces to zero.
ISSN: 2231-5381
This section deals with study of the voltages
developed across the interface inductances during
various switching states of the four-leg inverter [24].
Consider the switching state (1 0 0 0), i.e., switches
A1 ,B2, C2, and D2 are ON. Fig. 4 shows the
corresponding equivalent circuit for this state. Here,
va,vb, and vcare the instant supply voltages, and vLa,
vLb, vLc, and vLnare the voltage drops across the
interface inductors.
Writing KVL
Vdc− vLa− va+ vb+ vLb= 0
Vdc− vLa− va+ vc+ vLc= 0
Vdc− vLa− va+ vLn= 0.
(1)
The equation (1) can be rewritten as
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International Journal of Engineering Trends and Technology- Volume3Issue2- 2012
1 −1 0
0
1 0 −1 0
1 0 0 −1
=
−
−
+
+
cycle can be fragmented into eight small time periods
(p1 to p8 ), and is described in Table II along with its
switching states, respectively. It is not possible to
find out these eight unknowns with the four
instantaneous equations that can be formed from the
four legs. Thus, the mathematical analysis is done for
the controlling (upper and lower) values of the userdefined switching frequency.
(2)
−
TABLE I
INDUCTOR VOLTAGES FOR DIFFERENT
SWITCHING STATES
Phases
a
1
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
b
0
1
0
0
0
1
1
1
0
0
1
1
0
1
1
0
c
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
n
0
0
0
1
1
1
0
0
0
1
0
1
1
1
1
0
vLa
vLb
vLc
vLn
3Vdc/4-va
-Vdc/4-va
-Vdc/4-va
-Vdc/4-va
-Vdc/2-va
-Vdc/2-va
-Vdc/2-va
-Vdc/2-va
-Vdc/2-va
-Vdc/2-va
Vdc/4-va
Vdc/4-va
Vdc/4-va
-Vdc/4-va
-va
-va
-Vdc/4-vb
3Vdc/4-vb
-Vdc/4-vb
-Vdc/4-vb
-Vdc/2-vb
Vdc/2-vb
Vdc/2-vb
Vdc/2-vb
-Vdc/2-vb
-Vdc/2-vb
Vdc/4-vb
Vdc/4-vb
-Vdc/4-vb
Vdc/4-vb
-vb
-vb
-Vdc/4-vc
-Vdc/4-vc
3Vdc/4-vc
-Vdc/4-vc
Vdc/2-vc
-Vdc/2-vc
Vdc/2-vc
-Vdc/2-vc
Vdc/2-vc
-Vdc/2-vc
Vdc/2-vc
-Vdc/2-vc
Vdc/2-vc
Vdc/2-vc
-vc
-vc
-Vdc/4
-Vdc/4
-Vdc/4
3Vdc/4
Vdc/2
Vdc/2
-Vdc/2
-Vdc/2
-Vdc/2
Vdc/2
-3Vdc/4
Vdc/4
Vdc/4
Vdc/4
0
0
The inductor voltages can be obtained as
vLa= (3/4)Vdc− va
vLb= (−1/4)Vdc– vb
vLc= (−1/4)Vdc− vc
vLn= (−1/4)Vdc.
(3)
As given in Table I voltagesacross the interfacing
inductors can be calculated for all other switching
state, in a comparable manner. These voltages are
used to find the variations in filter currents during
these switching states. As shown in Fig. 5 any one of
the switching transition patterns possible is chosen
for examination. This switching arrangement occurs
during the zero-crossing period of the phase-a
voltage and, consequently instantaneous voltages of
the entire phases are identified. The points at which
the filter currents hit the hysteresis band limits as a
result of switching decisions can be identified by “•”
mark in the figure. Thus, by connecting these points
the path of the current can be found. One switching
ISSN: 2231-5381
Fig. 5. Switching signals and filter currents (actual,
reference, and hysteresis Ban limits).
A. Lower Limit of User-Defined Switching Frequency
As explained in the previously, when the UC states p4
and p8 extend to the maximum possible extent and to
the end of the intervals p5 and p1, the lower limit of
the UDS frequency is obtained. Thus, p5 and p1 in
Fig. 5 are made equal to zero, and the figure is
redrawn, as shown in Fig. 6. During p8 , the leg-b
current travels from the lower limit to upper limits of
the hysteresis band, causing a change of 2h (in
amperes). Using Tables I and II
TABLE II
SWITCHING STATES CORRESPONDING TO
EACH TIME INTERVAL
P1
P2
P3
P4
P5
P6
P7
A1
1
1
0
0
0
0
1
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B1
1
0
0
0
0
0
0
C1
1
1
1
0
0
1
1
D1
0
0
0
0
1
1
1
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International Journal of Engineering Trends and Technology- Volume3Issue2- 2012
P8
1
1
=
1
1
(9)
(4)
During p2, p3, p4, p6, p7 , and p8 , the net change in
leg-n current is zero. Therefore
(5)
During p4 , the change in the leg-c current is−2h (in
amperes).
Thus
.
(6)
The change in current in leg-a during p3 ,p4 , and p6 is
−2h
(in amperes).
Thus
=-2h.
(10)
From (5) to (10), the following matrix equation is
obtained
(7)
.
(11)
Here, the values of va, vb, and vcare known as the
phase-a voltage passes through zero crossing for the
chosen switching pattern. Thus, from (5), (6), and
(11), the lower limit of the switching frequency
flow_lim can be calculated as
.
(12)
Fig 6. Switching signals and filter currents (actual,
reference, and hysteresis band limits) corresponding
to lower limit of user-defined switching frequency.
Similarly, during p2, p3, p4, p6 , and p7 , the change in
leg-b current is −2h (in amperes). Thus
.(8)
The change in the current in leg-c during p6, p7, p8, p2
, and p3 is 2h (in amperes). Thus,
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International Journal of Engineering Trends and Technology- Volume3Issue2- 2012
Fig. 7. Switching signals and filter currents (actual,
reference, and hysteresis band limits) corresponding
to upper limit of user-defined switching frequency.
B. Upper
Frequency
Limit
of
User-Defined
Switching
As the duration of the UC states decreases to zero,
the upper limit of the user-defined switching
frequency is obtained. Thus, p4 and p8 in Fig. 5 are
made zero, and the figure is redrawn inFig. 7.During
p1 , the leg-b current traverses a change of 2h (in
amperes). Thus
1=−
.
( / )
(13)
In leg-c during p5 , the change in current is−2h (in
amperes). Thus
5=−
.
( / )
(14)
During p3, p5 , and p6 , the change in leg-a current is
given by
( / )
( / )
( / )
( / )
6+
3+
( / )
( / )
5+
7 = −2ℎ.(16)
Change in leg-c current during p6, p7, p1, p2 , and p3 is
( / )
6+
( / )
( / )
2+
−2ℎ
7+
( / )
( / )
1+
+
( / )
5+
−(1/2)
( / )
2ℎ
6+
2+
( / )
−(1/4)
3
7=
(18)
Using (13)–(18), the following matrix equation can
be written
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1
4
−
1
2
⎤
⎥
⎥
⎥.
⎥
⎥
⎥
⎦
( / )
2ℎ
−
( / )
+
3
4
−
−
1
4
⎤
⎥
⎥
⎥
⎥
⎥
⎥
⎦
(19)
Thus, the upper limit of the switching frequency
fupplimcan be calculated using (13), (14), and (19) as
=
_
(
)
.(20)
The UDCS scheme can efficientlyperform only if
the userdefined frequency fswis chosen between the
specified limits, i.e.,
<
<
.
IV. MODELING OF THE UDCS CONTROLLER
The modeling of the UDCS controller involves the
selection of the suitable switching frequency and
voltage source parameters such as dc-link voltage,
the value of dc storage capacitor, the value of
interface inductor, and the hysteresis band. A threephase 440-V distribution system is considered for the
formulation. But, the end results are independent of
the supply voltage, and thus, can be used for
modeling VSI parameters for any supply voltage.
A.Selection of the DC-Link Voltage
In leg-n, during p1, p2, p3, p5, p6 , and p7 , the current
change is
1+
−
/ )
2ℎ
0
3=
(17)
−(3/4)
−
The done for other switching patterns also converge
to similar results.
In leg-b, change in current during p2, p3, p5, p6 , and
p7 is given as
2+
1
2
1
−
2
1
2
−
5+
6 = −2ℎ.(15)
( / )
×
⎡
⎢
2
⎢
3
=⎢
6
⎢
7
⎢
⎢2ℎ
⎣
1
−
4
1
−
−
4
3
−
4
1
−
4
2ℎ
(
−
_
( / )
3+
⎡
0
⎢
1
⎢−
−
⎢ 2
⎢ 1
−
⎢ 2
1
⎢
−
⎣
2
The suitable choice of the dc-link voltage is
essential for the appropriate operation of this scheme.
A factor m is defined, which is the ratio of Vdcand
peak value of phase voltage. The correct functioning
of the UDCS method requires the presence of
nonnegative (positive or zero) values for the time
periods fromp1 to p8 such that state transition would
enable theswitching signals of legs a, b, and c to
follow the user-defined signal.
TABLE III
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International Journal of Engineering Trends and Technology- Volume3Issue2- 2012
VARIATION OF LIMITING FREQUENCIES AND
TIME INTERVALS
WITH DC-LINK VOLTAGE
resulting change in energy stored in
given by
(1/2)
m
Vdc
(Volts)
3.1
3.3
3.5
3.7
3.9
4.1
1113.7
1185.6
1257.4
1329.3
1401.1
1473
Upper Limit
Fupp_lim
Time
(Hz)
Interval
p1
5394
5990.5 Negative
6561.7
7111.5 Positive
7643.4
8159.8
Lower Limit
Flow_lim
Time
(Hz)
Interval
p2
2855.2
3077.5 Negative
3274.4
3450.1 Positive
3607.7
3749.9
Thus, the value ofmis varied and fupplim, p1
(corresponding to upper limit), flow_lim, and p2
(corresponding to lower limit) are calculated using
(20), (13), (12), and (11), respectively. Table
IIIillustrates these values for h = 0.4 (in amperes) and
Lf= 30mH. It can be observed that the time intervals
p1 and p2 attain negative values formless than 3.5.
Thus, the UDCS scheme can effectively work only
for values of m equal to or greater than 3.5. This
limiting value of m is verified by simulation studies
too. Also by extensive calculations, it has been found
that this minimum value of m holds good for any
value of h and Lf, for both upper and lower limits of
switching frequency. As the dclink voltage should,
thus, be kept as low as possible, the authors choose
the value of m near to the minimum value, say 3.7.
B. Selection of the DC Storage Capacitor
The design of the dc storage capacitor is based on its
ability to normalize its voltage under transient
conditions. Rate of energy of the system in joules per
second is, therefore, given by X × 1000 J/s. Let us
further assume a worse case when the load changes
from a tenth full load to a full load, i.e., from X/10 to
X. The compensator has to supply this from the
capacitor. The reduction in capacitor voltage would
cease in half-a-cycle or at the worst one cycle by the
action of the moving average filter in the control
algorithm. The PI controller action does not come to
picture as it responds very slowly. Thus, the energy
to be supported by the dc capacitor is given as
=
(21)
Wheren is the number of cycles, which is considered
as one. If the transient results in capacitor voltage
change from 3.7Vmto 3.3Vmor vice versa, the
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[(3.7
) − (3.3
capacitor is
) ]=
. (22)
The aforementioned equation implies that
=(
(
/
)
.
)
( .
)
.
(23)
TABLE IV
VARIATION OF LIMITING FREQUENCIES
WITH h AND Lf
H (Amps)
Lf
(H)
0.02
0.02
0.02
0.03
0.03
0.03
0.04
0.04
0.04
0.2
0.3
0.4
0.2
0.3
0.4
0.2
0.3
0.4
Fupp_lim
(Hz)
21334.1
14222.8
10667
14222.8
9481.8
7111.5
10667.2
7111.5
5333.6
Flow_lim
(Hz)
10350.1
6900
5175.1
6900
4600
3450.1
5175
3450.1
2587.6
C . Selection of Switching Frequency
Eq (12) and (20) gives the lower limits and upper
limits of switching frequencies for the UDCS
scheme. An effort is made to express these
controlling frequencies in the form of simple and
handy equations.Ffrequency limits are computed for
different values of h and Lf, using(12) and
(20)corresponding to m = 3.7, as given in Table IV.
From the obtained values offlowlim and fupplim, the
following relations are deduced for the lower limits
and upper limits of switching frequencies
=
_
_
=
.
.
.
(24)
.(25)
The earlier equations describing the limiting cases are
valid for any value of h and Lf .Thus, the switching
frequency, in general, can be expressed as
=
(26)
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WhereKswvaries between 15.6 and 32.1 for the
limiting cases. The practical restriction on switching
frequency offered by the semiconductor switch is
also to be considered while making the choice.
D. Selection of the Hysteresis Band (h) and Interface
Inductor (Lf )
The value of Kwis to be suitably selected. Its choice
as 15.6 results in theupper limit of switching
frequency. But this is not suitable dueto higher
switching losses and EMI considerations.
TABLE V
SIMULATION PARAMETERS
System voltage: 440 V (L-L voltage), 50 Hz
Loads:Za=60+j13.2Ω.Zb=100+j15.7Ω,Zc=140
+j18.85Ω and 3Φ full bridge diode
rectifier feeding a R-L load of100Ω,
0.1 H
Interface inductors (Lf) : 30 mH with series
resistance of 0.1 Ω
Dc link voltage (Vdc): 1330V
Dc Capacitor (Cdc): 1000 µF
Hysteresis band (h): 0.4 A
Leg-n switching frequency (fsw): 5 kHz
Thus, a tradeoff value is chosen for Kw between
these limits, say 22.
Thus
ℎ =
.
(27)
computed using (23) as 1000 µF. Theuser-defined
switching frequency fswbeing is taken as 5 kHz. The
value of h is taken as0.4 A, for a maximum 10 A
rated current. The value of interface inductor Lf is
calculated using (27)and is found to be 30mH. It is
ensured that fswlies within itslimits (3.45 kHz -7.1
kHz ), obtained using(24) and (25). The designed
VSIparameters are shown in Table V. The load
contains an unbalancedR–L load along with a threephase diode rectifier. Thesevalues are used for
simulation studies as shown in Fig. 1. Thetheoryof
instantaneous symmetrical componentsis used for the
generationof the reference filter currents [25].
B. Performance Indexes
The designed UDCS controller’s performance is
comparedwith the conventional hysteresis controller
using thefollowing indexes.
1)Total Mean Switching Frequency: The mean
switchingfrequency of any leg-k is calculated as the
number ofswitching cycles in one time period of
power cycle. The totalmean switching frequency, fav
total is thus defined as follows:
=∑
_
(28)
, , ,
WhereNkis the number of switching cycles in leg-k
during onecycle period T of the system voltage.
2) Switching Frequency Deviation Index: The
switching frequencydeviation index (DI) is prelude in
order to account forthe drift in the instantaneous
switching frequencies fromthe mean switching
frequency. The DI for any leg-k is definedas
=
∑
_
_
, fork = a, b, c, and n
_
The value of h cannot be raised beyond a limit as it
develops poor quality of compensation. Thus, the
value of h is chosenbetween 4% to 10% due to the
above mentioned reasons. It is also clear that the
switching frequency f sw, hysteresis band h, and
interface inductance Lfare related to one other.
Therefore, just as the choice of switching frequency
can be made over a range, the parametric variations
like variation in the value of Lf
V. SIMULATION STUDIES
A. Design Example
A three-phase 440-V distribution power network is
contemplated.The dc-link voltage is computed
as1330 V, considering mas 3.7, Taking a 10-kVA
system, i.e., X = 10, n = 1,andT = 0.02 s, Cdcis
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(29)
Wherefk_instand fkavare the instantaneous and
meanswitching frequenciesduring one power cycle.
This index is a goodindicator of the dependability of
the switching frequency. Thus, avery low value of DI
is wanted.
3) Percentage Total Harmonic Distortion: The
percentagetotal harmonic distortion (% THD) of the
compensated sourcecurrents indicates the quality of
the load compensation.
C. Simulation Results
The DSTATCOM based on the nominated design
procedureis cable of compensating the unbalance and
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harmonicsin load currents. Fig. 9(a) and (b),
showstheinstantaneous
and
mean
switching
frequencies for legs a, b,c, and n for the conventional
hysteresis and UDCS controlstrategies,respectively.
The supply phase voltages, load currents,and the
compensated source currents are shown in Fig. 8.
Here,fainst, fbinst, fc inst, and fninstrefer to the
instantaneousswitching frequencies for legs a, b, c,
and n. These are representedas vertical lines, whereas
faav, fbav, fc av, and fnavrefer to the corresponding mean
values and arerepresented ashorizontal lines. The
indexes based on the simulationresults are tabulated
in Table VI. The proposed UDCS controllershows
the decrease in switching frequency. The reduction in
the totalmean switching frequency is 17.2%. All the
legs have gottuned to the user-defined frequency of 5
kHz.Fig. 9(a) shows the frequency variation of
conventional scheme. Fig. 10(a) and (b) shows the
distinguishing harmonic spectrum of the phase-a
source currents for theconventional hysteresis and
proposed UDCS. In the proposed scheme, the 100th
harmoniccomponent (corresponding to the userdefined switching frequency 5 kHz) is seen to be
dominant. Thus, the simulationresults value the
UDCS design procedure.
VII. CONCLUSION
This paper has put forth the modeling and design of a
UDCS frequency current-control-based three phase
four wire distribution network. Analytical
expressions were derived that enables the user to
select the switching frequency for the proper working
of the UDCS method. Guidelines were also proposed
for the choice of inverter parameters like hysteresis
band, DC link voltage, DC link capacitor and
inductor. The proposed modeling procedure was
valued by simulation and experimental studies on a
three-phase four-wire distribution network.
REFERENCES
[1] M. P. Kazmierkowski and L. Malesani, “Current control
techniques for three-phase voltage-source PWM converters: A
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