International Journal of Engineering Trends and Technology (IJETT) – Volume22 Number 7- April 2015
Controlling of Moving Objects using Power-Pc
K. Abhijith1, S. Sri Surya Srikanth2
1
M. Tech student, embedded systems & Department of E I E& GITAM University, Visakhapatnam, Andhra Pradesh, INDIA
2
Asst.Professor &Department of E I E& GITAM University, Visakhapatnam, Andhra Pradesh, INDIA
Abstract— This paper deals a Mission Computer which is a
ruggedized computer designed to carry out various airborne
functions, viz. control and guidance, it also carries out the health
of on-board systems. This is a miniaturized subsystem having
adequate memory and high speed computing capabilities
occupying minimum space and having minimum weight. Mission
computer to be designed based on power pc, adc, dac. power pc
supports interfaces like pci, usb, ethernet, sio, timers, and
sdram/ddram etc. the processor to be interfaced with ram, flash
and nvram.fpga to be used in-order to implement logic
derivation .
– PCI initiator and target operation
– 32-bit PCI Address/Data bus
– 33 and 66 MHz operation
Keywords—Transceiver, analog to digital converters (ADC),
digital to analog converters (DAC), optocouplers/isolators,
flash, SDRAM (synchronous dynamic random access memory)
I. Introduction
In this paper a high-performance embedded processor from
Free-scale Semiconductor, Inc. (formerly Motorola)
specifically meets all of these design challenges in one
compact, low-power device. Specifically, the MPC5200
integrates a high performance MPC603e core capable of
processing 760 Dhrystone 2.1 MIPS at 400 MHz at a
temperature range of 40 to 85 C. The PowerPC core also
utilizes a high-performance, double-precision Floating Point
Unit (FPU) to accelerate complex math operations in parallel
with other critical tasks. A 105 C version operating at 264
MHz (500 MIPS) is also available for use outside of the driver
compartment where higher-temperature ratings may be
required
Key Features:
– 16 KB Instruction cache, 16 KB Data cache with Double
precision FPU and Critical interrupt capability
• SDRAM / DDR Memory Interface with 133 MHz operation
– SDRAM and DDR SDRAM support
– 256 MB addressing range per CS, two CS available
– 32-bit data bus ,Built-in initialization and refresh
• Flexible multi-function External Bus Interface
– Supports interfacing to ROM/Flash/SRAM memories or
other memory mapped devices
– 8 programmable Chip Selects
• Peripheral Component Interconnect (PCI) Controller
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Read and write accesses to the SDRAM are burst-oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA[1:0]
select the bank; A[12:0] select the row). The address bits
registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst
lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a
burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated
at the end of the burst sequence.The SDRAM uses an internal
pipelined architecture to achieve high-speed operation.
Precharging one bank while accessing one of the other three
banks will hide the PRECHARGE cycles and provide
seamless, high-speed, random-access operation.
II. DESIGN OVERVIEW
The entire design and development of the Power Pc
network is done using XILINX software for signals of data
frames transmission. The design of the network is shown in
below figure. The block diagram for the system is as follows.
The AD977A is controlled by two signals: R/C and
CS. When R/C is brought low, with CS low, for a minimum of
50 ns, the input signal will be held on the internal capacitor
array and a conversion ―n‖ will begin. Once the conversion
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process does begin, the BUSY signal will go low until the
conversion is complete. Internally, the signals R/C and CS are
OR’d together and there is no requirement on which signal is
taken low first when initiating a conversion. The only
requirement is that there be at least 10 ns of delay between the
two signals being taken low. After the conversion is complete
the BUSY signal will return high and the ADC will again
resume tracking the input signal. Under certain conditions the
CS pin can be tied Low and R/C will be used to determine
whether you are initiating a conversion or reading data. On the
first conversion, after the ADC is powered up, the DATA
output will be indeterminate.
Conversion results can be clocked serially out of the AD977A
using either an internal clock, generated by the AD977A, or
by using an external clock. The AD977A is configured for the
internal data clock mode by pulling the EXT/INT pin low. It is
configured for the external clock mode by pulling the
EXT/INT pin high.,
A. Flash:
The S29JL064H is a 64 megabit, 3.0 volt-only flash memory
device, organized as 4,194,304 words of 16 bits each or
8,388,608 bytes of 8 bits each. Word mode data appears on
DQ15–DQ0; byte mode data appears on DQ7–DQ0. The
device is designed to be programmed in-system with the
standard 3.0 volt V supply, and can also be programmed in
standard EPROM programmers. The device is available with
an access time of 55, 60, 70, or 90 ns and is offered in 48-pin
TSOP and 63-ball Fine Pitch BGA packages. Standard control
pins—chip enable (CE#), write enable (WE#), and output
enable (OE#)—control normal read and write operations, and
avoid bus contention issues. The device requires only a single
3.0 volt power supply for both read and writes functions.
Internally generated and regulated voltages are provided for
the program and erase operations.
Simultaneous Read/Write Operations:
The Simultaneous Read/Write architecture
provides simultaneous operation by dividing the memory
space into four banks, two 8 Mb banks with small and large
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sectors, and two 24 Mb banks of large sectors. Sector
addresses are fixed, system software can be used to form
user-defined bank groups. During an Erase/Program
operation, any of the three non-busy banks may be read
from. Note that only two banks can operate simultaneously.
The device can improve overall system performance by
allowing a host system to program or
erase in one bank, then immediately and simultaneously
read from the other bank, with zero latency. This releases
the system from waiting for the completion of program or
erase operations. The S29JL064H can be organized as both
a top and bottom boot sector configuration.
B. Transceiver :
The SN74ALVC16424 (TSSOP1-48) 16-bit (dualoctal) no inverting bus transceiver contains two separate
suppl rails B port has VCCB, which is set at 5 V, and A
port haVCC-A, which is set to operate at 3.3V. This
allows for translation from a 3.3-V to a 5-V environment
and vice versa. The Flash is designed for asynchronous
communication between data buses. To ensure the highimpedance state during power up or power down, the
output-enable (OE) input should be tied to VCC through a
pull-up resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
The Flash is characterized for operation from –40°C to
85°C.
C. Digital To Analog Convertor (DAC):
The DAC8420 is a quad, 12-bit voltage-output DAC with
serial digital interface in a 16-lead package. Utilizing
BiCMOS technology, this monolithic device features
unusually high circuit density and low power consumption.
The simple, easy-to-use serial digital input and fully
buffered analog voltage outputs require no external
components to achieve a specified performance. The 3wire serial digital input is easily interfaced to
microprocessors running at 10 MHz with minimal
additional circuitry.
Each DAC is addressed individually by a 16-bit serial
word consisting of a 12-bit data word and an address
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International Journal of Engineering Trends and Technology (IJETT) – Volume22 Number 7- April 2015
header. The user-programmable reset control CLR forces E. MIL STD Bus:
all four DAC outputs to either zero scale or midscale,
The transmission media, or data bus, is defined as a
asynchronously overriding the current DAC register values.
twisted shielded pairtransmission line consisting of the
The output voltage range, determined by the inputs
main bus and a number of stubs. There is one stub for
VREFHI and VREFLO, is set by the user for positive or
each terminal connected to the bus. The main data bus is
negative unipolar or bipolar signal swings within the
terminated at each end with a resistance equal to the
supplies, allowing considerable design flexibility.
cable's characteristic impedance (plus or minus two
percent). This termination makes the data bus behave
The DAC8420 is available in 16-lead PDIP, SOIC, and
electrically like an infinite transmission line.
Stubs,
CERDIP packages. Operation is specified with supplies
which
are
added
to
the
main
bus
to
connect
the
terminals,
ranging from +5 V only to ±15 V
provide ―local‖ loads and produce impedance mismatch
where added. This mismatch, if not properly controlled,
produces electrical reflections and degrades the
performance of the main bus.
D. OptoCoupler :
An Optocoupler, also known as an Optoisolator or Photo-coupler, is an electronic components
that interconnects two separate electrical circuits by means
of a light sensitive optical interface.
The basic design of an Opt coupler consists of an LED
that produces infra-red light and a semiconductor photosensitive device that is used to detect the emitted infra-red
beam. Both the LED and photo-sensitive device are
enclosed in a light-tight body or package with metal legs
for the electrical connections as shown.
An optocoupler or opto-isolator consists of a light
emitter, the LED and a light sensitive receiver which can
be a single photo-diode, photo-transistor, photo-resistor,
photo-SCR, or a photo-TRIAC and the basic operation of
an optocoupler is very simple to understand.
F. Signal Integrity Check:
Signal integrity or SI is a set of measures of the quality
of an electrical signal. In digital electronics, a stream of
binary values is represented by a voltage (or current)
waveform. However, digital signals are fundamentally
analog in nature, and all signals are subject to effects such
as noise, distortion, and loss. Over short distances and at
low bit rates, a simple conductor can transmit this with
sufficient fidelity. At high bit rates and over longer
distances or through various mediums, various effects can
degrade the electrical signal to the point where errors
occur and the system or device fails. Signal integrity
engineering is the task of analyzing and mitigating these
effects. Signal integrity engineering is an important
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activity at all levels of electronics packaging and assembly,
from internal connections of an integrated circuit (IC),
through the package, the printed circuit board (PCB), the
backplane, and inter-system connections. While there are
some common themes at these various levels, there are
also practical considerations, in particular the interconnect
flight time versus the bit period, that cause substantial
differences in the approach to signal integrity for on-chip
connections versus chip-to-chip connections.
Some of the main issues of concern for signal integrity are
ringing, crosstalk, ground bounce, distortion, signal loss,
and power supply noise.
Signal integrity problems in modern integrated circuits
(ICs) can have many drastic consequences for digital
designs:
Products can fail to operate at all, or worse yet,
become unreliable in the field.
The design may work, but only at speeds slower than
planned
Yield may be lowered, sometimes drastically
The cost of these failures is very high,
and includes photo mask costs, engineering costs
and opportunity cost due to delayed product introduction.
Therefore electronic design automation (EDA) tools have
been developed to analyze, prevent, and correct these
problems.
[
In integrated circuits, or ICs, the main cause of signal
integrity problems is crosstalk. In CMOS technologies,
this is primarily due to coupling capacitance, but in
general it may be caused by mutual inductance, substrate
coupling, non-ideal gate operation, and other sources. The
fixes normally involve changing the sizes of drivers and/or
spacing of wires.In analog circuits, designers are also
concerned with noise that arise from physical sources,
such as thermal noise, flicker noise, and shot noise. These
noise sources on the one hand present a lower limit to the
smallest signal that can be amplified, and on the other,
define an upper limit to the useful amplification.
In digital ICs, noise in a signal of interest arises
primarily from coupling effects from switching of other
signals. Increasing interconnect density has led to each
wire having neighbours that are physically closer together,
leading to increased coupling capacitance between
neighbouring nets. As circuits have continued to shrink in
accordance with Moore's law, several effects have
conspired to make noise problems worse:
To keep resistance tolerable despite decreased width,
modern wire geometries are thicker in proportion to
their spacing. This increases the sidewall capacitance
at the expense of capacitance to ground, hence
increasing the induced noise voltage (expressed as a
fraction of supply voltage).
Technology scaling has led to lower threshold
voltages for MOS transistors, and has also reduced
the difference between threshold and supply voltages,
thereby reducing noise margins.
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Logic speeds, and clock speeds in particular, have
increased significantly, thus leading to faster
transition (rise and fall) times. These faster transition
times are closely linked to higher capacitive crosstalk.
Also, at such high speeds the inductive properties of
the wires come into play, especially mutual
inductance.
These effects have increased the interactions
between signals and decreased the noise immunity of
digital CMOS circuits. This has led to noise being a
significant problem for digital ICs that must be
considered by every digital chip designer prior
to tape-out. There are several concerns that must be
mitigated:
Noise may cause a signal to assume the wrong value.
This is particularly critical when the signal is about
to be latched (or sampled), for a wrong value could
be loaded into a storage element, causing logic
failure.
Noise may delay the settling of the signal to the
correct value. This is often called noise-on-delay.
Noise (e.g. ringing) may cause the input voltage of a
gate to drop below ground level, or to exceed the
supply voltage. This can reduce the lifetime of the
device by stressing components, induce latchup, or
cause multiple cycling of signals that should only
cycle once in a given period.
Finding IC signal integrity problems
Typically, an IC designer would take the
following steps for SI verification:
Perform a layout extraction to get the parasitic
associated with the layout. Usually worst-case
parasitic and best-case parasitic are extracted and
used in the simulations. For ICs, unlike PCBs,
physical measurement of the parasitic is almost never
done, since in-situ measurements with external
equipment are extremely difficult. Furthermore, any
measurement would occur after the chip has been
created, which is too late to fix any problems
observed.
Create a list of expected noise events, including
different types of noise, such as coupling and charge
sharing.
Create a model for each noise event. It is critical that
the model be as accurate as possible.
For each signal event, decide how to excite the
circuit so that the noise event will occur.
Create a SPICE (or another circuit simulator) net
list that represents the desired excitation, to include
as
many
effects
(such
as
parasitic inductance and capacitance, and various
distortion effects) as possible.
Run SPICE simulations. Analyze the simulation
results and decide whether any re-design is required.
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It is common to analyze the results with an eye
pattern and by calculating a timing budget.
Modern signal integrity tools for IC design
perform all these steps automatically, producing
reports that give a design a clean bill of health, or a
list of problems that must be fixed. However, such
tools generally are not applied across an entire IC,
but only selected signals of interest.
G. Waveforms:
The waveforms for Signal integrity checking is
Waveforms of DAC selection
E. SOFTWARE DESIGN
The program for this system is written by using the
VHDL hyperlynx and XILINX software.
III. CONCLUSION AND FUTURE SCOPE
The waveforms for ADC and DAC
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By improving efficiency in the use of
power pc we can more accurately reduce the noises that are
being caused due to the disturbances that are created in the
system more efficiently and we can completely reproduce the
required signal at the end of the signal integrity check process.
Thus the reliability and robustness of the system increases.
The high performance is achieved.
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International Journal of Engineering Trends and Technology (IJETT) – Volume22 Number 7- April 2015
REFERENCES
[1] Allen, Phillip E.; Holberg, Douglas R. CMOS
Analog Circuit Design. ISBN 0-19-511644-5.
[2] Fraden, Jacob (2010). Handbook of Modern
Sensors: Physics, Designs, and Applications.
Springer. ISBN 978-1441964656.
[3] Kester, Walt, The Data Conversion Handbook
, ISBN 0-7506-7841-0
[4] S. Norsworthy, Richard Schreier, Gabor C.
Temes, Delta-Sigma Data Converters. ISBN 0-78031045-4.
[5] "SDRAM Part Catalog". 070928 micron.com
[6] Jennifer Johnson (24 April 2012). "G.SKILL
Announces DDR3 Memory Kit For Ivy Bridge
[7] "Next-Generation DDR4 Memory to Reach
4.266GHz - Report". Xbitlabs.com. August 16, 2010.
Retrieved 2011-01-03.
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