International Journal of Engineering Trends and Technology (IJETT) – Volume22 Number 5- April2015
A New High Precision Dynamic Comparator for
Low Power High Speed ADCs
Poothi Pydi Reddy#1, Dharavat Ravi Naik*2
#1
M.Tech Student, *2Assistant Professor, Department of ECE, Pydah College of Engineering and Technology, India
Abstract—A novel dynamic comparator for low power and
high speed analog-to digital applications has been designed.
It uses a positive feedback mechanism to regenerate the
analog input signal into a full-scale digital level, which is
same as that of conventional comparators but the gain
preceding the regenerative latch stage was improved and the
complementary version of the output-latch stage, which has
bigger output drive current capability at the same area. The
schematics of existing dynamic comparators and proposed
comparator are captured using Tanner Tools schematic
editor and simulated in 90nm PTM Technology using
HSPICE. The topology of the proposed design is able to
minimize the propagation delay and power consumption with
the improved performances than other research works and
the transistor lengths produced the faster output, which is
suitable for the successful operation of the ADC.
Keywords—Dynamic comparator, ADC, PTM, Regenerate,
Latch
I. INTRODUCTION
Over the years, development of digital integrated circuit
has closely followed Moore’s Law. As a result, transistor size
has greatly shrunk and the speed of digital circuit has been
exponentially increased. This trend, which still continues
today, widens the gap between the digital circuit and its
analog counterpart, for which the technology advance is not
as beneficial. On one hand, there exists very high speed
digital circuit with its ever growing processing power and
efficiency. On the other hand, analog circuit struggles and
largely fails to keep pace. This trend puts high pressure on
analog circuit designers to develop very high speed interface
circuits [3], namely, analog to digital and digital to analog
converters (ADCs and DACs)
In high-speed analog-to-digital converters, comparator
design has a crucial influence on the overall performance that
can be achieved. Comparator is widely used in the process of
converting analog signals to digital signals. In the A/D
conversion process, it is necessary to first sample the input.
This sampled signal is then applied to a combination of
comparators to determine the digital equivalent of the analog
signal and it compare the analog signal with another
reference signal and outputs are binary signal based on the
comparison.
ISSN: 2231-5381
High speed comparator architecture comprises of preamplifier [8], latch and buffer stages.The preamplifier stage
amplifies the input signal to improve the comparator
sensitivity and isolate the input of the comparator from
switching noise coming from positive feedback stage. The
latch stage is used to determine which of the input signals is
larger and extremely amplifies their difference. The output
buffer amplifies the information from latch and gives digital
signal as output. The latched comparator is used for the clock
signal and indicates digital output level; whether its
differential input signal is positive or negative. A positive
feedback mechanism to regenerate the analog input signal
into a full scale digital signal is much faster and power
efficient than performing multi-stage linear applications.
The preamplifier latched comparator [] consists of an
amplifier and a latch. The amplifier which is added before the
latch can reduce offset voltage to obtain a high resolution.
This type of latched comparator was also used for high speed
and low power performance. Input-offset voltage is a difficult
problem in comparator design. In precision applications, such
as high-resolution converters, large input-offset voltages [12]
cannot be tolerated. Fully dynamic latched comparator
achieves low power dissipation but also improves kickback
noise and reduces the clock driving requirement compared
with a conventional comparator. So these comparators are
most widely used in high speed ADCs
II. CONVENTIONAL TOPOLOGIES
Lewis-Gray Comparator [2] has low DC power
consumption and adjustable threshold voltage. The
transconductance of transistor M3 and M4 is much larger
than that of the input transistor pair; hence the differential
voltage gain built between Di nodes from the input transistor
pair is not big enough to overcome an offset voltage caused
from such a small mismatch between transistor M3 and M4
pair. As a result, those transistors are the most critical
mismatch pair in this comparator and needed to be sized big
enough to minimize the offset voltage at the cost of the
increased power consumption. Lewis-Gray comparator shows
a high offset voltage and its high offset voltage dependency
on a different common mode voltage Vcom, it is only suitable
for low resolution comparison.
Comparing with Lewis-Gray comparator, Differential
pair comparator [8] shows faster operation and less overall
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International Journal of Engineering Trends and Technology (IJETT) – Volume22 Number 5- April2015
offset voltage. However, still its structure which consists of a
stack of four transistors requires large voltage headroom; it is
problematic in low-voltage deep-submicron CMOS
technologies. Strong dependency on speed and offset with a
different common-mode input voltage Vcom and problem in
low power supply voltage operation due to its structure can
be overcome by using Double-tail latch-type voltage SA [11].
Since this comparator requires both Clk and Clkb signals for
its operation, high accuracy timing between Clk and Clkb is
required otherwise desired output may deviate and it results
in increased power dissipation. The comparator from [3]
without offset calibration technique resolved the problem by
replacing Clkb with Di nodes. As a result, Clk load was
lessened and the input-referred offset was reduced because
the output latch-stage obtains the gain from the both secondinput transistor pairs (M10/M11 and M12/M13). However,
the improved offset has to trade off with the increased delay.
Fig. 1(c) Double-tail latch-type voltage SA (Comparator 3)
Fig. 1(a) Lewis Gray Comparator (Comparator 1)
Fig. 1(d) Two Stage Dynamic Comparator (Comparator 4)
III. OPERATION PRINCIPLES OF PROPOSED
COMPARATOR
Fig. 1(b) Differential Pair Comparator (Comparator 2)
ISSN: 2231-5381
The basic structure of the proposed comparator stems
from the Comparator 3 and Comparator 4. Therefore, the
proposed comparator provides better input offset
characteristic and faster operation in addition to the
advantages of those comparators such as less kickback noise,
reduced clock load and removal of the timing requirement
between Clk and Clkb over a wide common-mode and supply
voltage range.
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International Journal of Engineering Trends and Technology (IJETT) – Volume22 Number 5- April2015
Fig. 2 Proposed Comparator (Comparator 5)
Fig. 3 Simulated waveform of Comparator 1
For its operation, during the pre-charge (or reset) phase
(Clk=0V), both PMOS transistor M4 and M5 are turned on
and they charge Di nodes capacitance to VDD, which turn
both NMOS transistor M16 and M17 of the inverter pair on
and Di’ nodes discharge to ground. Sequentially, PMOS
transistor M10, M11, M14 and M15 are turned on and they
make Out nodes and Sw nodes to be charged to VDD while
both NMOS transistors M12 and M13 are being off. During
the evaluation (decision-making) phase (Clk=VDD), each Di
node capacitance is discharged from VDD to ground in a
different time rate in proportion to the magnitude of each
input voltage. As a result, an input dependent differential
voltage is formed between Di+ and Di- node. Once either Di+
or Di- node voltage drops down below around VDD - |VTP|, the
additional inverter pairs M18/M16 and M19/M17 invert each
Di node signal into the regenerated (amplified) Di’ node
signal.
Then the regenerated and different phased Di’ node
voltages are amplified again and passed to the output-latch
stage by transistor M10−M13. As the regenerated each Di’
node voltage is rising from 0V to VDD with a different time
interval (or a phase difference, which increases with the
increasing input voltage difference Vin), M12 and M13 turn
on one after another and the output-latch stage starts to
regenerate the small voltage difference transmitted from Di’
nodes into a full-scale digital level: Out+ node will output
logic high (VDD) if the voltage difference at Di’ nodes Di’(t)
is negative (Di+’(t) < Di-’(t)) and Out+ will be low (0V)
otherwise. Once either of the Out node voltages drops below
VDD - |VTP|, this positive feedback becomes stronger because
either PMOS transistor M8 or M9 will turn on.
Fig. 4 Simulated waveform of Comparator 2
IV. SIMULATION RESULTS
To compare the performances of the proposed
comparator with the previous works, each circuit was
designed using 90nm technology with
, fCLK=3GHz,
CLOAD=7fF, Temp=250C, and common mode voltage
and simulated with HSPICE.
A. Simulated Waveforms
ISSN: 2231-5381
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Fig. 5 Simulated waveform of Comparator 3
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International Journal of Engineering Trends and Technology (IJETT) – Volume22 Number 5- April2015
Power(mW)
0.25
0.2
0.15
0.1
0.05
0
0.201
0.121
0.135
0.159
0.148
Fig. 8 Power Comparison Graph
Fig. 6 Simulated waveform of Comparator 4
Delay(ps)
100
80
60
40
20
0
94
82
73
88
79
Fig. 9 Delay Comparison Graph
V. CONCLUSION
Fig. 7 Simulated waveform of Comparator 5
B. Performance Comparison
TABLE I
Comparison of Performance Parameters
Comparator
Type
Number of
Transistors
ΣWidth
( )
Delay
(ps)
Comparator1
10
18.4
94
Power
Consumption
(mW)
0.121
Comparator2
Comparator3
Comparator4
11
14
15
18.4
18.4
18.3
82
73
88
0.135
0.201
0.159
Comparator5
19
16.3
79
0.148
In this paper, the comparator circuits for high-speed
ADCs have been investigated. The comparator circuits are
mainly optimized for the low propagation time, low power
consumption and minimal circuit area. The minimal
propagation time delay of 79 ps, offset voltage of 14.6 mV
and power consumption of 0.148 mW is achieved by the
proposed fully dynamic latched comparator. The sizes of all
the transistors of proposed comparator are optimized in such
a way that it shows low power and high speed, which is
suitable for high speed ADCs.
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