International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 2 – March 2015
Detection Mechanism of Intermittent Faults on the Reliability
Of a RISC Microprocessor
S. Bhavyasri 1, D.Roja 2, Ch.Jaya Prakash Narayana 3, Ch.Venkata Krishna 4, V.S.Lakshmi 5
1,2,3,4
5
UG Student, Electronics & Comm. Engineering, Gandhiji Institute of Sci. & Tech., Jaggaiahpet, A.P, India
Assistant Professor, Electronics & Comm. Engineering, Gandhiji Institute of Sci. & Tech., Jaggaiahpet, A.P, India
Abstract: The reduction of transistors size has allowed
the increase of microprocessors speed and the decrease
of their size and supply voltage, but at the cost of
augmenting the incidence of faults. This reduction
causes a higher rate of transient faults, commonly
provoked by temporary environmental conditions such
as electromagnetic interference, or cosmic or internal
radiation. Even, radiation may now affect multiple
locations. Also, changes in the manufacturing processes
have increased the rate of permanent faults. This type of
fault is produced by irreversible physical changes in a
chip. Recently, intermittent faults have emerged as a
new source of trouble in deep submicron integrated
circuits.
. .Keywords— Detection, Fault, Intermittent, Reliability,
RISC, Microprocessor
I. INTRODUCTION
Pipelining is an implementation technique in which
multiple instructions are overlapped in execution.
With the scaling of complementary metal-oxidesemiconductor
(CMOS)
technology
to
the
submicron range, designers have to deal with a
growing number and variety of fault types. In this
way, intermittent faults are gaining importance in
modern very large scale integration (VLSI) circuits.
The presence of these faults is increasing due to the
complexity of manufacturing processes (which
produce
residues
and
parameter
variations),
together with special aging mechanisms. This work
presents a case study of the impact of intermittent
Nowadays Embedded Systems have become a part faults on the behaviour of a reduced instruction set
of human life. The most important part of an
embedded system is the embedded processor. The
computing (RISC) microprocessor.
We
have
carried
out
an
exhaustive
performance of embedded processor determines the
reliability assessment by using verilog-based fault
performance of embedded system. An embedded
injection. In this way, we have been able to modify
processor is a Reduced Instruction Set Computer
different intermittent fault parameters, to select
(RISC) A RISC processor uses load - store various targets, and even, to compare the impact of
architecture, fix length instructions and pipelining.
intermittent faults with those induced by transient
In load - store architecture, load instruction reads
and permanent faults. The objective of this work is
data from memory and writes it to a register, data
twofold: i) to study the impact of intermittent faults
processing instructions process data available in in a reduced instruction set computing (RISC)
registers and write result to a register, and store
microprocessor,
and
ii)
to
compare
the
instruction copies data from register to memory.
consequences of intermittent faults with the effects
caused by permanent and transient
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 2 – March 2015
faults. To carry out the fault injection experiments,
architecture with a four-stage pipeline. The VHDL
we have used VHDL-based Fault Injection due to
model of Plasma is described at RT and logic
its flexibility, as well as high observability and abstraction levels. To exercise the main elements of
controllability of the model components. This paper
the microprocessor (memory, registers, buses,
complements previous works published by the arithmetic and logic unit (ALU) and control unit
authors, where the impact of intermittent faults
(CU)), the bubble sort sorting algorithm has been
on a commercial complex instruction set computing
used. In this way, we have injected intermittent
(CISC) microcontroller was analyzed.
faults into the storage elements (the register bank,
and the random-access memory (RAM)), the buses,
II. FAULT INJECTION MODEL
Fig. 1 shows the classification of the and the combinational logic of the ALU and CU.
different VHDL-based fault injection techniques. Fig. 2 shows the structure of the Plasma core, and
With simulator commands, it is possible to change,
the injection targets.
at simulation time, the value or the timing of the
signals and variables of the system. Saboteurs and
mutants modify the VHDL code of the system by
inserting injection components (saboteurs) or
activating
mutated
components
versions
(mutants).
of
Although
the
existing
these
two
techniques are more complex to apply, and
introduce more spatial and temporal overhead than
simulator commands, they allow injecting more
Figure 2 Block diagram of the Plasma core and injection
targets
III.
complex fault models. Other techniques extend the
syntax and semantics of the VHDL language.
The
DESIGN ASPECTS OF 32-BIT RISC
PROCESSOR
design of 32-bit RISC processor
incorporates various design blocks like Arithmetic
Logic Unit (ALU), Accumulator, Program Counter
(PC), Instruction Register (IR), Memory, Control
Unit (CU), and additional logic.
The design incorporates some the following issues.
Figure 1 VHDL Based Fault Injection Model
The
system
target
is
the
Plasma
microprocessor. It has a 32-bit microprocessor
without
interlocked
ISSN: 2231-5381
pipeline
stages
It handles 32 bit data ,28 bit address
Uses fixed instruction format of length 32
bit.
(MIPS)
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 2 – March 2015
Size of opcode is of 4 bit, handling 15 performs arithmetic and logic instructions directly
instructions.
and control of transfer instructions are performed
Has 256 memory locations
with the help of control and logic decoder.
Start
32-bit registers (IR,ACC)
Implements 2-staged pipelining i.e overlaps
of fetch and execute cycles.
Has
Enter acc,data,opcode
give execlk
Positive edge
of execlk
Opcode=“0111”
Acc1=
Not data
Stop
Opcode=“1000”
Acc1=
Left shift data
Stop
Opcode=“1001”
Acc1=
Right shift Data
Stop
Opcode=“1010”
Acc1=acc
(jump)
Stop
Opcode=“1011”
Acc1=Acc
(skip)
Stop
Opcode=“1100”
Acc1=Acc
(halt)
Stop
Opcode=“1101”
Acc1= data
(ldacc)
Stop
two addressing modes ,Register
Opcode=“0000”
addressing and memory addressing modes
No interrupts and No conditional branches
Data that it handles is unsigned integer type.
Acc1=
Acc+data
Stop
Acc1=
Acc-data
Stop
Acc1=
Data+1
Stop
Acc1=
Data-1
Stop
Acc1=
Acc and data
Stop
Acc1=
Acc or data
Stop
Acc1=
Acc xor data
Stop
Opcode=“0001”
Opcode=“0010”
The next sections of this chapter presents
the schematic diagrams of individual modules,
explanation of their function, flow chart to
Opcode=“0011”
Opcode=“0100”
implement the function, VHDL description of the
Opcode=“0101”
individual modules. In the last section the top order
module
Block
diagram,
functioning,
VHDL
Opcode=“0110”
Stop
description of the top module are given.
Figure 4: FLOW CHART FOR IMPLEMENTATION OF
ALU
Figure 3: 32 Bit ALU
Figure 5: 32 Bit Accumulator
The ALU performs both arithmetic and logical
operations and as well as control of transfer
instructions. It takes data and acc as inputs to
generate output according to the opcode. An execlk
is given as input for synchronization and the output
is available at positive edge of the execlk. It
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The result of an Alu operation is always stored in
accumulator at some specified time based on the
control logic instruction and also the execlk. This
output is again fed to Alu as input. If Reset =0, the
output of accumulator is cleared to zero. When reset
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 2 – March 2015
is high and load accumulator signal is set high, the
output of the ALU is loaded in to the accumulator
at the neg.edge of the execlock.
Figure 8: Flow chart for the implementation of Control
Unit
Let us consider an instance when
some information is stored in the memory. Now
when the system is switched on, CPU is initialized.
Figure 6: FLOW CHART FOR IMPLEMENTATION OF
ACCUMULATOR
In order to fetch an instruction, as a result the
program goes to the location in the memory that is
pointed out by the program counter. After some
instance, the instruction from the memory is put on
the data bus. This cycle is called the instruction
fetch cycle. The instruction is now available at the
data bus. at next instance; the instruction is loaded
into the instruction register. This is called the
instruction load. In this cycle the 4 msb’s of the
instruction are separated and put in the opcode
Figure 7: BUFFER
register and are loaded to control unit as well as
It is used for writing data in to memory. When it is
required to write data in to the memory, then
necessary control signals are generated at the buffer.
Buffer is used for achieving bi-directional operation
of the data bus
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ALU. The rest of the bits are sent out as Irout. The
outputs of the instruction register and the program
counter are connected to a mux. During the
negative edge of the fetch signal, the output of the
instruction register is selected, while the output
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 2 – March 2015
from the program counter is selected during the
sensitive to intermittent faults in combinational
positive edge of fetch cycle.
logic. This result is due to the higher complexity of
Now when the fetch signal goes low the mux the Plasma processor in terms of combinational
selects the output from the instruction register and it
logic
(multiplexers,multiplier-divider,
and
the
points to the location of the operand. Now the
memory controller). Also, more latent errors have
operand present in the location is placed on the data
been detected in the Plasma processor, specially
bus. After an instruction is fetched the program
caused by faults in the storagemodules, mainly
counter is incremented. It points to the next location. because the memory of the Plasma processor is
Now the operand is available at the ALU. The
bigger.
operand is taken in by the ALU and operates on it.
Now the result is available at acc1 at positive edge
of execlk. During the negative edge of execlk, the
result at the Acc1 register is placed on the data bus,
which is sent and loaded into the accumulator for
Figure 9: Simulation Encoder
any further operations. If the data has to be stored
into the memory, then during this clock cycle, Rd
and Wr has to be 0 & 1 respectively. As a result the
accumulator is connected to the memory and the
Figure 10: Fault Detector
value in the accumulator is sent back to a location
in the memory through a module named Buffer.A
characteristic of RISC processor is their ability to
execute one instruction per clock cycle.
Figure 11: Fault corrector
IV.
SIMULATION RESULTS
The present work completes the results presented
where the behavior of an 8051 microcontroller
under the influence of intermittent faults is
analyzed. Comparing these works with the results
presented in this paper, both cores show similar
Figure 12: Correction with Error pattern
general trends, although some differences have
been observed. The Plasma microprocessor is more
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 2 – March 2015
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Author’s Profile
S. BHAVYASRI is a Graduate
student persuing her B.Tech in
ECE specialization in Gandhiji
Institute of Science &
Technology. Her interested
areas are VLSI, Signal
processing.
D.ROJA is a Graduate student
persuing her B.Tech in ECE
specialization in Gandhiji
Institute of Science &
Technology. Her interested
area is VLSI.
CH.JAYA
PRAKASH
NARAYANA is a Graduate
student persuing his B.Tech in
ECE specialization in Gandhiji
Institute of Science &
Technology. His interested
area is Signal processing.
CH.VENKATA KRISHNA is
a Graduate student persuing
his
B.Tech
in
ECE
specialization in Gandhiji
Institute of Science &
Technology. His interested
area is VLSI.
V.SOWJANYA LAKSHMI is
working as Assistant professor
in Gandhiji Institute of
Science & Technology. She
has guided several students in
the field of VLSI.
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