International Journal of Engineering Trends and Technology (IJETT) – Volume 8 Number 9- Feb 2014
Segmented-Channel MOSFET Design and
Optimization – A Review
1
1
Flavia Princess Nesamani I., 1Sujith M.B., 2Lakshmi Prabha V.
Electronics and Communication Department, Karunya University, Coimbatore-641114
2
Principal, Government College of Technology, Coimbatore
Abstract— The steady miniaturization of the conventional
MOSFET resulted in continuous improvement in integratedcircuit cost and functionality. Planar bulk MOSFET designs face
many challenges as they are being scaled down. A segmentedchannel MOSFET (SegFET) device design combines the benefits
of both planar bulk MOSFETs and thin-body transistor
structures. The salient feature of this device is that the channel is
segmented. The base material of the device is a corrugated
substrate consisting of multiple stripes which acts as the
channel. The areas between these stripes are filled with high-k
material (Hafnia/Zirconia). Device isolation materials are used
to isolate the transistor. This device exhibits a higher
performance, lower short channel effects and reduced power
consumption.
Keywords— SegFET, segmented, corrugated substrate, high-k
material, Hafnia/Zirconia
stripes are isolated by very shallow trench isolation
(VSTI) oxide. A shallow trench isolation (STI)
oxide is used to isolate the transistor. The gate
electrode wraps top portion of each stripe to form a
tri-gate structure [13-14] proper control of the
device possible. High dielectric constant (high-k)
gate materials [15-16] act as alternatives to SiO2
which reduces short channel effects. By forming a
MOSFET on corrugated substrate with precisely
spaced stripes, a low power consumption, low
leakage [17] and high performance device can be
developed.
I. INTRODUCTION
II. LITERATURE REVIEW ON DESIGN AND OPTIMIZATION OF
SEGMENTED C HANNEL MOSFET
The constant improvement of CMOS technology
scaling [1] has enabled continuous improvement in
integrated-circuit cost and functionality. As the
MOSFET dimensions are scaled below 30nm
electrostatic integrity and device variability [2], [3]
become harder to control which results in
degrading the performance of the circuit. In order
to overcome these problems, device engineers have
started transitioning from the conventional planar
bulk MOSFET to thin-body transistor structures
such as the FinFET or fully depleted silicon-oninsulator (FDSOI) MOSFET [4]-[7]. Due to the
increased process complexity, requirement of
expensive starting substrate and increased
manufacturing cost a new alternative for SOI
MOSFET [8-9] was developed. The segmentedchannel MOSFET (SegFET) [2-4],[9-12], structure
was proposed as a more evolutionary solution for
continued bulk MOSFET scaling. It offers the
advantages of a thin-body MOSFET along with the
advantages of a conventional planar MOSFET.
SegFETs can be fabricated using conventional
process. The channel region of SegFET consists of
one or more parallel stripes of equal width. The
Recently,
a
segmented-channel
MOSFET
(SegFET) structure was proposed as a more
evolutionary solution for continued bulk MOSFET
scaling that offers the advantages of a thin-body
MOSFET i.e. the reduced variability in
performance and improved scalability together
with the advantages of a conventional planar
MOSFET i.e. the low substrate cost and capability
for dynamic threshold-voltage control.
Byron Ho et al., 2012 [4] fabricated a SegFET
using a conventional process flow starting with
corrugated substrate. They designed the device
with a gate length of 200 nm. They used Si3N4
instead of SiO2 as the VSTI material because SiO2
will be removed during the cleaning process in
fabrication. Many short channel effects were
reduced due enhanced electrostatic integrity. The
main feature of this design is, it does not require
high aspect ratio channel stripes & ultrathin SOI
layer which was essential for FinFET device. The
device simulations indicate that threshold voltage
can be reduced by boron segregation in VSTI.
Tsu-Jae King et al., 2007 [10] got a patent for
designing and fabricating MOSFET on pre-existing
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International Journal of Engineering Trends and Technology (IJETT) – Volume 8 Number 9- Feb 2014
ridges of semiconductor material. They used High
precision technologies like pulse shaped doping,
CVD, etching etc. were used to fabricate the device.
“Wrapped gates” were used to enhance the
performance. The main advantages they inferred
were improved device performance and low power
consumption
Saurabh Chopra et al., 2012 [11] fabricated
SegFET using a conventional process flow starting
with a corrugated substrate. Silicon-Germanium
was used as channel material to enhance p channel
MOSFET performance. Due to the fringing electric
fields through the VSTI regions, it provides
improved gate control of the channel, so that the
SegFET exhibits improved short channel behaviour
compared to the conventional MOSFET. SegFETs
achieve higher current per unit layout width for the
same gate overdrive, despite having smaller
effective channel width. This was due to higher
effective mobility resulting from reduced biaxial
strain.
Xin Sun, 2010 [3] describes about the fabrication
of segmented-channel MOSFET (SegFET) on
corrugated substrate. The channel region of a trigate bulk MOSFET consists of one or more parallel
segments stripes of equal width (WSTRIPE). The
stripes are isolated by very shallow trench isolation
(VSTI) oxide. The VSTI oxide extends to a depth
below the source/drain extension regions, but it can
be much shallower than the STI oxide. Spacer
lithography was used to form the corrugated
substrate. Selective epitaxial growth was used to
form the semiconductor stripes of corrugated
substrate. LTO spacers are produced by CVD and
anisotropic etch back process.
Nuo Xua et al., 2011 [12] describes about the
fabrication of Segmented-Channel MOSFETs for
Reduced Short-Channel Effects. To form the
corrugated-silicon substrate, 193nm immersion
lithography was used to print resist lines and spaces
with 120 nm pitch. Using reactive ion etching (RIE)
Si in the spaces was recessed by 35 nm. The
substrate surface was flattened by depositing a 300nm-thick layer of Si3N4 and this layer was
subsequently etched back using RIE to form VSTI
regions. Due to enhanced gate control, SegFETs
show reduced short-channel effects and can
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achieve comparable drive current per unit layout
area as conventional MOSFETs.
Kaushik Roy et al., 2003 [17] describes about the
leakage mechanisms and leakage reduction
techniques in in deep-sub micrometer CMOS
circuits. Increased leakage current in deep-sub
micrometer regime is the major reason of power
dissipation of CMOS circuits as channel length
oxide thickness and threshold voltage gate are
reduced. This paper mentions about various
transistor intrinsic leakage mechanisms which
includes drain-induced barrier lowering, weak
inversion gate oxide tunneling and gate-induced
drain leakage. Different methods for reducing
short-channel effects such as channel engineering
techniques including retrograde well and halo
doping were used as in CMOS devices. At the
circuit level, transistor stacking, multiple threshold
voltage, dynamic threshold voltage, multiple drain
voltage, and dynamic drain voltage techniques can
effectively reduce the leakage current in highperformance logic and memory designs.
Hyohyun Nam et al., 2012 [2] describes about
the fabrication of SegFET on corrugated substrate
and analyses about the performance, power and
process induced variation of the device. In this
paper they described about using high–k material
(HfO2) in between the channel stripes of the
corrugated substrate as well as in shallow trench
isolation region in order to improve the
performance of the device. This device has an
improved electrostatic integrity when compared
with the bulk MOSFET and also does not require
SOI substrate which reduces the cost of fabrication
when compared with SOI based FinFET.
Prathima A. et al. [5] describes about the impact
of device parameters of triple gate SOI- FinFET. In
order to reduce the off state leakage current (IOFF)
the fin thickness has to be reduced and reducing the
fin height resulted in reducing the gate leakage
current (IGATE). It was found that static power
dissipation of the inverter increases as the fin
height increases due to the increase in leakage
current, whereas delay reduced with increase fin
width due to higher drive current. The performance
of the inverter reduced with the downscaling of the
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International Journal of Engineering Trends and Technology (IJETT) – Volume 8 Number 9- Feb 2014
gate oxide thickness due to higher gate leakage
current and gate capacitance.
Yasuhisa Omura et al., 2008 [13] puts forward an
advanced consideration on the design of scaled
multiple-gate FET (MuGFET). When considering
about the drivability and short-channel effects
triple-gate (TG) FET is superior to the
conventional FinFET. In order to increase the on
current and to suppress the short channel effects a
high-fin device has to be used.
Ali A. Orouji et al., 2005 [7] proposed a novel
configuration for the symmetrical double gate SOI
MOSFET using two side gates. It was used to
investigate the influence of extremely shallow
source and drain junctions on the short-channel
effects. A constant voltage, other than the main
gate voltage was applied to the side gates to form
inversion layers that acts as virtual source and drain.
Based on the simulation results they proved that the
proposed symmetrical double gate SOI MOSFET
with asymmetrical side gates for the induced
source/drain is far superior in terms of controlling
the short-channel effects when compared to the
conventional symmetrical double gate SOI
MOSFET.
Anurag Chaudhry et al. [6] examines the
performance degradation of a MOS device
fabricated on silicon-on-insulator (SOI) caused due
to the undesirable short-channel effects as the
channel length is scaled to meet the increasing
demand for high-speed high-performing ULSI
applications. Inorder to improve the device
performance and to supress the SCE such as drain
induced barrier lowering, hot carrier effects etc. a
new device called the dual material gate was
discussed. This structure uses “gate-material
engineering” instead of “doping engineering”
which resulted in improved performance of the
device.
Pushkar Ranade et al., 2001 [14] proposed
Molybdenum (Mo) as an important material for use
as a MOSFET gate electrode and the implantation
of nitrogen ions into the Mo film has resulted in
reduction of interfacial work function of Mo. It was
observed that Mo was thermally stable on a wide
range of dielectrics (SiO2, Si3N4, HfO2) and thus
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appears to be a promising gate electrode for future
CMOS generations.
Tsu‐Jae King Liu, 2012 [10] describes about
the existing MOSFET structures and also discusses
about the development and reasons behind the
evolution of the new semiconductor device called
as SegFET. According to the concept SegFET is a
proven transistor design which is based on
segmenting only the channel region of a standard
planar MOSFET. The device uses same retrograde
channel doping as a planar MOSFET to suppress
the short channel effect. It uses the conventional
fabrication process and is compactable with all
technologies developed by bulk CMOS.
S.L.Tripathi et al., 2012 [15] discusses about
multi-gate MOSFET structures with high-k
dielectric materials. The use of high k dielectric
materials such as HfO2, Si3N4 improves the
strength of the fringing electric field which resulted
in an improvement in the on state current while the
off state current sub threshold slope and drain
induced barrier lowering of the FinFET was
decreased, thus resulted in improvement of the
device. The increase in the Ion/Ioff ratio of the
device resulted in a decrease in power operation.
Jean-Pierre Colinge, 2004 [8] describes about
Multiple-gate SOI MOSFETs. These devices offer
a large current drive per unit silicon area than
conventional MOSFETs. These devices will also
offer a lower short-channel effect. A new class of
MOSFET, called triple-plus gate device has been
introduced, which offer a practical solution to the
problem of the manufacturing surrounding-gate
silicon MOSFET. The structure was similar to
triple gate transistor structures with field induced,
pseudo-fourth gate that emulates the fourth gate
underneath the device.
III. CONCLUSIONS
The methods of designing and optimizing the
Segmented channel MOSFET are studied.
Different methods for fabrication of the device are
analysed. This device combines the advantages of
both thin-body MOSFET and conventional
MOSFET. As the MOSFET was designed on preexisting stripes, the device consumes less power
and the performance is improved.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 8 Number 9- Feb 2014
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