International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 4- Dec 2013
Speed and Area optimized Design of DDR3 SDRAM
(Double Data Rate3 Synchronously Dynamic RAM)
Controller for Digital TV Decoders
*M.Rajendra1
N.Suresh Babu
2
PG Student (M. Tech), Dept. of ECE, Chirala Engineering College, Chirala., A.P, India.
Professor, Vice Principal & HOD-ECE, Chirala Engineering College, Chirala., A.P, India.
1
2
Abstract: Today to store large amount of data generally so many memory devices are available
in the market. But to access the storage data a need of retrieval devices should be needed. In
this paper to accommodate that type of task a DDR3SDRAM IS PROPOSED. The proposed
memory design is modeled using finite state machine which should be used in the internal
block of setup box application. To maintain the functionality different FIFO’s and counter
design are included in the proposed architecture. For each block HDL code is developed based
on VERILOG language. In this paper the Xilinx ISE EDA Tool is used for synthesis and
Modelsim is used for simulation.
Keywords- Digital TV; DDR SDRAM; Verilog; FSM.
Then
1. Introduction
In order to store any information
the
double-data-rate
DDR1
SDRAM
or
with
synchronous
must and should there is a need to
dynamic random access memories came
interact with memory devices. In the
into technology proven place. Now the
olden days for the storage purpose they
DDR3 SDRAM or double-data-rate three
are used RAM and ROM’s. But after day
synchronous
to
memories is surviving to satisfy the data
day
based
improvements
on
the
the
need
technological
of
memory
rate
dynamic
transferring
random access
according
to
the
utilization and interaction make force to
interfaces supportability. The working
develop new storage devices. So then a
principle
new era is opened for these memory
memories
is
storage devices. After RAM and ROM’s, a
compare
with
static and dynamic RAM’s (SRAM and
When we compare this memory with the
DRAM) are come into the market. But
previous one’s there is a lot of achieved
here the problem of data transferring rate
characteristics in terms of interfacing.
is coming into the picture.
Mainly the data rate is improving 4 times
of
these
newly
totally
the
designed
different
existed
when
memories.
in the second generation and 8 times in
the third generation.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 4- Dec 2013
2 each and every generation sections is
shown
clearly.
According
to
the
interfacing needs along with maintaining
of
data
rate
taking
care
of
power
estimation is also plays a vital role of
memory sales.
Figure 3 CHIP LEVEL VIEW OF DDR RAM
The figure 3 shows the chip level
Figure 1 different generation of DRAM’s
view of the DDR RAM. This chip level
and their data rates.
design is directly interface with the
The data rate of each and every
peripherals device based on the size
memory should have to be improving in
matching’s.
order to interact with the high bandwidth
specifications should take care while
devices. Otherwise there is a chance of
providing the interfacing with the other
mismatching
devices.
the
synchronism.
These
Voltage
and
current
rates has to be improve according to the
rate of frequency matching’s.
Figure 1 Comparison of Estimated Power in
DDR RAMS
Figure 4 memory organization
The
The power estimation of different
generations is taken into account to enter
into the low power area while designing
the next generation devices. In the figure
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memory
devices
are
interacting with the other peripherals
through only the memory controller. The
arbiter provides the information about
which device the memory has to be
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 4- Dec 2013
interact
according
the
schemes
the
SDRAM input receiver. DQS is center-
arbiter preferred. Whenever the request
aligned with data for WRITEs. The read
is coming from the controller immediately
data is transmitted by the DDR3 SDRAM
the memory reacts according to the
and edge-aligned to the data strobes.
command that the controller generates
and
interact
block.
All
with
the
the
P
corresponding
memory
architectures
generally use pumping mechanism to
maintain the frequency issues. Here the
devices are neither forward nor backward
compatibility. So the structure is used
according
to
the
requirements
of
interfacings. The name double data rate
means the frequency of clock is two times
than the single data rate ram with the
same clock frequency due to its double
pumping.
Figure 2 DDR3 SD RAM Architecture
In the above architecture the DDR
2. DDR3 SDRAM CONTROLLER
SDRAM
ARCHITECTURE
The DDR3 SDRAM uses double data
rate architecture to achieve high-speed
operation.
The
double
data
rate
architecture is 8n-prefetch architecture
with an interface designed to transfer two
data words per clock cycle at the I/O
pins. A single read or write access for the
DDR3 SDRAM consists of a single 8n-bitwide, one-clock-cycle data transfer at the
internal
DRAM
core
and
eight
corresponding n-bit-wide, one-half-clock
cycle data transfers at the I/O pins. The
differential data strobe (DQS, DQS#) is
transmitted externally, along with data,
for use in data capture at the DDR3
plays
a
vital
role
for
communication which is the designing
module .The DDR3 SDRAM operates
from a differential clock (CK and CK#).
The crossing of CK going HIGH and CK#
going LOW is referred to as the positive
edge of CK. Control, command, and
address signals are registered at every
positive
edge
of
CK.
Input
data
is
registered on the first rising edge of DQS
after the WRITE preamble, and output
data is referenced on the first rising edge
of DQS after the READ preamble. Read
and write accesses to the DDR3 SDRAM
are burst-oriented. Accesses start at a
selected location and continue for a
programmed number of locations in a
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 4- Dec 2013
programmed sequence. Accesses begin
with the registration of an ACTIVATE
command, which is then followed by a
READ or WRITE command. The address
bits
registered
coincident
with
the
ACTIVATE command are used to select
the bank and row to be accessed. The
address bits registered coincident with
Figure 3 Functional Block Diagram
the READ or WRITE commands are used
to select the bank and the starting
column location for the burst access.
DDR3 SDRAM use READ and WRITE
BL8
and
BC4.
An
auto
precharge
function may be enabled to provide a
self-timed row precharge that is initiated
As with standard DDR SDRAM, the
multibank
architecture
of
DDR3 SDRAM allows for concurrent
operation,
thereby
providing
high
bandwidth by hiding row precharge and
activation time. A self refresh mode is
provided, along with a power-saving,
The functional block diagram of the
DDR3 controller is shown in Figure 6.
of
DDR3SDRAM
controller consists of Initialization FSM
Command FSM, data path , bank control
,clock counter, refresh counter, Address
FIFO, command FIFO ,Wdata FIFO and
R_data reg .
Command FSM generates c-
State to perform the normal write, read
and fast write, read operations.
The data path module performs the
between
Hash
CAM
unit
and
DDR3SDRAM banks. The Address FIFO
gives the address to the Command FSM
so the bank control unit can open
particular bank and address location in
that bank. The Wdata FIFO provides the
data to the data path module in normal
gets the data from the data path module
Functional Block Diagram
architecture
design.
and fast write operation. The R_data reg
power-down mode.
The
State to initialize the modules in the
data latching and dispatching of the data
at the end of the burst access.
pipelined,
Initialization FSM generates proper i-
normal and fast read operation.
In this paper the designed DDR3
controller provides interface to the HASH
CAM
circuit
and
the
DDR
Memory
Banks. If the data word is found, the
CAM returns a list of one or more storage
addresses where the word was found
(and in some architecture, it also returns
the data word, or other associated pieces
of data). Because a CAM is designed to
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 4- Dec 2013
search its entire memory in a single
if
control
is
“11”
DDR3
controller
operation, it is much faster than RAM in
performs the Fast read operation.
Read data register
virtually all search applications.
The DDR3 controller gets the address,
When
DDR3
controller
performs
data and control from the HASH CAM
Normal read or Fast read operation Read
circuit in to the Address FIFO. Write data
data register gets the data send to the
FIFO and control FIFO respectively.
Hash Cam circuit.
Address FIFO
In this design, the ACTIVE command
DDR3 SDRAM controller gets the
will be issued for each read or write
address from the Address FIFO so that
access to open the row. After a tRCD
controller can perform the read from the
delay is satisfied, READA or WRITEA
memory or write in to the memory
commands will be issued with a high
address location specified by the Address
ddr_add[10]
FIFO. Here the Address FIFO width is 13
REFRESH
bit and stack depth is 8.
access. Therefore, the clocks required for
Write data FIFO
read/write cycle are fixed and the access
DDR3 SDRAM controller gets the data
can be random over the full address
from
the
Write
closing
the
the
AUTO
row
after
range. Read or write is determined by the
operation in to the memory address
sys_r_wn status sampled at the rising
location specified by the Address FIFO.
edge of the clock before the tRCD delay is
Here the Address FIFO width is 64 bit
satisfied. If logic high is sampled, the
and stack depth is 8.
state machine switches to c_READA. If a
Control FIFO
logic low is sampled, the state machine
DDR3 SDRAM controller gets the
switches to c_WRITEA[8].
FIFO
For read cycles, the state machine
controller can perform the read from the
switches from, c_READA to c_cl for CAS
memory or write in to the memory
latency,
address location specified by the Address
transferring data from DDR to processor.
FIFO. Here the Control FIFO width is 2
The burst length determines the number
bit and stack depth is 8. If the control
of clocks the state machine stays in
FIFO gives the “01” DDR3 controller
c_rdata
performs the Normal read operation. If
transferred, it switches back to c_idle [8].
the
control
from
is
the
FIFO
for
enable
in write
command
data
to
Control
“10” DDR3
then
state.
switches
After
to
the
crate
data
for
is
controller
For write cycles, the state machine
performs the Normal read operation and
switches from c_WRITEA to c_wdata for
transferring data from bus master to
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DDR, then switches to c_tDAL. Similar to
SDRAM is that it synchronizes the data
read, the number of clocks the state
transfer, and the data transfer is twice as
machine
is
fast as previous, the production cost is
determined by the burst length. The time
also very low. When compare with the
delay tDAL is the sum of WRITE recovery
existing
time tWR and the AUTO PRECHARGE
consumes less area and high speed due
timing delay tRP. After the clock rising
to efficient
edge of the last data in the burst
machine.
stays
in
c_wdata
state
one
the
proposed
design
design of the finite state
sequence, no commands other than NOP
can be issued to DDR before tDAL is
satisfied.
The dashed lines indicate possible
state switching paths when the tCK
period is larger than the timing delay
specification [8].
Figure 7 Simulation Result Read Operation
Data Path Control
Data path module performs the data
latching and dispatching based on the
command
FSM
states.
It
provides
interface between the Read data register
and the memory banks.
Bank control
The bank control controls the all the
eight banks effectively depending upon
the istate and cstate by sending the
Figure 8 Simulation Result write Operation
We have successfully designed using
Verilog
required control signals.
HDL
and
simulated
using
3. Results & Discussions
Modelsim and synthesized using Xilinx
In this paper we have designed a High
tool. Fig 7 & 8 show the Simulation
speed DDR3 SDRAM Controller with 64-
result for Read & Write Operations. Fig 9
bit data transfer which synchronizes the
& 10 the RTL and Technology Schematics
transfer of data between DDR RAM and
of the Designed SDRAM.
External peripheral devices like host
computer,
laptops
and
so
on.
The
advantages of this controller compared to
SDR SDRAM, DDR1 SDRAM and DDR2
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[3].H. Kim, et al, “High-Performance and
Low-Power
Memory-
Architecture
for
Application”,
IEEE
Circuit
and
Interface
Video
Processing
Transactions
Systems
for
on
Video
Technology, Vol. 11, Nov. 2001, pp.
1160-1170.
[4]. E. G. T. Jaspers, et al, “Bandwidth
Reduction
for
Video
Processing
in
Consumer Systems”, IEEE Transactions
Figure 9 RTL Schematic
on Consumer Electronics, Vol. 47, No. 4,
Nov. 2001, pp. 885- 894.
[5] Charless H. Roth, Jr (2005) ‘Digital
Systems Design Using VHDL’, 3rd edition,
Thomson Asia private limited, Singapore.
[6] Virtex-5 FPGA XAUI User Guide.
edition,
Tata
McGraw-Hill
publishing
company limited. Singapore.
[7] A. J. McAuley, et al, “Fast Routing
Figure 10 Technology Schematic
Table Lookup Using CAMs”, Proceedings
Acknowledgements
on 12th Annual Joint Conference of the
The authors would like to thank
the
anonymous
reviewers
for
their
comments which were very helpful in
improving the quality and presentation of
this paper.
IEEE Computer and Communications
Societies (INFOCOM), Vol.3, March 1993,
pp.1382 – 1391.
[8] “DDR SDRAM Controller”-April 2004
Reference
Design
RD1020
Lattice
Semiconductor Corp.
References:
[1].X. Yang, et al, “High Performance IP
Lookup Circuit Using DDR SDRAM”,
IEEE
International
SOC
Conference
Authors Profile:
M.RAJENDRA is Pursuing his
M.
Tech
from
Chirala
(SOCC), Sept. 2008, pp. 371-374.
Engineering College, Chirala in
[2].G. Allan, “The Love/Hate Relationship
the department of Electronics
with DDR SDRAM Controllers”, MOSAID
Technologies Whitepaper, 2006.
ISSN: 2231-5381
& Communications Engineering (ECE) with
specialization in VLSI & Embedded systems.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 4- Dec 2013
Prof. N.Suresh Babu is vicePrincipal & HOD of ECE Dept.
in CEC Chirala. He got his
M.Tech
Engineering
from
in
Birla
Microwave
Institute
of
Technology, Ranchi. He has 14 years of
Teaching Experience and 2 years of Industrial
Experience in various organizations
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