Circuit Note
CN-0152
Devices Connected/Referenced
Circuits from the Lab™ tested circuit designs address
common design challenges and are engineered for
quick and easy system integration. For more information
and/or support, visit www.analog.com/CN0152.
AD9552
Oscillator Frequency Upconverter
ADCLK854
LVDS/CMOS Clock Fanout Buffer
Clock Distribution Circuit with Pin-Programmable Output Frequency,
Output Logic Levels, and Fanout
EVALUATION AND DESIGN SUPPORT
Circuit Evaluation Boards
AD9552 Evaluation Board (AD9552-PCBZ)
ADCLK854 Evaluation Board (ADCLK854-PCBZ)
Design and Integration Files
Schematics, Layout Files, Bill of Materials
Software
ADCLK854
VREF
CIRCUIT FUNCTION AND BENEFITS
VS/2
LVDS/
CMOS
CLK0
OUT1 (OUT1A)
CLK0
OUT1 (OUT1B)
CLK1
The AD9552 oscillator frequency upconverter and ADCLK854
LVDS/CMOS clock fanout buffer together create a flexible clock
distribution solution that is pin-programmable. The AD9552
is equipped with an SPI port to program the device. This
interface enables a wide output frequency range up to 900 MHz.
However, it is also pin-programmable which simplifies use in
many designs that do not require software programmability.
In the pin-programmable mode, there are up to 64 standard
output frequencies available, based on the input frequency
selection. The AD9552, therefore, functions like a frequency
pin-programmable VCXO. The AD9552 is also equipped to
operate from a crystal resonator at the input for additional
flexibility. A simplified block diagram of the AD9552 is
shown in Figure 1, and a simplified block diagram of the
ADCLK854 is shown in Figure 2.
OUT0 (OUT0A)
OUT0 (OUT0B)
OUT2 (OUT2A)
CLK1
OUT2 (OUT2B)
IN_SEL
OUT3 (OUT3A)
CTRL_A
OUT3 (OUT3B)
LVDS/
CMOS
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
CTRL_B
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
LVDS/
CMOS
OUT8 (OUT8A)
OUT8 (OUT8B)
OUT9 (OUT9A)
AD9552
REF
XTAL
INPUT
FREQUENCY
SOURCE
SELECTOR
PLL
CTRL_C
OUTPUT
CIRCUITRY
OUT9 (OUT9B)
OUT2
OUT10 (OUT10A)
OUT1
OUT10 (OUT10B)
SLEEP
08978-001
PIN-DEFINED AND SERIAL PROGRAMMING
08978-002
OUT11 (OUT11A)
OUT11 (OUT11B)
Figure 2. Simplified Block Diagram of ADCLK854 Clock Fanout Buffer
Figure 1. Simplified Block Diagram of AD9552 Oscillator Frequency Upconverter
Rev. A
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CN-0152
Circuit Note
The ADCLK854 is a clock fanout buffer and is pinprogrammable for both LVDS and 1.8 V CMOS outputs.
The ADCLK854 has up to 12 LVDS outputs, 24 CMOS
outputs, or combinations of both. The ADCLK854 could be
replaced with several other clock fan out clock buffers available
from Analog Devices with fewer outputs and/or different
output logic choices.
5.
Connect an oscilloscope, spectrum analyzer, or other
lab equipment to any of the J3 to J6 SMA connectors
on the upper right side of the board.
6.
Power the evaluation board by plugging it into the
USB port.
7.
A frequency of 625 MHz should be observed on the
OUT1 SMA connector.
CIRCUIT DESCRIPTION
8.
If another output frequency is desired, remove the
USB port. Then change the dip switch settings and
reapply the USB port connection.
The simplified circuit in Figure 3 displays the setup between
the AD9552 and the ADCLK854 customer evaluation boards.
The AD9552 is setup to run off a 26 MHz crystal resonator. The
AD9552 LVPECL output then drives the ADCLK854 evaluation
board for LVDS and/or CMOS fanout capability. The LVPECL
output is selected for its low jitter and phase noise.
Using the AD9552 and ADCLK854 together is a natural fit for
low jitter clock distribution. The pin-programmability feature of
both parts enables a stand-alone clock generator solution that
avoids interface control lines back to an FPGA or microcontroller. In addition, both of these parts make for a small
footprint. The simplified circuit bock diagram is shown in
Figure 3. Details of the internal connections and bill of
materials can be found in the individual AD9552 Evaluation
Board and the ADCLK854 Evaluation Board documentation.
After each dip switch setting, the AD9552 must be powered
down by removing the USB cable to reprogram the AD9552.
See the AD9552 data sheet for a detailed explanation of pin
programming.
The ADCLK854 outputs are pin-programmable up to 12
differential LVDS outputs or 24 single-ended 1.8 V CMOS
outputs. Jumpers CTRL_A, CTRL_B, CTRL_C, and SLEEP
are used to configure the outputs. See Table 1 to configure the
outputs to the desired setting.
Table 1. ADCLK854 Configuration
Logic 0 = LVDS;
Logic 1 = CMOS
Logic 0 = LVDS;
Logic 1 = CMOS
Logic 0 = LVDS;
Logic 1 = CMOS
Logic 0 = LVDS;
Logic 1 = CMOS
CTRL_A
CTRL_B
AD9552
ADCLK854
EVALUATION BOARD
EVALUATION BOARD
CTRL_C
REF CLK
OUT1
CLKD
CMOS
CLKD
LVDS
LVPECL
OUT1
SLEEP
Output 0 to Output 3
Output 4 to Output 7
Output 8 to Output 11
Output 0 to Output 11
SLEEP
The following absolute phase noise and spectrum plot of Figure 4
and Figure 5 are from the LVDS output of the ADCLK854 clock
fanout buffer.
08978-003
–20
Figure 3. Simplified Diagram of AD9552 and ADCLK854 Circuit Combination
1.
Ensure that Jumper JMP3 is positioned for manual
control.
2.
Verify that all five jumpers are removed on
Connector P2.
3.
Set the positions of the S3 dip switches to 0111 to
indicate a 26 MHz crystal is being used.
4.
Set the positions of the S2 dip switches to 0010 and
the positions of the S1 dip switches to 0011.
PHASE NOISE (dBc/Hz)
The following procedure explains how the AD9552 evaluation
board can be manually programmed by using on-board
jumpers and dip switches to set the logic levels for the input
and output frequency selection. In this example, the crystal
frequency is 26 MHz, and the output frequency is 625 MHz.
INTEGRATED NOISE: −53.6dBc/19.7MHz
RMS NOISE: 169.1millidegree
RMS JITTER: 752fs
RESIDUAL FM: 4.43kHZ
–40
–60
–80
–100
–120
–140
–160
–180
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
08978-004
CTRL_C
Y3 Y2 Y1 Y0
CTRL_B
YS Y4
CTRL_A
RESET
A2 A1 A0
OP SEL
REF CLK
Figure 4. ADCLK854 LVDS Output Phase Noise at 625 MHz (Spurious = Off)
Rev. A | Page 2 of 4
Circuit Note
REF LVL
–5dBm
CN-0152
MARKER 1 (T1)
–7.34dBm
624.89979960MHz
RBW 10kHz
YBW 30kHz
SWT 2.5sec
appropriate ac swing to both inputs. For this circuit note, the
CLK0 and CLK0B inputs are used for the lowest jitter.
RF ATT 10dB
UNIT
dB
0
–30
CLK1 is set up to evaluate the ADCLK854 with a single-ended
source via the balun on the evaluation board. This input is not
used in this Circuit Note.
–40
Functional Block Diagram
–10
–20
A functional diagram of the basic setup is shown in Figure 3 of
this circuit note, with the exception of the external power
supplies and the spectrum analyzer. UG-070 shows the
configuration for the ADCLK854 evaluation board.
–50
–60
–70
–80
Setup and Test
–100
START 575
625
STOP 675
MHz
08978-005
–90
Figure 5. ADCLK854 Output Spectrum Using the ADCLK854
Evaluation Board (LVDS outputs)
After connecting the boards and applying power as described
above, this circuit note describes how to manually program
the AD9552 using the jumpers and dip switches. The output
signal from the ADCLK854 can then be examined using an
oscilloscope or a spectrum analyzer.
A complete design support package for this circuit note can be
found at http://www.analog.com/CN0152-DesignSupport.
LEARN MORE
COMMON VARIATIONS
CN0152 Design Support Package:
http://www.analog.com/CN0152-DesignSupport
Analog Devices offers a variety of clock distribution chips and
clock buffers. Refer to www.analog.com/clock for more
information.
AN-1051 Application Note, Reference Design for the AD9553
Oscillator Frequency Up Converter, Analog Devices.
CIRCUIT EVALUATION AND TEST
This circuit note describes how to operate the AD9552 as a pinprogrammable device requiring no software support.
Equipment Needed
A 1.8 V @ 400 mA supply for the ADCLK854 evaluation board
and a 3.3V @ 300 mA supply for AD9552 evaluation board are
required. If the software programmable features of the AD9552
are to be used, a PC should be connected to the AD9552
evaluation board using a USB cable, and the USB 5 V can be
used to supply power to the AD9552 board. For this circuit
note, USB power is used, although the software programmable
features of the AD9552 are not exercised.
In addition, a high quality spectrum analyzer is required to
measure the phase noise and spectral output results described
in this circuit note.
Getting Started
Connect the power supplies to the evaluation boards. Then
connect the differential LVPECL outputs of the AD9552 board,
J3 and J4, to the CLK0 and CLK0B inputs of the ADCLK854
board. The recommended setup for the ADCLK854 evaluation
board is shown in Figure 2 of UG-070. The supply voltage is
set to 1.8 V. The IN_SEL jumper provides the desired input
configuration. Logic 0 on the IN_SEL pin selects the CLK0 and
CLK0B inputs, and Logic 1 on the IN_SEL pin selects the CLK1
and CLK1B inputs. On the ADCLK854 evaluation board, the
CLK0 and CLK0B inputs are set up for ac-coupled, differential
inputs. This input configuration requires the user to provide the
AN-0988 Application Note, The AD9552: A Programmable
Crystal Oscillator for Network Clocking Applications,
Analog Devices.
Kester, Walt. 2005. The Data Conversion Handbook.
Chapters 6 and 7. Analog Devices.
Kester, Walt. 2006. High Speed System Applications. Chapter 2,
“Optimizing Data Converter Interfaces.” Analog Devices.
Kester, Walt. 2006. High Speed System Applications. Chapter 3,
“DACs, DDSs, PLLs, and Clock Distribution.” Analog Devices.
MT-007 Tutorial, Aperture Time, Aperture Jitter, Aperture Delay
Time—Removing the Confusion, Analog Devices.
MT-008 Tutorial, Converting Oscillator Phase Noise to Time
Jitter. Analog Devices.
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of AGND and DGND. Analog Devices.
MT-085 Tutorial, Fundamentals of Direct Digital Synthesis
(DDS). Analog Devices.
MT-086 Tutorial, Fundamentals of Phase Locked Loops (PLL).
Analog Devices.
MT-101 Tutorial, Decoupling Techniques. Analog Devices.
Data Sheets and Evaluation Boards
AD9552 Data Sheet
AD9552 Evaluation Board
ADCLK854 Data Sheet
ADCLK854 Evaluation Board
Rev. A | Page 3 of 4
CN-0152
Circuit Note
REVISION HISTORY
11/10—Rev. 0 to Rev. A
Added Evaluation and Design Support Section ........................... 1
Changes to Circuit Description Section ........................................ 2
Added Circuit Evaluation and Test Section .................................. 3
4/10—Revision 0: Initial Version
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CN08978-0-11/10(A)
Rev. A | Page 4 of 4