Computer Architecture …………………………………
Lecture No.4
5-Instruction Set Architecture and Design
There
are
basic principles involved in instruction set architecture and
design. Therefore, this section includes many important issues will discuss.
5-1 Memory locations and Operations.
The main memory can be modeled as an array of millions of adjacent cells,
each capable of storing a binary digit (bit), having value of 1 or 0. These cells are
organized in the form of groups of fixed number, say n, of cells that can be dealt
with as an atomic entity. An entity consisting of 8 bits is called a byte. In many
systems, the entity consisting of n bits that can be stored and retrieved in and out
of the memory using one basic memory operation is called a word (the smallest
addressable entity). Typical size of a word ranges from 16 to 64 bits. It is, however,
customary to express the size of the memory in terms of bytes. For example, the
size of a typical memory of a personal computer is 256 Mbytes, that is,
256 * 220 = 228 bytes. ( where 265 = 28 and Mbytes = 220 )
In order to be able to move a word in and out of the memory, a distinct
address has to be assigned to each word. This address will be used to determine the
location in the memory in which a given word is to be stored. This is called a
memory write operation. Similarly, the address will be used to determine the
memory location from which a word is to be retrieved from the memory. This is
called a memory read operation (as mentioned in lecture 2).
The number of bits, l , needed to distinctly address M words in a memory is
given by l = log2 M . For example, if the size of the memory is 64 M (read as 64
mega
words),
then
the
number
of
bits
in
the
address
is
log2 (64 * 220) = log2 (226) = 26 bits. Alternatively, if the number of bits in the
address is l , then the maximum memory size (in terms of the number of words that
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Computer Architecture …………………………………
Lecture No.4
l
can be addressed using these l bits) is M = 2 . Figure (4.1) illustrates the concept
of memory words and word address as explained above.
Figure (4.1) Illustration of the main memory addressing
5.2 Instruction formats.
Any instruction issued by the processor must carry at least two types of
information. These are the operation to be performed, encoded in what is called the
op-code field, and the address information of the operand on which the operation is
to be performed, encoded in what is called the address field.
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Computer Architecture …………………………………
Lecture No.4
5.3 Instructions Types
Instructions can be classified based on the number of operands as:
5.3.1 Three Address Instructions
In instruction that have three operands, one of the operand specifies the
destination as an address where the result is to be saved. The other two operands
specify the source either as addresses of memory location or constants.
Example 1: Execute the following instruction using three address format:
x=c*b/r-d
Sol : the solution is shown below, together with comments that explain the register
transfer operation of each instruction.
Step No.
1
2
3
Step
mul R1,c,b
sub R2,r,d
div X , R1,R2
Description
R1 c*b
R2  r-d
X  r1/r2
The advantage of the three-address format is that it results in short programs
when evaluating arithmetic expressions.
5.3.2.Two'Address Instructions
In this type both operands specify sources. The first operand also specifies
the destination address after the result is to be saved. The first operand must be an
address in memory, but the second may be an address or a constant.
Example 2 : Execute the following instruction using two address format :
x=c*b/r-d
Sol : the solution is shown below, together with comments that explain the register
transfer operation of each instruction.
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Computer Architecture …………………………………
Step No.
1
2
3
4
5
6
Step
mov R1,c
mul R1,b
Mov R2,r
Sub R2,d
Div R1,R2
Mov x,R1
Lecture No.4
Description
R1 c
R1  R1*b
R2  r
R2R2-d
R1R1/R2
x R1
Note that :
 In this type of instruction we can use (mov) beside the arithmetic operations.
 This method requires more steps than previous method to represent the same
instruction.
 For temporary storage use a register.
5.3.3.One'Address Instructions
Some computer has only one general purpose register, usually called Ac
"Accumulator". It is implied as one of the source operands and the destination
operand in memory instruction the other source operand is specified in the
instruction as location in memory.
Example 3 : Execute the following instruction using one address format :
x=c*b/r-d
Sol : the solution is shown below, together with comments that explain the register
transfer operation of each instruction.
Step No.
1
2
3
4
5
6
7
Step
load r
Sub d
Store t
load c
Mul b
Div t
Store x
Description
Ac r
Ac  Ac-d
T  Ac
Ac  c
Ac  Ac*b
Ac  Ac/t
X  Ac
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Computer Architecture …………………………………
Lecture No.4
Note that :
 In this type of instruction we can use (load) and (store) beside the arithmetic
operations.
 This method requires more steps than previous methods to represent the
same instruction.
 For temporary storage use a memory location and is not a register. Why ?
5.3.4.Zero'Address Instructions
Some computers have arithmetic instruction in which all operands are
implied, these zero operand instruction use a stack. A stack is a list structure in
which all insertion and deletion occur at one end, the element on a stack may be
removed only in the reverse of the order in which they were entered. The process of
inserting an item is called Pushing, removing an item is called Popping.
Example: Execute the following instruction using Zero-address format:
x=c*b/r-d
Sol :
Step No.
1
2
3
Step
Push d
Push r
Sub
4
5
6
Push b
Push c
Mul
7
Div
Description
TOS  d "TOP :Top OF Stack"
TOS  r
Pop d
Pop r
Sub them
TOS  (r-d)
TOS  b
TOS  c
Pop c
Pop b
multiply them
TOS  (c*b)
Pop (c*b)
Pop (r-d)
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Computer Architecture …………………………………
8
Pop x
Lecture No.4
Divide
TOS  (c*b) / (r-d)
X  TOS
Home Work: Execute the following instruction using all previous instruction
format types:
1- X = (A + B)* (C + D)
2- S = F-(C*B)+M
3- N= (A+B*C)/ (F*E)
5.4 Instruction Length
Instruction length is the number of bits or bytes which defines an instruction.
This can be done simply by specifying how many bits in each field in the
instruction.
The length of pcode field is inferred from the (No. of instructions) supported
by the processor. By convert the No. of instruction supported by the processor to
the form 2n , n will be the No. of bits for (opcode field).
Example : If the CPU can do 64 instruction , then the no. of bits in the opcode
field will be : 64  26  n=6 .Therefore the no. of bits =6.
The length of address field is inferred from memory which is formulated as
follow:
2n B
2n W
(30 KW, 256 MB, 1GB…..) Where n will be the No. of bits in each address field.
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Computer Architecture …………………………………
Lecture No.4
Example : Memory size = 1 KB
1K = 2
10
 n= 10
Address bits =10
Example: A Computer have memory size 16 kw where word is 16 bit. The
instruction stored in one location (word) the instruction have three parts :
operation code field, and address field.
1- How many bit in each field?
2- Draw the instruction format and indicate the No. of bits.
3- Specify the No. of operation in this computer.
SOL:
1- Memory size = 16 kw  16 k = 24 × 210 = 214  14 bit address line.
 No. of bit for operand field = 14.
Now:
The instruction stored in one location (word) and the word =16 bit
 No. of bit for opcode field = 16 – 14 = 2
2-
Opcode
2 bit
Operand (address)
14 bit
3-The No. of bit for operation = 2 No. of bit for opcode field
= 22 = 4 operations
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