8
6
7
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS
NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR
USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER
PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES.
1
2
3
4
5
REVISIONS
JUMPER TABLE
REV
JP#
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY ANALOG DEVICES.
ON
DESCRIPTION
DATE
APPROVED
OFF
1
2
3
RELAY CONTROL CHART
D
D
4
CONTROL
CODE
DEVICE
FUNCTION
CONNECTOR
5
* SEE ASSEMBLY INSTRUCTIONS
C
C
B
B
TEMPLATE ENGINEER
DATE
A N A LO G
D EV C E S
SCHEMATIC
MARCH 2009
HARDWARE SERVICES
TITLE
HARDWARE SYSTEMS
TEST ENGINEER
A
AD9265 CMOS EVALUATION BOARD
COMPONENT ENGINEER
TEST PROCESS
HARDWARE RELEASE
P.O SPEC. BK/BD SPEC. SOCKET OEM
8
OEM PART#
7
HANDLER
DESIGNER
MASTER PROJECT TEMPLATE
PTD ENGINEER
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES
5
4
3
FRACTIONS
+-1/32
ANGLES
+-2
2
REV.
DRAWING NO.
A
AD9265CE01A
TOLERANCES
DECIMALS
X.XX +-0.010
X.XXX +-0.005
CHECKER
6
TESTER TEMPLATE
SIZE
D
SCALE
CODE ID NO.
SHEET
1
1
OF
8
A
8
6
7
2
3
4
5
1
REVISIONS
VARIABLE POWER SUPPLY INPUT
REV
DESCRIPTION
DATE
APPROVED
E6
1
2
5V_AVDD
C55
10UF
100MHZ
GND
POWER SUPPLY INPUT
D
1
C
PGND
2
3V_AVDD
GND
D
AVDD: +1.8V
DRVDD: +1.8V
SVDD: +1.8V TO +3.3V
C57
10UF
100MHZ
LNJ308G8TRA (GREEN)
4
6
3
5
BNX012-01
GND
E4
Z5.531.3625.0
P8
1
2
3
4
5
6
R67
249
PJ-002AH-SMT
CR6
S2A-TP
A
C63
10UF
CR7
1
2
3
1
C
1 F1 2
1.1A
FL1
2
A
P26
AD9265
E8
GND
1
5V_AVDD_RAW
2
3V_CLK
REST OF BOARD
C84
10UF
100MHZ
3V_AVDD_RAW
V_DIG: +1.8V TO +3.3V (SPI, CMOS BUFF)
3V_AVDD: +3.3V (AMP)
5V_AVDD: +5V (AMP)
AMP_VSS: -5V OR GND (AMP VS OPTION)
GND
E12
1
AVDD_RAW
2
AVDD
GND
100MHZ
SUPPLY REGULATORS
ADP1708ARDZ-R7 U8
1
EN
7
SENSE
3
5
IN
OUT
4
6
IN2
OUT2
8 ADJ
R74
147K
C
A
R75
28K
C53
4.7UF
Z5.531.3625.0
P9
1
2
3
4
5
6
P27
+5V_REG
5V_AVDD_RAW
GND1 PAD
1
2
TSW-102-08-G-S
C64
4.7UF
2 PAD
E7
1
SVDD_RAW
DRVDD_RAW
C56
10UF
V_DIG_RAW
P18
1 JP25 2
JPR0402
GND
1
2
GND
GND
C
CONNECT FOR EXTERNAL NEGATIVE AMPLIFIER VOLTAGE
TSW-102-08-G-S
E10
C
1
U4
1
7
3
4
8
2
C59
10UF
100MHZ
EN
SENSE
IN
OUT
IN2
OUT2
SS
GND1 PAD
P28
5
6
+3.3V_REG
GND
1
2
3V_AVDD_RAW
TP10
BLK
TSW-102-08-G-S
2 PAD
C75
10000PF
PLACE CLOSE TO AMPLIFIER
DRVDD
ADP1706ARDZ-3.3-R7
TP11
BLK
E9
C65
4.7UF
1
A
1
TP2
BLK
1
TP3
BLK
GND
2
V_DIG
100MHZ
CR4
C58
10UF
GND
C
S2A-TP
SVDD
100MHZ
GND
C54
4.7UF
AMP_VSS
2
GND
CR3
S2A-TP
C9
10UF
GND
GND
1
E1
B
C
CR5
S2A-TP
100MHZ
2
A
C72
10UF
V_DIG_RAW
ADP1706ARDZ-1.8-R7
U9
C73
10UF
C74
1UF
1
7
3
4
8
OPTIONAL SWITCHING POWER SUPPLY
R76
100K
E2
1
GND
L2 DNI
SW
FB
EN
C82
E5
5
6
GND
ADP2108AUJZ-1.8-R7 2
5
4
2.2UH
L3 DNI
2.2UH
C77
10UF
DNI
100MHZ
1
GND
E3 DNI
2
U10
1
7
3
4
8
AVDD_RAW
C81
10UF
C68
4.7UF
DNI
A
2
DRVDD_RAW
GND
100MHZ
1
100MHZ
C80
10UF
GND
DNI
DNI
E11
SW_1.8_DIG
DNI
C79
10UF
P30
1
2
3
SAMTECTSW10608GS3PIN
2
100MHZ
SW_1.8_DIG
GND
C83
EN
SENSE
IN
OUT
IN2
OUT2
SS
GND1 PAD
10000PF
2 PAD
5
6
B
SVDD_RAW
C67
4.7UF
2 PAD
10000PF
2
1
+1.8V_REG
GND
VIN
3
DNI
U6
1
C62
4.7UF
EN
SENSE
IN
OUT
IN2
OUT2
SS
GND1 PAD
P29
1
2
TSW-102-08-G-S
AVDD_REG
AVDD_RAW
ADP1706ARDZ-1.8-R7
P32
1
2
TSW-102-08-G-S
P31
1
2
TSW-102-08-G-S
C69
4.7UF
A
GND
SCHEMATIC
A N A LO G
DE V CES
TITLE
AD9265 CMOS EVALUATION BOARD
THIS DRAWING
IS THE PROPERTY
IT IS NOT TO BE REPRODUCED
OF ANALOG DEVICES
OR COPIED,
IN PART, OR USED IN FURNISHING
OR FOR ANY OTHER PURPOSE
OF ANALOG
7
6
5
4
3
DRAWING NO.
AD9265CE01A
TO OTHERS,
SIZE
PTD ENGINEER
SHOWN HEREON MAY BE PROTECTED
OWNED OR CONTROLLED
DESIGN VIEW
TO THE INTERESTS
DEVICES.
THE EQUIPMENT
8
INFORMATION
DETRIMENTAL
INC.
IN WHOLE OR
DD
BY PATENTS
BY OWNED ANALOG DEVICES.
2
SCALE
SHEET 2
1
REV
A
OF 8
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
D
D
P12
P5
SENSE
1
2
3
R6
DNI
DRVDD
P10
AVDD
1
2
3
0
1
2
LVDS_EN
1
2
SPARE1
TSW-102-08-G-S
VREF
DNI
TSW-102-08-G-S
R36
10K
R38
10K
GND
DNI
WHT
R51
TBD0402
TBD0402
EXT_REF
GND
1
R50
GND
P14
TP4
GND
DRVDD
1
2
LVDS_RR_EN
P17
DRVDD
LVDS_RR_EN
1
2
SPARE0
TSW-102-08-G-S
AVDD
C45
C66
GND
P16
DRVDD
LVDS_EN
0.1UF
DNI
TSW-102-08-G-S
R37
10K
R39
10K
GND
GND
0.1UF
VCM_DUT
C41
C39
GND
R70
10K
LVDS_EN
LVDS_RR_EN
SPARE1
SPARE0
10K
GND
GND
GND
GND
0.1UF
CLK+
CLK-
AVDD
C60
0.1UF
C61
0.1UF
GND
P3
SYNC
CLK+
CLKAVDD
AVDD
OEB
NC
DCO
D0
D1
D2
D3
AVDD
DITH_EN
AVDD
SVDD
CSB
SCLK/DFS
SDIO/DCS
DRVDD
NC
OR
D15
D14
AD9265
CMOS
P11
DRVDD
36
35
34
33
32
31
30
29
28
27
26
25
TSW-102-08-G-S
CSB
SCLK
SDIO
R35
10K
GND
GND
DRVDD
OR
D15
D14
SG-MLF-7006
D4
D5
D6
D7
D8
GND
DITH_EN
TSW-102-08-G-S
C43
0.1UF
B
GND
13
14
15
16
17
18
19
20
21
22
23
24
R69
10K
1
2
SVDD
DRVDD
D4
D5
D6
D7
D8
D9
DRVDD
D10
D11
D12
D13
OEB
DRVDD
1
2
DCO
D0
D1
D2
D3
1
2
3
4
5
6
7
8
9
10
11
12
GND
DUT
C47
2 3 4 5
B
PAD
48
47
46
45
44
43
42
41
40
39
38
37
1
R33
49.9
SYNC INPUT
VINVIN+
GND
C40
GND
PDWN
RBIAS
VCM
AVDD
LVDS_EN
VINVIN+
LVDS_RR_EN
NC
NC
VREF
SENSE
J3
AVDD
0.1UF
TP9
WHT
C48
1
R68
0.1UF
1
PDWN
2
TSW-102-08-G-S
C
1UF
1UF
GND
DRVDD
0.1UF
P7
C46
C
NEED TO UPDATE AD9265 SYMBOL TO SHOW PINS 39 AND 40 AS NC.
ALSO NEED TO ADD AD9265/55 IN FOR PART NAME.
PIN 46 SHOULD BE VCM (NOT CML)
D13
D12
D11
D10
D9
GND
0.1UF
C42
0.1UF
DRVDD
C38
DRVDD
GND
A
A
SCHEMATIC
A N A LO G
DE V CES
TITLE
AD9265 CMOS EVALUATION BOARD
THIS DRAWING
IS THE PROPERTY
IT IS NOT TO BE REPRODUCED
OF ANALOG DEVICES
OR COPIED,
IN PART, OR USED IN FURNISHING
OR FOR ANY OTHER PURPOSE
OF ANALOG
7
6
5
4
3
DRAWING NO.
AD9265CE01A
TO OTHERS,
SIZE
PTD ENGINEER
SHOWN HEREON MAY BE PROTECTED
OWNED OR CONTROLLED
DESIGN VIEW
TO THE INTERESTS
DEVICES.
THE EQUIPMENT
8
INFORMATION
DETRIMENTAL
INC.
IN WHOLE OR
DD
BY PATENTS
BY OWNED ANALOG DEVICES.
2
SCALE
SHEET 3
1
REV
A
OF 8
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
D
D
C16
3V_CLK
0.1UF
GND
P6
Y1
4
C70
VCC
1
2
1
TRISTATE CTRL
GND
TSW-102-08-G-S
2
R7
1.00K
OUT
3
XTAL_IN
0.1UF
125MHZ
CLKIN+
DNI
GND
R28
0
BALUN CLOCK CIRCUITRY
DNI
3
R93
24.9
DNI
CLK+
HSMS-2812BLK
DNI
CR1
1
0.1UF
R85A
0
3
GND
CLKOUT-
R86A
0
GND
GND
R31
R86
0
0
C23
DNI
CLK-
0.1UF
GND
DNI
DNI
C30
3 T1 6
1
R29
0
WHT
0.1UF
R12
49.9
1
DNI
1
4
C27
TP6
BLK
GND
GND
ADT1-1WT+
GND
DNI
DNI
2
DNI
0.1UF
2 3 4 5
R17
24.9
TP5
1
J7
C
CLKOUT+
2
DNI
SEC
4
R48
0
R25
49.9
0
R73
100
PRI
0.1UF
2 3 4 5
0
C22
DNI
1
DNI
R85
DNI
0.1UF
C18
J6
R30
100
C6
MABA-007159-000000
T9
5
1
T5
CLOCK INPUT
C
R72
SEC
XTAL_IN
PRI
MABA-007159-000000
GND
CLKIN-
GND
B
B
A
A
SCHEMATIC
A N A LO G
DE V CES
TITLE
AD9265 CMOS EVALUATION BOARD
THIS DRAWING
IS THE PROPERTY
IT IS NOT TO BE REPRODUCED
OF ANALOG DEVICES
OR COPIED,
IN PART, OR USED IN FURNISHING
OR FOR ANY OTHER PURPOSE
OF ANALOG
7
6
5
4
3
DRAWING NO.
AD9265CE01A
TO OTHERS,
SIZE
PTD ENGINEER
SHOWN HEREON MAY BE PROTECTED
OWNED OR CONTROLLED
DESIGN VIEW
TO THE INTERESTS
DEVICES.
THE EQUIPMENT
8
INFORMATION
DETRIMENTAL
INC.
IN WHOLE OR
DD
BY PATENTS
BY OWNED ANALOG DEVICES.
2
SCALE
SHEET 4
1
REV
A
OF 8
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
C619
3V_CLK
GND
0.1UF
U603
WHT
5
3V_CLK
1
R606
1.00K
R607
1.00K
STATUS
OUT0
OUT0_N
OUT1
OUT1_N
OUT2
OUT2_N
OUT3
OUT3_N
OUT4_OUT4A
OUT4_N_OUT4B
OUT5_OUT5A
OUT5_N_OUT5B
OUT6_OUT6A
OUT6_N_OUT6B
OUT7_OUT7A
OUT7_N_OUT7B
LF
11
12
9517_CLK
R605
1.00K
BYPASS
8
LF
3V_CLK
CP
9
BYPASS_LDO
0.1UF
LD
CLK
CLK_N
C621
GND
0.1UF
18
7
17
AD9517_PWDNBUF
PD_N
SYNC_N
RESET_N
3V_CLK
C
R609 FIFO_SCLK
13
1.00K
FIFO_SDI 16
14
R608
AD9517_CSB
SCLK
SDIO
CS_N
SDO
PAD
0
44
1
46
4
NC7WZ16P6X
GND
CP
GND
5
C603
42
41
39
38
19
20
22
23
35
34
33
32
26
27
28
29
15
CLKOUT+
0.1UF
R614
200
PECL_OUT1
PECL_OUT1_N
GND
R616
200
C604
CLKOUT-
0.1UF
C
TP604
FIFO_SDO
AD9517-4BCPZ
C623
R640
100
WHT
0.1UF
2 3 4 5
GND
DNI
J603
1
4
3
PRI
SEC
DNI
0.1UF
DNI
5 4 3 2
GND
DNI
DNI
5
GND
R633
57.6
1
GND
GND
C624
DNI
MABA-007159-000000
PECL_OUT1_N
GND
CHARGE PUMP FILTER
R638
200
1
9517_CLK
DNI
T601
0.1UF
TP605
C620
DNI
C660
PECL_OUT1
GND
J602
D
GND
2
WHT
PAD
1
A
C
SML-LXT0805IW-TR
200
GND
2
4
Y2
DNI
CLKIN+
REFIN_REF1
REFIN_N_REF2
A2
R651
57.6
48
47
C602
3
CR601
R630
GND
U601
VCP
RSET
REFMON
CPRSET
6
1
0.1UF
VS
REF_SEL
Y1
TP603
R611
5.11K
VS_LVPECL
6
C601
CLKIN-
A1
0
TP602
1
10
24
25
30
31
36
37
43
45
3
21
40
R604
1.00K
1
R610
4.12K
3V_CLK
D
WHT
1
VCC
R629
TP601
WHT
PECL/CML/LVDS CLK CIRCUITRY
DNI
R639
200
0.1UF
DNI
R627
0
R626
100
1500PF
B
.033UF
C606
C605
R625
200
C607
LF
B
1800PF
CP
R623
0
GND
3V_CLK
C608
BYPASS_LDO
C622
.22UF
0.1UF
C609
C614
0.1UF
0.1UF
C610
C615
0.1UF
C611
0.1UF
C616
0.1UF
C612
0.1UF
C617
GND
A
0.1UF
C613
0.1UF
C618
0.1UF
0.1UF
GND
A
GND
SCHEMATIC
A N A LO G
DE V CES
TITLE
AD9265 CMOS EVALUATION BOARD
THIS DRAWING
IS THE PROPERTY
IT IS NOT TO BE REPRODUCED
OF ANALOG DEVICES
OR COPIED,
IN PART, OR USED IN FURNISHING
OR FOR ANY OTHER PURPOSE
OF ANALOG
7
6
5
4
3
DRAWING NO.
AD9265CE01A
TO OTHERS,
SIZE
PTD ENGINEER
SHOWN HEREON MAY BE PROTECTED
OWNED OR CONTROLLED
DESIGN VIEW
TO THE INTERESTS
DEVICES.
THE EQUIPMENT
8
INFORMATION
DETRIMENTAL
INC.
IN WHOLE OR
DD
BY PATENTS
BY OWNED ANALOG DEVICES.
2
SCALE
SHEET 5
1
REV
A
OF 8
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
D
D
ANALOG INPUT CIRCUITRY
DNI
GND
GND
R32
GND
0
R95 DNI
49.9
2 3 4 5
2
1
4
5 (NC)
ADT1-1WT+
0.1UF
DNI
DNI
GND
C97
0
C
AIN_VCM
DNI
VIN+
C15
C1
2.2PF
10PF
DNI
R15
33
GND
JP7
C71
R96
AIN_VCM
10
R16
33
DNI
1
2
JPSLD02
0.1UF
DNI
1
DNI
6
C25
0.1UF
C0402
J2
3
100
R3
10
DNI
GND
T6
0.1UF
R22
L1
R47
0
3
AIN_VCM
R46
0
4
T3
R4
49.9
2 3 4 5
R5
1
0.1UF
SEC
0
AMP_OUT+
1
2
JPSLD02
SEC
5
PRI
C2
10PF
JP6
C96
PRI
C3
R1
1
MABA-007159-000000
4
3
J1
MABA-007159-000000
T2
5
1
15NH
R34
0
R23
R8
10
10
AMP_OUT-
VIN-
C
C4
10PF
GND
TP19
1
WHT
GND
TP1
BLK
JP8
VCM_DUT
1
2
3
AIN_VCM
1 JP4 2
JPR0402
AMP_VCM
GND
A
COM
B
OPTIONAL ANALOG INPUT
3PIN_SOLDER_JUMPER
JP5
1
2
3
3V_AVDD
B
R10
0.1UF DNI
0
12
R94
49.9
0
DNI
R14
57.6
0
DNI
C14
R42
0
0.1UF
VON
VOP
ENBL
VCOM
GND
DNI
DNI
10
11
PAD
C49
R18
24.9
R43
10K
AMP_VSS
36NH
DNI
DNI
DNI
R20
1.00K
C13
100PF
DNI
DNI
L6
L8
15NH
36NH
AMP_OUT-
1000PF
DNI
DNI
DNI
JP1
ADL5562_PRELIM
GND
15NH
R21
1.00K
9
GND
P19
AMP_VDD
1
PDWN/ENBL
2
TSW-102-08-G-S
L9
AMP_VCM
DNI
DNI
GND
A
1000PF
VCC
VIP2
VIP1
VIN1
VIN2
13
14
15
16
PAD
0
2 3 4 5
R0603
R54
R45
200
C51
GND
R0402
R52
5
6
7
8
R11
1
2
3
4
L5
AMP_OUT+
24.9
U1
2
1
JPR0402
0.1UF
-(NC)
DNI
C50
R19
0
0.1UF
R13
57.6
C34
3
DNI
SEC
4
2
R41
DNI
PRI
C12
R44
200
1
MABA-007159-000000
1
3PIN_SOLDER_JUMPER
T4
5
GND
J9
A
COM
B
GND
DNI
DNI
C52
B
0.1UF
0
5V_AVDD
10UF
C8
R0603
R56
0.1UF
C7
AMP_VDD
AMP_VCM
C5
0.1UF
GND
A
GND
SCHEMATIC
PAD IS NOT ELECTRICALLY CONNECTED INSIDE AMP
A N A LO G
DE V CES
TITLE
AD9265 CMOS EVALUATION BOARD
THIS DRAWING
IS THE PROPERTY
IT IS NOT TO BE REPRODUCED
OF ANALOG DEVICES
OR COPIED,
IN PART, OR USED IN FURNISHING
OR FOR ANY OTHER PURPOSE
OF ANALOG
7
6
5
4
3
DRAWING NO.
AD9265CE01A
TO OTHERS,
SIZE
PTD ENGINEER
SHOWN HEREON MAY BE PROTECTED
OWNED OR CONTROLLED
DESIGN VIEW
TO THE INTERESTS
DEVICES.
THE EQUIPMENT
8
INFORMATION
DETRIMENTAL
INC.
IN WHOLE OR
DD
BY PATENTS
BY OWNED ANALOG DEVICES.
2
SCALE
SHEET 6
1
REV
A
OF 8
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
OUTPUT BUFFERS
P25
D
D
R26
1
2
10K
R27
DNI
RN4
5
22
D2
D3
4 RN10 5
22
D4
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
1
56
29
28
GND
22
3 RN10 6
22
2 RN107
22
1 RN10 8
D5
D6
D7
22
4 RN5 5
22
3 RN5 6
22
2 RN5 7
D8
D9
D10
22
1 RN5 8
22
4 RN9 5
22
3 RN9 6
D11
D12
D13
2 RN9 7 22
22 1 RN9 8
22
D14
D15
OR
C29
0.1UF
C31
0.1UF
GND
22
3 RN4 6
22
2 RN4 7
22
1 RN4 8
D1
C11
0.1UF
V_DIG
GND
50
35
22
7
4
D0
C
10K
R49
DCO
C10
0.1UF
R71
TP7
BLK
VCC
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
O16
O17
O18
O19
P15
U2
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
DCO_O
D0_O
D1_O
D2_O
D3_O
D4_O
D5_O
D6_O
D7_O
D8_O
D9_O
D10_O
D11_O
D12_O
D13_O
D14_O
D15_O
OR_O
SPI CIRCUITRY
C33
SVDD
GND
SVDD
0.1UF
NC7WZ07P6X 5
R62
1.00K
U3
R83
0
1
A1
Y1
6
R63
R84
3
A2
Y2
4
1.00K
FIFO_FPGA_SDI
0
DNI
74VCX162827MTDX
VCC
P4
1
2
3
4
5
6
7
8
9
SDIO
GND
R58
10K
C
R66
100K
FIFO_SDI
GND
4
11
18
25
32
39
46
53
22
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
I15
I16
I17
I18
I19
OE1_N
OE2_N
OE3_N
OE4_N
R64
100K
2
GND
1
2
GND
GND
GND
GND
CSB
DNI
TSW-103-08-G-T
GND
R61
1.00K
SCLK
3V_CLK
FIFO_SDO
R79
R65
100K
0
FIFO_FPGA_SDO
SVDD
R80
GND
C78
0
DNI
B
FIFO_SCLK
VCC
R78
0
OTR LED CIRCUIT
B
U5
5
0
FIFO_FPGA_SCLK
GND
0.1UF
R59
10K
R77
1
A1
Y1
6
3
A2
Y2
4
DNI
GND
2
C32
FIFO_CSB
3V_AVDD
GND
1
A1
Y1
6
0
R55
249
3
A2
Y2
4
FIFO_FPGA_CSB
CR2
GND
R82
0
DNI
A
C
SML-LXT0805IW-TR
GND
GND
R40
10K
NC7WZ16P6X
0
U7
VCC
R53
R81
GND
0.1UF
5
OR_O
R57
10K
2
NC7WZ16P6X
GND
GND
A
A
SCHEMATIC
A N A LO G
DE V CES
TITLE
AD9265 CMOS EVALUATION BOARD
THIS DRAWING
IS THE PROPERTY
IT IS NOT TO BE REPRODUCED
OF ANALOG DEVICES
OR COPIED,
IN PART, OR USED IN FURNISHING
OR FOR ANY OTHER PURPOSE
OF ANALOG
7
6
5
4
3
DRAWING NO.
AD9265CE01A
TO OTHERS,
SIZE
PTD ENGINEER
SHOWN HEREON MAY BE PROTECTED
OWNED OR CONTROLLED
DESIGN VIEW
TO THE INTERESTS
DEVICES.
THE EQUIPMENT
8
INFORMATION
DETRIMENTAL
INC.
IN WHOLE OR
DD
BY PATENTS
BY OWNED ANALOG DEVICES.
2
SCALE
SHEET 7
1
REV
A
OF 8
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
D
D
FIFO 5 CONNECTIONS
OR_O
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
6469169-1
6469169-1
6469169-1
GND 6469169-1
P2
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
6469169-1
GND
PLUG HEADER
PLUG HEADER
PLUG HEADER
P2
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
PLUG HEADER
6469169-1
P1
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
C
6469169-1
P2
P2
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
GND
GND 6469169-1
PLUG HEADER
P2
D0_O
D2_O
D4_O
D6_O
D8_O
D10_O
D12_O
D14_O
P1
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
PLUG HEADER
B
6469169-1
P1
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
PLUG HEADER
D1_O
D3_O
D5_O
D7_O
D9_O
D11_O
D13_O
D15_O
DCO_O
PLUG HEADER
P2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
FIFO_SDO
FIFO_SDI
FIFO_SCLK
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
PLUG HEADER
6469169-1
6469169-1
P1
FIFO_FPGA_SDI
FIFO_FPGA_SCLK
PLUG HEADER
FIFO_FPGA_SDO
FIFO_FPGA_CSB
C
PLUG HEADER
AD9517_CSB
FIFO_CSB
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
PLUG HEADER
P1
P1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B
6469169-1
A
A
SCHEMATIC
A N A LO G
DE V CES
TITLE
AD9265 CMOS EVALUATION BOARD
THIS DRAWING
IS THE PROPERTY
IT IS NOT TO BE REPRODUCED
OF ANALOG DEVICES
OR COPIED,
IN PART, OR USED IN FURNISHING
OR FOR ANY OTHER PURPOSE
OF ANALOG
7
6
5
4
3
DRAWING NO.
AD9265CE01A
TO OTHERS,
SIZE
PTD ENGINEER
SHOWN HEREON MAY BE PROTECTED
OWNED OR CONTROLLED
DESIGN VIEW
TO THE INTERESTS
DEVICES.
THE EQUIPMENT
8
INFORMATION
DETRIMENTAL
INC.
IN WHOLE OR
DD
BY PATENTS
BY OWNED ANALOG DEVICES.
2
SCALE
SHEET 8
1
REV
A
OF 8