CDA3101 Assignment 2
Due 3/22
Submissions are due by the beginning of class on the specified due date. Handwritten
or typed solutions are acceptable. If you do write your solutions by hand, be sure to
write clearly. If the grader cannot read your answer, they cannot give you the points.
Late submissions will be accepted with a 10% penalty for each day they are late (up to
48 hours). You must show how you arrived at the answer or no credit will be given.
1. (30 pts) Explain the differences between single-cycle, multi-cycle, and pipelined
processors as if you’re teaching these concepts to your friend. In particular, explain how
a clock cycle is defined in each scheme as well as the unique datapath elements
needed for each implementation. What are the advantages and disadvantages of each
of the three implementations? Be as clear and thorough as possible to help your friend
understand. Use diagrams if you’d like.
2. (20 pts) A computer architect needs to design the pipeline of a new microprocessor.
She has an example program with 106 instructions. Each instruction takes 600 ps to
finish.
a. How long does it take to execute this program on a non-pipelined, single-cycle
processor?
b. Assume the current state-of-the-art pipeline has 30 stages. Assume also that the
stages are perfectly balanced. How much speedup will it achieve compared to
the non-pipelined processor?
c. Realistically, we cannot achieve ideal speedup due to the overhead of
implementing pipelining stages (e.g. imperfectly balanced stages, adding
pipeline registers, etc). Does this overhead affect the instruction latency,
instruction throughput, or both? For each metric affected, is the effect significant?
Why or why not?
3. (25 pts) Consider the following instructions. Complete the pipeline diagram,
indicating the cycle in which each instruction’s stages are executed. Assume that
forwarding is used to avoid stalls, when possible. Draw lines between stages to indicate
forwarded values. If necessary, stalls may be indicated with an ‘S’. You will certainly
need more cycles than are included below.
Cycle
add $s3,$s4,$s2
sub $s5,$s3,$s1
lw $s6,12($s3)
add $s7,$s3,$s6
lw $s6,12($s5)
add $s6,$s5,$s6
1
IF
2
ID
3
EX
4
5
6
MEM WB
7
8
9
4. (25 pts) We’ve discussed three possible solutions to the control hazard issue. Explain
and give an example of each approach. Make sure to describe the scenario in which
stalls are required in each approach and indicate how many stalls are required in that
scenario.
a. Assume branch not taken.
b. Perform branching in the ID stage.
c. Branch prediction (assume we’re using a 1-bit branch prediction buffer and an
initially-empty branch target buffer).