Ultralow Distortion IF VGA
AD8375
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Bandwidth of 630 MHz (−3 dB)
Gain range: −4 dB to +20 dB
Step size: 1 dB ± 0.2 dB
Differential input and output
Noise figure: 8 dB @ maximum gain
Output IP3 of ~50 dBm at 200 MHz
Output P1dB of 19 dBm at 200 MHz
Provides constant SFDR vs. gain
Parallel 5-bit control interface
Power-down feature
Single 5 V supply operation
24-lead, 4 mm × 4 mm LFCSP
COMM
VPOS
VCOM
PWUP
AD8375
OUT+
VIN+
OUT+
α
POST-AMP
OUT–
VIN–
OUT–
APPLICATIONS
A4
A3
A2
A1
06724-001
REGISTERS
AND
GAIN DECODER
A0
Figure 1.
Differential ADC drivers
High IF sampling receivers
Wideband multichannel receivers
Instrumentation
GENERAL DESCRIPTION
The AD8375 is powered on by applying the appropriate logic
level to the PWUP pin. The quiescent current of the AD8375 is
typically 130 mA. When powered down, the AD8375 consumes
less than 5 mA and offers excellent input-to-output isolation.
Rev. A
65
–50
60
–60
55
OIP3
–70
50
–80
45
HD2
–90
40
HD3
–100
–110
40
35
60
80
100
120
140
FREQUENCY (MHz)
160
180
30
200
OIP3 (dBm), OUTPUT @ 3dBm/TONE
The AD8375 provides a broad 24 dB gain range with 1 dB
resolution. The gain is adjusted through a 5-pin control interface
and can be driven using standard TTL levels. The open-collector
outputs provide a flexible interface, allowing the overall signal
gain to be set by the loading impedance. Thus, the signal
voltage gain is directly proportional to the load.
–40
06724-052
Using an advanced high speed SiGe process and incorporating
proprietary distortion cancellation techniques, the AD8375
achieves 50 dBm output IP3 at 200 MHz.
Fabricated on an Analog Devices, Inc., high speed SiGe process,
the AD8375 is supplied in a compact, thermally enhanced,
4 mm × 4 mm, 24-lead LFCSP package and operates over the
temperature range of −40°C to +85°C.
HARMONIC DISTORTION (dBc), OUTPUT @ 2V p-p
The AD8375 is a digitally controlled, variable gain, wide
bandwidth amplifier that provides precise gain control, high
IP3, and low noise figure. The excellent distortion performance
and high signal bandwidth make the AD8375 an excellent gain
control device for a variety of receiver applications.
Figure 2. Harmonic Distortion and Output IP3 vs. Frequency
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Technical Support
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AD8375
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Basic Structure ............................................................................ 12
Applications ....................................................................................... 1
Applications..................................................................................... 13
Functional Block Diagram .............................................................. 1
Basic Connections ...................................................................... 13
General Description ......................................................................... 1
Single-Ended-to-Differential Conversion............................... 13
Revision History ............................................................................... 2
Broadband Operation ................................................................ 14
Specifications..................................................................................... 3
ADC Interfacing ......................................................................... 14
Absolute Maximum Ratings............................................................ 5
Layout Considerations ............................................................... 17
ESD Caution .................................................................................. 5
Characterization Test Circuits .................................................. 17
Pin Configuration and Function Descriptions ............................. 6
Evaluation Board ........................................................................ 18
Typical Performance Characteristics ............................................. 7
Outline Dimensions ....................................................................... 22
Circuit Description ......................................................................... 12
Ordering Guide .......................................................................... 22
REVISION HISTORY
10/12—Rev. 0 to Rev. A
Change to Maximum Junction Temperature Parameter,
Table 3 ................................................................................................ 5
Added Exposed Pad Notation, Figure 3 and Exposed Pad
Notation, Table 4 ............................................................................... 6
Added Exposed Pad Notation to Outline Dimensions ............. 22
8/07—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
AD8375
SPECIFICATIONS
VS = 5 V, T = 25°C, RS = RL = 150 Ω at 140 MHz, 2 V p-p differential output, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
INPUT STAGE
Maximum Input Swing
Differential Input Resistance
Common-Mode Input Voltage
CMRR
GAIN
Amplifier Transconductance
Maximum Voltage Gain
Minimum Voltage Gain
Gain Step Size
Gain Flatness
Gain Temperature Sensitivity
Gain Step Response
OUTPUT STAGE
Output Voltage Swing
Output Impedance
NOISE/HARMONIC PERFORMANCE
46 MHz
Noise Figure
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
70 MHz
Noise Figure
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
140 MHz
Noise Figure
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
200 MHz
Noise Figure
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
Conditions
Min
VOUT < 2 V p-p (5.2 dBm)
Pin VIN+ and Pin VIN−
For linear operation (AV = −4 dB)
Differential
Max
630
5
125
Gain code = 00000
Gain code = 00000
Gain code = 00000
Gain code ≥ 11000
From gain code = 00000 to 11000
All gain codes, 20% fractional bandwidth for fC < 200 MHz
Gain code = 00000
For VIN = 100 mV p-p, gain code = 10100 to 00000
Pin VOUT+ and Pin VOUT−
At P1dB, gain code = 00000
Differential
Typ
0.060
0.89
8.5
150
1.9
55
0.067
20
−4
0.98
0.12
8
5
Unit
MHz
V/ns
165
0.074
1.01
V p-p
Ω
V
dB
S
dB
dB
dB
dB
mdB/°C
ns
12.6
16||0.8
V p-p
kΩ||pF
8.3
−92
−94
50
22
dB
dBc
dBc
dBm
dBm
8.3
−98
−95
51
22
dB
dBc
dBc
dBm
dBm
8.3
−90
−100
51
20
dB
dBc
dBc
dBm
dBm
8.3
−85
−92
50
19
dB
dBc
dBc
dBm
dBm
Gain code = 00000
VOUT = 2 V p-p
VOUT = 2 V p-p
2 MHz spacing, +3 dBm per tone
Gain code = 00000
VOUT = 2 V p-p
VOUT = 2 V p-p
2 MHz spacing, 3 dBm per tone
Gain code = 00000
VOUT = 2 V p-p
VOUT = 2 V p-p
2 MHz spacing, 3 dBm per tone
Gain code = 00000
VOUT = 2 V p-p
VOUT = 2 V p-p
2 MHz spacing, 3 dBm per tone
Rev. A | Page 3 of 24
AD8375
Data Sheet
Parameter
POWER INTERFACE
Supply Voltage
VPOS and Output Quiescent Current
vs. Temperature
Power-Down Current
vs. Temperature
POWER-UP/GAIN CONTROL
VIH
VIL
Logic Input Bias Current
Conditions
Thermal connection made to exposed paddle under device
−40°C ≤ TA ≤ +85°C
PWUP low
−40°C ≤TA ≤ +85°C
Pin A0 to Pin A4, Pin PWUP
Minimum voltage for a logic high
Maximum voltage for a logic low
Min
Typ
Max
Unit
4.5
120
5.0
125
5.5
130
150
V
mA
mA
mA
mA
2.5
3
1.6
0.8
900
Table 2. Gain Code vs. Voltage Gain Look-Up Table
5-Bit Binary Gain Code
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
Voltage Gain (dB)
+20
+19
+18
+17
+16
+15
+14
+13
+12
+11
+10
+9
+8
5-Bit Binary Gain Code
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
>11000
Rev. A | Page 4 of 24
Voltage Gain (dB)
+7
+6
+5
+4
+3
+2
+1
0
−1
−2
−3
−4
−4
V
V
nA
Data Sheet
AD8375
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage, VPOS
PWUP, A0 to A4
Input Voltage, VIN+, VIN−
DC Common Mode
VCOM
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
θJC (At Exposed Paddle)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
5.5 V
−0.6 V to (VPOS + 0.6 V)
−0.15 V to +4.15 V
VCOM ± 0.25 V
±6 mA
825 mW
63.6°C/W
14.6°C/W
140°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 5 of 24
AD8375
Data Sheet
24
23
22
21
20
19
COMM
VPOS
COMM
COMM
COMM
PWUP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
PIN 1
INDICATOR
AD8375
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
VOUT–
VOUT+
VOUT–
VOUT+
COMM
VPOS
NOTES
1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO GROUND.
SOLDER TO A LOW IMPEDANCE GROUND PLANE.
06724-002
A1
A0
VPOS
VPOS
COMM
VPOS
7
8
9
10
11
12
VCOM
VIN+
VIN–
A4
A3
A2
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9, 10, 12, 13, 23
11, 14, 20, 21, 22, 24
15, 17
16, 18
19
Mnemonic
VCOM
VIN+
VIN−
A4
A3
A2
A1
A0
VPOS
COMM
VOUT+
VOUT−
PWUP
EPAD
Description
Common-Mode Pin. Typically bypassed to ground using external capacitor.
Voltage Input Positive.
Voltage Input Negative.
MSB for the 5-Bit Gain Control Interface.
MSB − 1 for the Gain Control Interface.
MSB − 2 for the Gain Control Interface.
LSB + 1 for the Gain Control Interface.
LSB for the 5-Bit Gain Control Interface.
Positive Supply Pins. Should be bypassed to ground using suitable bypass capacitor.
Device Common (DC Ground).
Positive Output Pins (Open Collector). Require dc bias of +5 V nominal.
Negative Output Pins (Open Collector). Require dc bias of +5 V nominal.
Chip Enable Pin. Enabled with a logic high and disabled with a logic low.
Exposed Pad. The Exposed Pad is internally connected to ground. Solder to a low impedance
ground plane.
Rev. A | Page 6 of 24
Data Sheet
AD8375
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, RS = RL = 150 Ω, 2 V p-p output, maximum gain unless otherwise noted.
25
20
1.0
46MHz
70MHz
140MHz
200MHz
0.8
0.6
GAIN ERROR (dB)
GAIN (dB)
15
10
5
0.4
0.2
0
–0.2
–0.4
0
–0.6
–5
15
00101
20
00000
–1.0
–4
11000
Figure 4. Gain vs. Gain Code at 46 MHz, 70 MHz, 140 MHz, and 200 MHz
10
5
0
–5
–10
10
100
FREQUENCY (MHz)
1000
20
6
INPUT MAX
RATING
BOUNDARY
200MHz
140MHz
70MHz
46MHz
15
10
0
–4
1
11
6
16
21
GAIN (dB)
Figure 8. P1dB vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz
10
8
20
10100
5
Figure 5. Gain vs. Frequency Response
25
25°C
85°C
–40°C
20
OP1dB (dBm)
4
2
0
–2
15
+25°C
+85°C
–40°C
10
–4
–6
5
–10
–4
11000
0
10100
5
10
01111
01010
GAIN CODE
15
00101
20
00000
0
46
Figure 6. Gain Error over Temperature at 140 MHz
100
150
200
250
300
350
FREQUENCY (MHz)
400
450
500
06724-008
–8
06724-005
GAIN ERROR (dB)
GAIN (dB)
15
15
00101
25
OP1dB (dBm)
20
20dB
19dB
18dB
17dB
16dB
15dB
14dB
13dB
12dB
11dB
10dB
9dB
8dB
7dB
6dB
5dB
4dB
3dB
2dB
1dB
0dB
–1dB
–2dB
–3dB
–4dB
5
10
01111
01010
GAIN CODE
Figure 7. Gain Step Error, Frequency 140 MHz
06724-004
25
0
10100
06724-007
5
10
01111
01010
GAIN CODE
06724-003
0
10100
06724-006
–0.8
–10
–4
11000
Figure 9. P1dB vs. Frequency at Maximum Gain, Three Temperatures
Rev. A | Page 7 of 24
AD8375
Data Sheet
55
AV = +20dB
51
50
50
AV = +10dB
AV = 0dB
49
60
AV = 20dB
45
OIP3 (dBm)
48
OIP3 (dBm)
65
+25°C 20dB
–40°C 20dB
+85°C 20dB
+25°C 0dB
–40°C 0dB
+85°C 0dB
47
46
AV = –4dB
45
55
40
50
AV = 0dB
44
35
45
30
40
OIP3 (dBm)
52
43
42
50
70
90
110
130
150
FREQUENCY (MHz)
170
190
210
25
–3
35
–2
–1
0
1
2
3
4
06724-012
40
30
06724-009
41
5
POUT PER TONE (dBm)
Figure 10. Output Third-Order Intercept at Four Gains,
Output Level at 3 dBm/Tone
Figure 13. Output Third-Order Intercept vs. Power,
Frequency 140 MHz, Three Temperatures
52
–70
51
AV = +20dB
46MHz
70MHz
140MHz
200MHz
–75
50
49
–80
AV = +10dB
47
IMD3 (dBc)
OIP3 (dBm)
48
AV = 0dB
46
45
–85
–90
–95
44
AV = –4dB
–100
43
42
–105
–3
–2
1
2
0
POUT (dBm)
–1
4
3
5
6
70
–70
65
–75
60
–80
IMD3 (dBc)
55
+25°C
50
–40°C
+85°C
45
6
11
GAIN (dB)
1
16
Figure 14. Two-Tone Output IMD vs. Gain
at 46 MHz, 70 MHz, 140 MHz, and 200 MHz, Output Level at 3 dBm/Tone
Figure 11. Output Third-Order Intercept vs. Power
at Four Gains, Frequency 140 MHz
–85
+85°C
–90
–40°C
–95
–100
35
–105
30
40
60
80
100
120
140
FREQUENCY (MHz)
160
180
200
–110
40
60
80
100
120
140
FREQUENCY (MHz)
160
180
Figure 15. Two-Tone Output IMD vs. Frequency,
Three Temperatures, Output Level at 3 dBm/Tone
Figure 12. Output Third-Order Intercept vs. Frequency,
Three Temperatures, Output Level at 3 dBm/Tone
Rev. A | Page 8 of 24
200
06724-014
+25°C
40
06724-011
OIP3 (dBm)
–110
–4
06274-010
40
–4
06724-013
41
Data Sheet
AD8375
–75
–80
–95
–85
–100
–90
–105
–95
–110
–100
–115
40
60
80
100
120
140
FREQUENCY (MHz)
160
–105
200
180
–95
–105
–115
–125
–5
–100
–85
HD3 +20dB
HD3 +10dB
HD3 0dB
HD3 –4dB
–95
–100
–120
–105
–2
–2
–1
0
1
2
3
4
5
–1
0
1
POUT (dBm)
2
3
4
5
–110
25
20
15
46MHz
70MHz
140MHz
200MHz
10
5
0
–4
–2
0
2
4
6
8
10
GAIN (dB)
12
14
16
18
20
Figure 20. NF vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz
45
HD2 +25°C
HD3 +25°C
HD2 –40°C
HD3 –40°C
HD2 +85°C
HD3 +85°C
40
NOISE FIGURE (dB)
–85
–3
30
Figure 17. Harmonic Distortion vs. Power at Four Gain Codes,
Frequency 140 MHz
–80
–110
–4
35
–90
–115
–3
–105
POUT (dBm)
NOISE FIGURE (dB)
–80
–4
HD3 +25°C
–120
HARMONIC DISTORTION HD3 (dBc)
–95
–125
–5
–100
HD3 +85°C
Figure 19. Harmonic Distortion vs. Power, Frequency 140 MHz,
Three Temperatures
–70
–75
–110
–95
HD3 –40°C
–65
–90
–105
–90
–110
06724-016
–85
–90
–95
35
AV = –4dB
30
AV = 0dB
25
AV = +10dB
20
15
AV = +20dB
10
–100
–105
40
60
80
100
120
140
FREQUENCY (MHz)
160
180
200
0
0
Figure 18. Harmonic Distortion vs. Frequency, Three Temperatures,
VOUT = 2 V p-p
100
200
300
400 500 600 700
FREQUENCY (MHz)
Figure 21. NF vs. Frequency
Rev. A | Page 9 of 24
800
900
1000
06724-020
5
06274-017
HARMONIC DISTORTION HD2 AND HD3 (dBc)
HARMONIC DISTORTION HD2 (dBc)
–80
–85
HD2 –40°C
–60
HD2 +20dB
HD2 +10dB
HD2 0dB
HD2 –4dB
–80
HD2 +25°C
–100
Figure 16. Harmonic Distortion vs. Frequency at Four Gain Codes,
VOUT = 2 V p-p
–75
–75
HD2 +85°C
HARMONIC DISTORTION HD3 (dBc)
–90
06724-018
–90
–70
–70
06724-019
–85
–85
HARMONIC DISTORTION HD2 (dBc)
–80
–65
HARMONIC DISTORTION HD3 (dBc)
HD2 –4dB
HD2 0dB
HD2 +10dB
HD2 +20dB
HD3 –4dB
HD3 0dB
HD3 +10dB
HD3 +20dB
06724-015
HARMONIC DISTORTION HD2 (dBc)
–75
AD8375
Data Sheet
REF3 POSITION
–600mV/DIV
REF3 SCALE
500mV
0pF
10pF EACH SIDE
INPUT
2
R1
R3
M10.0ns 10.0GS/s IT 10.0ps/pt
A CH1
960mV
M2.5ns 20.0GS/s IT 10.0ps/pt
A CH4
28.0mV
REF3 500mV 2.5ns
Figure 22. Gain Step Time Domain Response
06724-024
CH1 500mV Ω CH2 500mV Ω
06724-021
1
Figure 25. Pulse Response to Capacitive Loading, Gain 20 dB
OUTPUT
REF1 POSITION
–1.02/DIV
REF1 SCALE
50mV
RISE (C2) 1.384ns
FALL(C2) 1.39ns
INPUT
2
2
REF1
CH2 500mV
REF1 50.0mV
Figure 23. ENBL Time Domain Response
M2.5ns 20.0GS/s IT 10.0ps/pt
A CH4
28.0mV
06724-023
R1
R3
R4
2.5ns
–610mV
0
180
–5
120
–10
60
–15
0
–20
–60
–25
–120
–30
10
Figure 24. Pulse Response to Capacitive Loading, Gain −4 dB
100
FREQUENCY (MHz)
Figure 27. S11 vs. Frequency
Rev. A | Page 10 of 24
–180
1000
06724-026
S11 MAG (dB)
10pF EACH SIDE
INPUT
REF1 2.0V
A CH2
Figure 26. Large Signal Pulse Response
REF1 POSITION
–420mV/DIV
REF1 SCALE
2V
0pF
M2.5ns 20Gsps
IT 2.5ps/pt
S11 PHASE (Degrees)
M20.0ns 10.0GS/s IT 20.0ps/pt
A CH1
960mV
06724-022
CH1 500mV Ω CH2 500mV Ω
06724-025
1
Data Sheet
AD8375
0
1.00E–09
9.00E–10
–20
8.00E–10
DELAY (Seconds)
S12 (dB)
–40
–60
–80
+20dB
+10dB
0dB
–4dB
7.00E–10
6.00E–10
5.00E–10
4.00E–10
3.00E–10
2.00E–10
–100
100
200
300
400 500 600 700
FREQUENCY (MHz)
800
900
1000
0.00E+00
0
100
200
300
400 500 600 700
FREQUENCY (MHz)
800
900
1000
Figure 30. Group Delay vs. Frequency at Gain
Figure 28. Reverse Isolation vs. Frequency
80
0
70
–20
CMRR (dB)
–60
50
40
30
–80
20
–100
–120
0
100
200
300
400 500 600 700
FREQUENCY (MHz)
800
900
1000
0
0
100
200
300
400 500 600 700
FREQUENCY (MHz)
800
900
1000
Figure 31. Common-Mode Rejection Ratio vs. Frequency
Figure 29. Off-State Isolation vs. Frequency
Rev. A | Page 11 of 24
06724-031
10
06724-028
ISOLATION (dB)
60
–40
06724-029
0
06724-027
1.00E–10
–120
AD8375
Data Sheet
CIRCUIT DESCRIPTION
BASIC STRUCTURE
The dependency of the gain on the load is due to the opencollector architecture of the output stage.
The AD8375 is a differential variable gain amplifier consisting
of a 150 Ω digitally controlled passive attenuator followed by a
highly linear transconductance amplifier.
The dc current to the outputs of the amplifier is supplied
through two external chokes. The inductance of the chokes and
the resistance of the load determine the low frequency pole of
the amplifier. The parasitic capacitance of the chokes adds to
the output capacitance of the part. This total capacitance in
parallel with the load resistance sets the high frequency pole of
the device. Generally, the larger the inductance of the choke, the
higher its parasitic capacitance. Therefore, the value and type of
the choke should be chosen keeping this trade-off in mind.
AD8375
ATTENUATOR
MUX BUFFERS
VIN+
VOUT+
gm CORE
AMP
VCOM
A0 TO A4
DIGITAL
SELECT
06724-032
VOUT–
VIN–
Figure 32. Simplified Schematic
Input System
The dc voltage level at the inputs of the AD8375 is set by an
internal voltage reference circuit to about 2 V. This reference is
accessible at VCOM and can be used to source or sink 100 μA.
For cases where a common-mode signal is applied to the inputs,
such as in a single-ended application, an external capacitor
between VCOM and ground is required. The capacitor improves
the linearity performance of the part in this mode. This capacitor
should be sized to provide a reactance of 10 Ω or less at the
lowest frequency of operation. If the applied common-mode
signal is dc, its amplitude should be limited to 0.25 V from
VCOM (VCOM ± 0.25 V).
The device can be powered down by pulling the PWUP pin
down to below 0.8 V. In the powered down mode, the total
current reduces to 3 mA (typical). The dc level at the inputs and
at VCOM remains at about 2 V, regardless of the state of the
PWUP pin.
Output Amplifier
The gain is based on a 150 Ω differential load and varies as RL is
changed per the following equations:
Voltage Gain = 20 × (log(RL/150) + 1)
For operation frequency of 15 MHz to 700 MHz driving a
150 Ω load, 1 μH chokes with SRF of 160 MHz or higher are
recommended (such as 0805LS-102XJBB from Coilcraft).
The supply current consists of about 50 mA through the VCC
pin and 80 mA through the two chokes combined. The latter
increases with temperature at about 2.5 mA per 10°C.
There are two output pins for each polarity and they are
oriented in an alternating fashion. When designing the board,
care should be taken to minimize the parasitic capacitance due
to the routing that connects the corresponding outputs together.
A good practice is to avoid any ground or power plane under
this routing region and under the chokes to minimize the
parasitic capacitance.
Gain Control
A 5-bit binary code changes the attenuator setting in 1 dB steps
such that the gain of the device changes from 20 dB (Code 0) to
−4 dB (Code 24 and higher).
The noise figure of the device is about 8 dB at maximum gain
setting and it increases as the gain is reduced. The increase in
noise figure is equal to the reduction in gain. The linearity of
the part measured at the output is first-order independent of
the gain setting. From 0 dB to 20 dB gain, OIP3 is approximately
50 dBm into 150 Ω load at 140 MHz (3 dBm per tone). At gain
settings below 0 dB, it drops to approximately 45 dBm.
and
Power Gain = 10 × (log(RL/150) + 2)
Rev. A | Page 12 of 24
Data Sheet
AD8375
APPLICATIONS
BASIC CONNECTIONS
+5V
VCM
Figure 35 shows the basic connections for operating the
AD8375. A voltage between 4.5 V and 5.5 V should be applied
to the supply pins. Each supply pin should be decoupled with at
least one low inductance, surface-mount ceramic capacitor of
0.1 μF placed as close as possible to the device.
0.1µF
150Ω
1µH
0.1µF
50Ω
AD8375
0.1µF
AC
1µH
0.1µF
0.1µF
150Ω
37.5Ω
The outputs of the AD8375 are open collectors that need to be
pulled up to the positive supply with 1 µH RF chokes. The
differential outputs are biased to the positive supply and require
ac coupling capacitors, preferably 0.1 µF. Similarly, the input
pins are at bias voltages of about 2 V above ground and should
be ac-coupled as well. The ac coupling capacitors and the RF
chokes are the principle limitations for operation at low
frequencies.
06724-035
5
A0 TO A4
Figure 33. Single-Ended-to-Differential Conversion
Using a single-ended input decreases the power gain by 3 dB
and limits distortion cancellation. Consequently, the secondorder distortion is degraded. The third-order distortion remains
low to 200 MHz, as shown in Figure 34.
To enable the AD8375, the PWUP pin must be pulled high.
Taking PWUP low puts the AD8375 in sleep mode, reducing
current consumption to 5 mA at ambient.
–60
–65
HARMONIC DISTORTION (dBc)
HD2
SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION
The AD8375 can be configured as a single-ended input to
differential output driver as shown in Figure 33. A 150 Ω
resistor in parallel with the input impedance of input pin
provides an impedance matching of 50 Ω. The voltage gain and
the bandwidth of this configuration, using a 150 Ω load,
remains the same as when using a differential input.
–70
–75
–80
–85
–90
HD3
–100
50
0
100
FREQUENCY (MHz)
150
Figure 34. Harmonic Distortion vs. Frequency of
Single-Ended-to-Differential Conversion
+VS
0.1µF
10µF
1µH
24
23
22
21
20
19
COMM VPOS COMM COMM COMM PWUP
0.1µF
BALANCED
AC
SOURCE
RS
2
VOUT– 18
2 VIN+
VOUT+ 17
3 VIN–
VOUT– 16
0.1µF
RL
1µH
AD8375
0.1µF
0.1µF
4 A4
VOUT+ 15
5 A3
COMM 14
6 A2
BALANCED
LOAD
VPOS 13
A1
7
A0
8
VPOS VPOS COMM VPOS
9
10
11
12
+VS
PARALLEL CONTROL INTERFACE
0.1µF
0.1µF
Figure 35. Basic Connections
Rev. A | Page 13 of 24
06724-034
RS
2
0.1µF
1 VCOM
200
06724-036
–95
AD8375
Data Sheet
BROADBAND OPERATION
For example, in the extreme case where the load is assumed to
be high impedance, RL = ∞, the equation for R1 reduces to R1 =
75 Ω. Using the equation for VR, the applied voltage should be
VR = 8 V. The measured single-tone low frequency harmonic
distortion for a 2 V p-p output using 75 Ω resistive pull-ups is
provided in Figure 37.
The AD8375 uses an open-collector output structure that
requires dc bias through an external bias network. Typically,
choke inductors are used to provide bias to the open-collector
outputs. Choke inductors work well at signal frequencies where
the impedance of the choke is substantially larger than the target
ac load impedance. In broadband applications, it may not be
possible to find large enough choke inductors that offer enough
reactance at the lowest frequency of interest while offering a
high enough self resonant frequency (SRF) to support the
maximum bandwidth available from the device. The circuit in
Figure 36 can be used when frequency response below 10 MHz
is desired. This circuit replaces the bias chokes with bias resistors.
The bias resistor has the disadvantage of a greater IR drop, and
requires a supply rail that is several volts above the local 5 V
supply used to power the device. Additionally, it is necessary
to account for the ac loading effect of the bias resistors when
designing the output interface. Whereas the gain of the AD8375
is load dependent, RL, in parallel with R1 + R2, should equal the
optimum 150 Ω target load impedance to provide the expected
ac performance depicted in the data sheet. Additionally, to
ensure good output balance and even-order distortion
performance, it is essential that R1 = R2.
SET TO
5V
R1
0.1µF
37.5Ω
0.1µF
VR
A0 TO A4
HARMONIC DISTORTION (dBc)
and
VR = R1 × 40 × 10 −3 + 5
15
1µH
0.1µF
ETC1-1-13
5V
37.5Ω
0.1µF
37.5Ω
AD8375
5
20
06724-038
10
FREQUENCY (MHz)
(2)
5V
50Ω
5
There are several options available to the designer when using
the AD8375. The open-collector output provides the capability
of driving a variety of loads. Figure 38 shows a simplified
wideband interface with the AD8375 driving a AD9445. The
AD9445 is a 14-bit 125 MSPS analog-to-digital converter with a
buffered wideband input, which presents a 2 kΩ differential
load impedance and requires a 2 V p-p differential input swing
to reach full scale.
(1)
R L − 150
0
The AD8375 is a high output linearity variable gain amplifier
that is optimized for ADC interfacing. The output IP3 and noise
floor essentially remain constant vs. the 24 dB available gain
range. This is a valuable feature in a variable gain receiver where
it is desirable to maintain a constant instantaneous dynamic
range as the receiver gain is modified. The output noise density
is typically around 20 nV/√Hz, which is comparable to 14-/16bit sensitivity limits. The two-tone IP3 performance of the
AD8375 is typically around 50 dBm. This results in SFDR levels
of better than 86 dB when driving the AD9445 up to 140 MHz.
Using the formula for R1 (Equation 1), the values of R1 = R2
that provide a total presented load impedance of 150 Ω can be
found. The required voltage applied to the bias resistors, VR,
can be found by using the VR formula (Equation 2).
75 × R L
–92
ADC INTERFACING
Figure 36. Single-Ended Broadband Operation with Resistive Pull-Ups
R1 =
HD3
–90
Figure 37. Harmonic Distortion vs. Frequency Using Resistive Pull-Ups
RL
R2
5
–88
–96
0.1µF
AD8375
–86
0.1µF
82Ω
1µH 0.1µF
L
(SERIES) 0.1µF
L
(SERIES) 0.1µF
33Ω
AD9445
33Ω
82Ω
A0 TO A4
Figure 38. Wideband ADC Interfacing Example Featuring the AD9445
Rev. A | Page 14 of 24
VIN+
14
14-BIT ADC
VIN–
06724-039
50Ω
HD2
–84
–94
VR
5V
0.1µF
ETC1-1-13
–82
06724-037
37.5Ω
–80
Data Sheet
AD8375
The addition of the series inductors L (series) in Figure 38
extends the bandwidth of the system and provides response
flatness. Using 100 nH inductors as L (series), the wideband
system response of Figure 40 is obtained. The wideband
frequency response is an advantage in broadband applications
such as predistortion receiver designs and instrumentation
applications. However, by designing for a wide analog input
frequency range, the cascaded SNR performance is somewhat
degraded due to high frequency noise aliasing into the wanted
Nyquist zone.
0
–1
–2
–3
–4
(dBFs)
For optimum performance, the AD8375 should be driven
differentially using an input balun or impedance transformer.
Figure 38 uses a wideband 1:1 transmission line balun followed
by two 37.5 Ω resistors in parallel with the 150 Ω input impedance of the AD8375 to provide a 50 Ω differential terminated
input impedance. This provides a wideband match to a 50 Ω
source. The open-collector outputs of the AD8375 are biased
through the two 1 μH inductors and are ac-coupled to the two
82 Ω load resistors. The 82 Ω load resistors in parallel with the
series-terminated ADC impedance yields the target 150 Ω
differential load impedance, which is recommended to provide
the specified gain accuracy of the device. The load resistors are
ac-coupled from the AD9445 to avoid common-mode dc
loading. The 33 Ω series resistors help to improve the isolation
between the AD8375 and any switching currents present at the
analog-to-digital sample and hold input circuitry.
1
0
SNR = 64.93dBc
SFDR = 86.37dBc
NOISE FLOOR = –108.1dB
FUND = –1.053dBFs
SECOND = –86.18dBc
THIRD = –86.22dBc
–10
–20
–30
–40
–5
–6
–7
–8
–50
FIRST POINT = –2.93dBFs
END POINT = –9.66dBFs
MID POINT = –2.33dBFs
MIN = –9.66dBFs
MAX = –1.91dBFs
–9
–10
20
–70
–80
3
2
–90
+
–100
4
5
–130
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz)
06724-040
–140
0
76
104
132 160 188 216
FREQUENCY (MHz)
244
272
300
Figure 40. Measured Frequency Response of Wideband ADC Interface
Depicted in Figure 38
6
–110
–120
–150
48
06724-041
(dBFS)
–60
Figure 39. Measured Single-Tone Performance of the
Circuit in Figure 38 for a 100 MHz Input Signal
The circuit depicted in Figure 38 provides variable gain,
isolation and source matching for the AD9445. Using this
circuit with the AD8375 in a gain of 20 dB (maximum gain) an
SFDR performance of 86 dBc is achieved at 100 MHz, as
indicated in Figure 39.
An alternative narrow-band approach is presented in Figure 41.
By designing a narrow band-pass antialiasing filter between the
AD8375 and the target ADC, the output noise of the AD8375
outside of the intended Nyquist zone can be attenuated, helping
to preserve the available SNR of the ADC. In general, the SNR
improves several dB when including a reasonable order antialiasing filter. In this example, a low loss 1:3 input transformer is used
to match the AD8375’s 150 Ω balanced input to a 50 Ω unbalanced source, resulting in minimum insertion loss at the input.
Rev. A | Page 15 of 24
AD8375
Data Sheet
at dc, which introduces a zero into the transfer function. In
addition, the ac coupling capacitors and the bias chokes
introduce additional zeros into the transfer function. The final
overall frequency response takes on a band-pass characteristic,
helping to reject noise outside of the intended Nyquist zone.
Table 5 provides initial suggestions for prototyping purposes.
Some empirical optimization may be needed to help compensate
for actual PCB parasitics.
Figure 41 is optimized for driving some of Analog Devices
popular unbuffered ADCs, such as the AD9246, AD9640,
and AD6655. Table 5 includes antialiasing filter component
recommendations for popular IF sampling center frequencies.
Inductor L5 works in parallel with the on-chip ADC input
capacitance and a portion of the capacitance presented by C4 to
form a resonant tank circuit. The resonant tank helps to ensure
the ADC input looks like a real resistance at the target center
frequency. Additionally, the L5 inductor shorts the ADC inputs
1µH
1nF
50Ω
1nF
AD8375
301Ω
1µH
5
1nF
1nF
L1
L3
C4
C2
L1
165Ω
CML
AD9246
AD9640
AD6655
L5
165Ω
L3
06724-042
1:3
A0 TO A4
Figure 41. Narrow-Band IF Sampling Solution for Unbuffered ADC Application
Table 5. Interface Filter Recommendations for Various IF Sampling Frequencies
Center Frequency
96 MHz
140 MHz
170 MHz
211 MHz
1 dB Bandwidth
27 MHz
30 MHz
32 MHz
32 MHz
L1
390 nH
330 nH
270 nH
220 nH
C2
5.6 pF
3.3 pF
2.7 pF
2.2 pF
Rev. A | Page 16 of 24
L3
390 nH
330 nH
270 nH
220 nH
C4
25 pF
20 pF
20 pF
18 pF
L5
100 nH
56 nH
39 nH
27 nH
Data Sheet
AD8375
LAYOUT CONSIDERATIONS
+9V
There are two output pins for each polarity, and they are
oriented in an alternating fashion. When designing the board,
care should be taken to minimize the parasitic capacitance due
to the routing that connects the corresponding outputs together.
A good practice is to avoid any ground or power plane under
this routing region and under the chokes to minimize the
parasitic capacitance.
96Ω
TC3-1T
0.1µF
0.1µF
330Ω
25Ω
50Ω
AD8375
T1
50Ω
96Ω
AC
0.1µF 330Ω
0.1µF
25Ω
06724-047
5
A0 TO A4
Figure 43. Test Circuit for Time Domain Measurements
CHARACTERIZATION TEST CIRCUITS
Differential-to-Differential Characterization
The S-parameter characterization for the AD8375 was
performed using a dedicated differential input to differential
output characterization board. Figure 44 shows the layout of
characterization board. The board was designed for optimum
impedance matching into a 75 Ω system. Because both the
input and output impedances of the AD8375 are 150 Ω
differentially, 75 Ω impedance runs were used to match 75 Ω
network analyzer port impedances. On-board 1 μH inductors
were used for output biasing, and the output board traces were
designed for minimum capacitance.
+5V
75Ω
75Ω TRACES
75Ω
75Ω TRACES
AD8375
0.1µF
AC
75Ω
0.1µF
5
A0 TO A4
Figure 44. Differential-to-Differential Characterization Board
Circuit Side Layout
Figure 42. Test Circuit for S-Parameters on Dedicated 75 Ω
Differential-to-Differential Board
+5V
TC3-1T
50Ω
AC
L1
1µH
C1
0.1µF
AD8375
T1
C2
0.1µF
5
L2
1µH
C3
0.1µF
R1
62Ω
R4
25Ω
ETC1-1-13
PAD LOSS = 11dB
C4
0.1µF
R2
62Ω
R3
25Ω
A0 TO A4
Figure 45. Test Circuit for Distortion, Gain, and Noise
Rev. A | Page 17 of 24
T2
50Ω
06724-043
AC
0.1µF
0.1µF
06724-046
75Ω
L2
1µH
06724-044
L1
1µH
AD8375
Data Sheet
EVALUATION BOARD
Figure 46 shows the schematic of the AD8375 evaluation board.
The silkscreen and layout of the component and circuit sides
are shown in Figure 47 through Figure 50. The board is powered
by a single supply in the 4.5 V to 5.5 V range. The power supply
is decoupled by 10 µF and 0.1 µF capacitors at each power supply
pin. Additional decoupling, in the form of a series resistor or
inductor at the supply pins, can also be added. Table 6 details
the various configuration options of the evaluation board.
The output pins of the AD8375 require supply biasing with
1 µH RF chokes. Both the input and output pins must be accoupled. These pins are converted to single-ended with a pair of
baluns (Mini-Circuits TC3-1T+ and M/A-COM ETC1-1-13).
The balun at the input, T1, is used to transform a 50 Ω source
impedance to the desired 150 Ω reference level. The output
balun, T3, and the matching components are configured to
provide a 150 Ω to 50 Ω impedance transformation with an
insertion loss of about 11 dB.
Rev. A | Page 18 of 24
INN
INP
R2
0Ω
R1
TC3-1T+
Figure 46. AD8375 Evaluation Board Schematic
Rev. A | Page 19 of 24
VPOS
C20
10µF
C60
0.1µF
T1
WA4
R72
R71
R70
C1
0.1µF
WA3
R10
C2
0Ω 0.1µF
R9
0Ω
WA2
C11
0.1µF
23
22
21
20
C5
19
WA1
WA0
VPOS 13
C14
0.1µF
VPOS
VPOS VPOS COMM VPOS
9
10
11
12
6 A2
A0
8
COMM 14
5 A3
VOUT– 16
VOUT+ 15
AD8375
VOUT+ 17
VOUT– 18
4 A4
A1
7
3 VIN–
2 VIN+
1 VCOM
C63
0.1µF
R13
0Ω
COMM VPOS COMM COMM COMM PWUP
24
VPOS
PU
C13
0.1µF
L2
1µH
R16
0Ω
VXA
R19
C7
0.1µF 61.9Ω
R23
30.9Ω
R24
R25
30.9Ω
VPOS
R20
61.9Ω
C64
0.1µF
C8
0.1µF
L1
1µH
R15
0Ω
R91
0Ω
C62
0.1µF
R62
T3
ETC1-1-13
R29
VPOS
R30
0Ω
OUTP
OUTN
06724-045
VPOS
Data Sheet
AD8375
AD8375
Data Sheet
Table 6. Evaluation Board Configuration Options
Components
C13, C14, C20,
C63, C64, R91
Function
Power Supply Decoupling. Nominal supply decoupling consists a 10 µF
capacitor to ground followed by 0.1 µF capacitors to ground positioned as
close to the device as possible.
T1, C1, C2, C60,
R1, R2, R9, R10,
R70 to R72
Input Interface. T1 is a 3:1 impedance ratio balun to transform a 50 Ω singleended input into a 150 Ω balanced differential signal. R2 grounds one side of
the differential drive interface for single-ended applications. R9, R10, and R70
to R72 are provided for generic placement of matching components. C1 and
C2 are dc blocks.
Output Interface. C7 and C8 are dc blocks. L1 and L2 provide dc biases for the
output. R19, R20, and R23 to R25 are provided for generic placement of
matching components. The evaluation board is configured to provide a 150 Ω
to 50 Ω impedance transformation with an insertion loss of about 11 dB. T3 is a
1:1 impedance ratio balun to transform the balanced differential signal to a
single-ended signal. R30 grounds one side of the differential output interface
for single-ended applications.
T3, C7, C8, C62
L1, L2, R15, R16,
R19, R20, R23 to R25,
R29, R30, R62
PU, R13, C5
WA0 to WA4
C11
Enable Interface. The AD8375 is enabled by applying a logic high voltage to
the PWUP pin. The device is disabled when the PU switch is set in the position
closest to the PU label, connecting the PWUP pin to ground. The device is
enabled when the PU switch is set in the opposite position, connecting the
PWUP to VPOS.
Parallel Interface Control. Used to hardwire A0 through A4 to the desired gain.
The bank of switches, WA4 to WA0, set the binary gain code. WA4 represents
the LSB. WA0 represents the MSB.
Voltage Reference. Input common-mode voltage ac-coupled to ground by
0.1 µF capacitor, C11.
Rev. A | Page 20 of 24
Default Conditions
C20 = 10 µF (size 3528)
C13, C14, C63, C64 = 0.1 µF
(size 0402)
R91 = 0 Ω (size 0402)
T1 = TC3-1+ (Mini-Circuits)
C1, C2, C60 = 0.1 µF (size 0402)
R2, R9, R10 = 0 Ω (size 0402)
R1, R70 to R72 = open (size 0402)
T3 = ETC1-1-13 (M/A-COM)
C7, C8, C62 = 0.1 µF (size 0402)
L1, L2 = 1 µH (size 0805)
R19, R20 = 61.9 Ω (size 0402)
R23, R25 = 30.9 Ω (size 0402)
R15, R16 = 0 Ω (size 0603)
R30 = 0 Ω (size 0402)
R24, R29, R62 = open (size 0402)
PU = installed
R13 = 0 Ω (size 0603)
C5 = open (size 0603)
WA0 to WA4 = installed
C11 = 0.1 µF (size 0402)
AD8375
06724-048
06724-050
Data Sheet
06724-049
06724-051
Figure 49. Component Side Layout
Figure 47. Component Side Silkscreen
Figure 50. Circuit Side Layout
Figure 48. Circuit Side Silkscreen
Rev. A | Page 21 of 24
AD8375
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.60 MAX
2.50 REF
0.60 MAX
3.75 BSC
SQ
1
0.50
BSC
2.25
2.10 SQ
1.95
EXPOSED
PAD
6
13
TOP VIEW
1.00
0.85
0.80
12° MAX
0.80 MAX
0.65 TYP
0.30
0.23
0.18
SEATING
PLANE
0.50
0.40
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
7
12
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
04-09-2012-A
PIN 1
INDICATOR
PIN 1
INDICATOR
24
19
18
Figure 51. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD8375ACPZ-WP
AD8375ACPZ-R7
AD8375-EVALZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Waffle Pack
24-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel
Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 22 of 24
Package Option
CP-24-1
CP-24-1
Data Sheet
AD8375
NOTES
Rev. A | Page 23 of 24
AD8375
Data Sheet
NOTES
©2007–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06724-0-10/12(A)
Rev. A | Page 24 of 24