An integrated organic circuit array for flexible large-area
temperature sensing
The MIT Faculty has made this article openly available. Please share
how this access benefits you. Your story matters.
Citation
He, David Da et al. “An Integrated Organic Circuit Array for
Flexible Large-area Temperature Sensing.” IEEE International
Solid-State Circuits Conference, Digest of Technical Papers
(ISSCC), IEEE, 2010. 142–143. Web. ©2010 IEEE.
As Published
http://dx.doi.org/10.1109/ISSCC.2010.5434013
Publisher
Institute of Electrical and Electronics Engineers
Version
Final published version
Accessed
Thu May 26 06:42:09 EDT 2016
Citable Link
http://hdl.handle.net/1721.1/72077
Terms of Use
Article is made available in accordance with the publisher's policy
and may be subject to US copyright law. Please refer to the
publisher's site for terms of use.
Detailed Terms
ISSCC 2010 / SESSION 7 / DESIGNING IN EMERGING TECHNOLOGIES / 7.5
7.5
An Integrated Organic Circuit Array for Flexible
Large-Area Temperature Sensing
David Da He, Ivan A. Nausieda, Kyungbum Kevin Ryu,
Akintunde I. Akinwande, Vladimir Bulovic, Charles G. Sodini
Massachusetts Institute of Technology, Cambridge, MA
Traditionally, several technologies have been used for temperature sensing,
including integrated silicon ΔVBE and ΔVt circuits, resistance temperature detectors, and thermocouples [1]. The organic thin-film transistor (OTFT) is a new
technology suitable for temperature sensing because of two key advantages.
First, OTFTs have the ability to be fabricated on flexible and large-area substrates
[2]. This ability allows an OTFT temperature sensor to be used for applications
such as electronic skin, biomedical thermal imaging, and structural temperature
monitoring [2]. Second, the OTFT’s semiconductor trap states make OTFTs highly responsive to temperature. This paper presents the first integrated OTFT temperature sensing circuit array. The array is compatible with flexible and largearea substrates, and its outputs are 22 times more responsive than the MOSFET
implementation while dissipating 90nW of power per cell.
The pentacene-based OTFTs are fabricated using an integrated photolithographic process that is kept below 95°C to ensure compatibility with large-area and
flexible substrates [3]. Figure 7.5.1 shows the measured OTFT transfer characteristics as die temperature is increased from -20°C to 60°C. In comparison to
the OTFT, Fig. 7.5.2 shows simulated BSIM3 silicon pMOSFET transfer characteristics versus temperature. Two important differences are observed between
the OTFT and the MOSFET. First, the OTFT’s current increases with temperature
in both subthreshold and above-threshold regimes, whereas the MOSFET’s
above-threshold current decreases with temperature. Second, when biased at a
constant ID, the OTFT’s VSG is approximately 20 times more responsive to temperature than the MOSFET’s VSG. Both differences are due to the fact that pentacene is a disordered semiconductor with substantial trap states [4].
A temperature sensing circuit that takes advantage of OTFT’s responsiveness to
temperature is shown in Fig. 7.5.3. OTFTs M3, M4, and M5 form two current mirrors that bias the two branches at different ID’s. Diode-connected and identically
sized M1 and M2 act as temperature sensing transistors whose VSG1 and VSG2 are
functions of temperature. The differential output VO=VSG1–VSG2 performs curvature cancellation and removes any common-mode Vt drifts of M1 and M2.
If M1 and M2 are subthreshold MOSFETs, then this circuit is analogous to a ΔVBE
circuit. From Fig. 7.5.3’s MOSFET implementation, one can graphically see that
VSG2 decreases faster than VSG1 over the same temperature rise because the
transfer curves converge at a higher ID. Therefore, the circuit’s output
VO=VSG1–VSG2 increases with temperature. On the other hand, Fig. 7.5.3’s OTFT
implementation shows that VSG2 decreases slower than VSG1 over the same temperature rise because the transfer curves diverge at a higher ID. As a result, the
OTFT circuit’s output VO=VSG1–VSG2 decreases with temperature.
The OTFT temperature sensing circuit is fabricated with the device dimensions
shown in Fig. 7.5.4 and occupies an area of 1mm×1mm. Wide transistors are
used in order to lower the VDD voltage and to increase the temperature sensing
area. The circuit uses a 5V voltage supply and a 3nA current sink from an Agilent
4156C. At each temperature, 240 samples of VO are taken at two samples/second and the standard deviation of the samples is 1.9mV. The averaged VO at each
temperature is plotted in Figure 7.5.4. The temperature responsivity (|dVO/dT|) is
6.3mV/°C and the temperature sensitivity is 2.5×106ppm at 25°C. The maximum
power dissipation of the circuit is 170nW at 50°C. In the unit of temperature, the
standard deviation of output samples corresponds to 0.30°C. The output is highly linear as shown by the best-fit line with R2=99.7%. The maximum and average
deviations of data from the best-fit line are 0.99% and 0.56%, respectively.
Another key advantage of the OTFT temperature sensing circuit is its ability to be
fabricated on large-area substrates. We explore this application by scaling the
circuit to a 3×3 array consisting of 1mm2 cells. The circuit schematic is shown
in Fig. 7.5.5. The circuit uses a 5V voltage supply and a 2nA current sink. The
averaged VO’s at each temperature for the nine cells are plotted in Fig. 7.5.5. The
average temperature responsivity is 6.8mV/°C and the maximum power dissipation of the array is 810nW at 50°C.
In an array format, variations due to cell-to-cell mismatches in device parameters such as Vt and carrier mobility become apparent. As shown in Fig. 7.5.5,
responsivities vary by 19% and 0°C VO voltages vary by 8% of their average values. However, an important observation is that R2 values to best-fit lines vary by
only 0.059% from an average of 99.8%. Therefore, the array’s VO linearity is
unaffected by cell-to-cell variations. Linearity is crucial to the array application
because it enables simple two-point calibrations, which can remove the effects
of responsivity and offset voltage variations. This is especially relevant to largearea applications where device mismatches are anticipated across the geometry.
In Fig. 7.5.5, if two-point calibration is used for each cell based on -10°C and
50°C data points, the average error between linearly interpolated VO and measured VO is only 1.1% with a standard deviation of 0.58%.
The linear temperature response of the circuit is a result of curvature cancellation between the differential outputs. This curvature cancellation is possible at a
range of ISINK and VDD bias settings. In Fig. 7.5.6 (left), VO is plotted versus temperature as ISINK is swept from 0.5nA to 10nA. The R2 value remains above 98%
for ISINK=0.5nA to 4.5nA. Linearity worsens at high ISINK currents because the high
VSG’s of M1 and M2 cause the current mirrors to enter the triode regime. In Fig.
7.5.6 (right), VO is plotted versus temperature as VDD is swept from 2V to 10V.
Transistors M3 and M4 are in the saturation regime as long as VDD stays above
3V, where the R2 value remains above 98% and is nominally independent of VDD
because the circuit’s operating point is set by ISINK.
In conclusion, this work has demonstrated the first integrated OTFT temperature
sensing circuit array compatible with large-area and flexible substrates (die
photo Fig. 7.5.7). The circuit outputs an average responsivity of 6.8mV/°C, which
is 22 times more responsive than the MOSFET implementation while dissipating
90nW of power per cell from a 5V supply. Output linearity is guaranteed across
the array as long as the current mirrors stay in the saturation regime. The linearity enables two-point calibrations, which remove the effects of cell-to-cell variations and make large-area implementations feasible.
Acknowledgements:
The authors would like to thank Peter Holloway of National Semiconductor for
his inputs. The devices were fabricated at Microsystems Technology Labs at MIT.
This work was funded in part by the FCRP Focus Center for Circuit & System
Solutions (C2S2) under contract 2003-CT-888, Hewlett Packard, and the
Canadian NSERC Scholarship.
References:
[1] D. Hilbiber, “A New Semiconductor Voltage Standard,” ISSCC Dig. Tech.
Papers, pp. 32-33, Feb. 1964.
[2] T. Someya, H. Kawaguchi, T. Sakurai, “Cut-and-paste Organic FET
Customized ICs for Application to Artificial Skin,” ISSCC Dig. Tech. Papers, vol,
pp. 288-289, Feb. 2004.
[3] I. Kymissis, A.I. Akinwande, V. Bulovic´, “A Lithographic Process for
Integrated Organic Field-Effect Transistors,” IEEE J. of Disp. Tech., vol. 1, pp. 913, Jan. 2005.
[4] E. Cantatore, E.J. Meijer, “Transistor Operation and Circuit Performance in
Organic Electronics,” Proc. 29th European Solid-State Circuits Conference, pp.
29-36, Sept. 2003.
As previously mentioned, the OTFT circuit would be a ΔVBE circuit if designed
using MOSFETs. The MOSFET circuit’s output responsivity is (nk/q)×ln(I1/I2)
according to [1], where n is the ideality factor, k is Boltzmann’s constant, and q
is the elementary charge. With n=1.5 and I1/I2=10, a ΔVBE circuit’s responsivity is
0.30mV/°C. Using the same current ratio of 10, the OTFT circuit’s responsivity of
6.3mV/°C is 21 times greater.
142
• 2010 IEEE International Solid-State Circuits Conference
978-1-4244-6034-2/10/$26.00 ©2010 IEEE
ISSCC 2010 / February 9, 2010 / 10:30 AM
7
Figure 7.5.1: The OTFT’s device cross-section and measured transfer characteristics versus temperature (W/L=1,000µm/5µm).
Figure 7.5.2: The BSIM3 pMOSFET’s simulated transfer characteristics versus
temperature (W/L=10µm/0.18µm).
Figure 7.5.3: The temperature sensing circuit with its operating principles
stylized for MOSFET and OTFT.
Figure 7.5.4: The OTFT temperature sensing circuit schematic and averaged
VO versus temperature with best-fit line.
Figure 7.5.5: The OTFT temperature sensing circuit array’s schematic, measured outputs, and output variations.
Figure 7.5.6: The dependence of output linearity on ISINK (left) and VDD (right)
with R2 values (bottom).
DIGEST OF TECHNICAL PAPERS •
143
ISSCC 2010 PAPER CONTINUATIONS
Figure 7.5.7: Die photo of the 3×3 OTFT temperature sensing circuit array.
• 2010 IEEE International Solid-State Circuits Conference
978-1-4244-6034-2/10/$26.00 ©2010 IEEE