Computer Engineering @
EECS Snapshot
Degree Programs:
B.S., M.S. and Ph. D. in Computer Engineering
Some Statistics:
4 primary faculty
54 Undergraduate students (Spring ‘11)
37 Graduate students (20 Ph. D. and 17 M.S.,
Spring ‘11)
Special Programs:
Cooperative Education Program in Computer
Engineering majors
Integrated B.S./M.S. Program
Master in Engineering (M.Eng.)
Research Thrusts:
Reconfigurable and Evolvable Hardware System
Soft Errors & Reliability for Memories & Logic
Embedded Systems for RFID
Modeling and Verification
Complementary Nano-Metallic Switches
Low Power and Robust Electronics
Nanocomputing
Implantable Systems and Wireless Health
Hardware Security
VLSI Architecture Design for Error-correcting
Codes, Cryptography and Digital Signal Processing
Employers (sample):
Qualcomm, Broadcom, Marvell, LSI, Cisco,
Seagate, IBM, Hewlett-Packard, Intel, AMD,
Synopsys, Cadence, Mentor Graphics, NVidia,
Texas Instruments, Analog Devices, National
Semiconductor, Xilinx, Altera, Samsung Electronics, Infineon, General Electric, Motorola,
EMC, Nokia, Apple, Google, Microsoft.
Student Organizations
IEEE (Institute of Electrical and Electronics
Engineers) is the world's leading professional
association for the advancement of technology.
The student chapter at
CWRU creates opportunities for you to interact with
the CWRU faculty and the
industry. Information sessions are held to introduce specific fields of
Electrical Engineering.
VLSI Design Lab
This lab has been supported by the Semiconductor Research Corporation, NSF, NASA,
Synopsys and Sun Microsystems.
This lab has a number of advanced UNIX
workstations
that run commercial CAD
software tools
for VLSI design and is currently used to
develop design
and testing
techniques for embedded system-on-chip.
Computer
Engineering
@
EECS
Embedded Systems Lab
The Embedded Systems Laboratory is equipped
with several Sun Blade Workstations running
Solaris and Intel PCs running Linux.
This lab has been recently equipped with advanced FPGA Virtex II prototype boards from
Xilinx, including about 100 Xilinx Virtex II
FPGAs and Xilinx CAD tools for development
work.
A grant-in-aid from Synopsys has provided the
Synopsys commercial CAD tools for software
development and simulation.
This Lab is also equipped with NIOS FPGA
boards from Altera, including software tools.
Chair: eecs-chair@case.edu
Office: 321 Glennan Building
Phone: 216-368-2802
Fax: 216-368-6888
Web: eecs.case.edu
The educational mission of the Computer Engineering program is to graduate students who have
fundamental technical knowledge of their profession and the requisite technical breadth and communications skills to become leaders in creating
the new techniques and technologies which will
advance the general field of Computer Engineering.
The Bachelor of Science program in Computer
Engineering is designed to give a student a strong
background in the fundamentals of computer engineering. A graduate of this program will be able
to use these fundamentals to analyze and evaluate
computer systems, both hardware and software. A
Computer Engineering graduate would also be
able to design and implement computer systems,
both hardware and software, which are state of
the art solutions to a variety of computing problems. This includes systems which have both a
hardware and a software component, whose design requires a well defined interface between the
two, and the evaluation of the associated tradeoffs.
The Computer Engineering division within EECS
at CWRU is unique. The division is small enough
that each student is able to receive personal attention from faculty, yet large enough to support a
diverse student population and a large number of
intellectually stimulating research programs for
students to participate in. Through internships and
co-ops, you will have the opportunity to apply
your knowledge to problems in the real world.
Graduating with a Computer Engineering degree
from Case equips you with the skills you need to
embark on challenging, high-tech careers; as entrepreneurs or researchers in industry or academia.
We hope you will choose to join us!
Some Research Projects
Reconfigurable and Evolvable Hardware System: Evolvable hardware is a new field about the
use of evolutionary
algorithms
to create
specialized
electronics
without
manual
engineering. It
brings together reconfigurable hardware, artificial intelligence, fault tolerance and autonomous systems.
The goal of our research is to design, simulate
and prototype advanced reconfigurable and
evolvable hardware for remote applications.
Soft Errors and Reliability for Memories and
Logic: Our research targets at on-line detection
and correction of soft errors in memories, and
reliability analysis in CMOS logic, including
hardening techniques from soft errors.
Nano-Metallic Switch: This research uses complementary nano-metallic switches (NEMS) and
memory devices to implement computing devices, such as gates, logics, memories. The key features include low contact resistance and low RCtime constant. These switches can withstand billions of switching cycles. Appropriate refractory
metals can be used for very high temperature operations.
Some Research Projects
Low Power and Robust Electronics: Power and
robustness of operation have emerged as two major concerns for digital design with nanoscaled
CMOS. Low
power design
techniques
typically impose contradictory design
requirements
with respect to
robustness of a
design. Our research targets developing design
methodology for low power and variation tolerance, while minimizing the design overhead.
Hardware Security: Hardware Intellectual Property (IP) piracy and reverse engineering efforts
have emerged as
major concerns for
IP vendors and
design houses. It is
critical to develop
low-cost design
techniques for
preventing IP infringement at different stages of
IP life-cycle. We are presently investigating
netlist and register transfer level design solutions
for hardware IP protection. Another major security concern for hardware is malicious alteration of
designs in an untrusted foundry.
VLSI Architecture Design for Advanced Error
-Correcting Codes: Error-correcting codes are
playing more and more important roles in digital
communication and storage systems. The everincreasing demand for reliability requires codes
with higher error-correcting capability. On the
other hand, advanced error-correcting codes involve very complicated mathematical computations. Mapping them directly to hardware implementations would usually lead to overwhelming
complexity. The goal of our research is to apply
integrated algorithmic and architectural optimizations to develop high-speed, small-area and/or
low-power practical hardware implementations
for those advanced algorithms.