Low Voltage, 400 MHz, Quad 2:1
Mux with 3 ns Switching Time
ADG774A
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Bandwidth: >400 MHz
Low insertion loss and on resistance: 2.2 Ω typical
On resistance flatness: 0.3 Ω typical
Single 3 V/5 V supply operation
Very low distortion: <0.3%
Low quiescent supply current: 1 nA typical
Fast switching times
tON = 6 ns
tOFF = 3 ns
TTL-/CMOS-compatible
Pb-free packages
16-lead QSSOP
16-lead 3 mm × 3 mm body LFCSP
ADG774A
S1A
D1
S1B
S2A
D2
S2B
S3A
D3
S3B
S4A
D4
S4B
EN
IN
02373-001
1 OF 2
DECODER
Figure 1.
GENERAL DESCRIPTION
The ADG774A is a monolithic CMOS device comprising four
2:1 multiplexer/demultiplexers with high impedance outputs.
The CMOS process provides low power dissipation yet offers
high switching speed and low on resistance. The on resistance
variation is typically less than 0.5 Ω over the input signal range.
The bandwidth of the ADG774A is typically 400 MHz and this,
coupled with low distortion (typically 0.3%), makes the part
suitable for switching of high speed data signals.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion. CMOS
construction ensures ultralow power dissipation.
The ADG774A operates from a single 3.3 V/5 V supply and is
TTL logic-compatible. The control logic for each switch is
shown in the truth table (see Table 5).
Rev. C
These switches conduct equally well in both directions when
on. In the off condition, signal levels up to the supplies are
blocked. The ADG774A switches exhibit break-before-make
switching action.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
Wide bandwidth data rates of >400 MHz.
Ultralow power dissipation.
Low leakage over temperature.
Break-before-make switching prevents channel shorting
when the switches are configured as a multiplexer.
Crosstalk is typically −70 dB @ 10 MHz.
Off isolation is typically −65 dB @ 10 MHz.
Available in compact 3 mm × 3 mm LFCSP.
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Technical Support
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ADG774A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Functional Block Diagram .............................................................. 1
Pin Configurations and Function Descriptions ............................6
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................7
Product Highlights ........................................................................... 1
Test Circuits ........................................................................................9
Revision History ............................................................................... 2
Terminology .................................................................................... 11
Specifications..................................................................................... 3
Application Circuits ....................................................................... 12
Single Supply ................................................................................. 3
Outline Dimensions ....................................................................... 13
Absolute Maximum Ratings............................................................ 5
Ordering Guide .......................................................................... 13
REVISION HISTORY
4/16—Rev. B to Rev. C
Changed CP-16-3 to CP-16-27 .................................... Throughout
Changes to Figure 3 and Table 4 ..................................................... 6
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 13
8/06—Rev. A to Rev. B
Updated Format .................................................................. Universal
Added LFCSP Model.......................................................... Universal
Added Lead-Free Models .................................................. Universal
Changes to Table 3 ............................................................................ 5
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 13
4/03—Rev. 0 to Rev. A
Changes to TPCs 9–11 ..................................................................... 5
Updated Outline Dimensions ......................................................... 8
7/01—Revision 0: Initial Version
Rev. C | Page 2 of 14
Data Sheet
ADG774A
SPECIFICATIONS
SINGLE SUPPLY
VDD = 5 V ± 10%, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.1
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels, ∆RON
25°C
B Version
TMIN to TMAX
0 to 2.5
2.2
3.5
0.15
4
0.5
On Resistance Flatness, RFLAT(ON)
0.3
0.6
LEAKAGE CURRENTS
Source Off Leakage, IS (OFF)
Drain Off Leakage, ID (OFF)
Channel On Leakage, ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
±0.001
±0.1
±0.001
±0.1
±0.001
±0.1
tOFF, tOFF (EN)
Break-Before-Make Time Delay, tD
Off Isolation
Channel-to-Channel Crosstalk
Bandwidth −3 dB
Distortion
Charge Injection
CS (OFF)
CD (OFF)
CD, CS (ON)
POWER REQUIREMENTS
VD = 0 V to 1 V, IS = −10 mA
VD = 0 V to 1 V, IS = −10 mA
±0.25
2.4
0.8
V min
V max
μA typ
μA max
pF typ
VIN = VINL or VINH
±0.1
3
6
12
3
6
3
1
−65
−70
400
0.3
6
5
7.5
12
ns typ
ns max
ns typ
ns max
ns typ
ns min
dB typ
dB typ
MHz typ
% typ
pC typ
pF typ
pF typ
pF typ
CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 22
±0.25
1
0.001
2
VD = 0 V to 1 V, IS = −10 mA
VD = 3 V/1 V, VS = 1 V/3 V, see Figure 17
VD = 3 V/1 V, VS = 1 V/3 V, see Figure 17
VD = VS = 3 V/1 V, see Figure 18
CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 22
CL = 35 pF, RL = 50 Ω, VS1 = VS2 = 2 V, see Figure 23
f = 10 MHz, RL = 50 Ω, see Figure 20
f = 10 MHz, RL = 50 Ω, see Figure 21
RL = 50 Ω, see Figure 19
RL = 100 Ω
CL = 1 nF, see Figure 24, VS = 0 V
VDD = 5.5 V
Digital inputs = 0 V or VDD
IDD
1
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
nA typ
nA max
nA typ
nA max
nA typ
nA max
±0.25
0.001
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tON, tON (EN)
Unit
μA max
μA typ
Temperature range for B version is −40°C to +85°C.
Guaranteed by design, not subject to production test.
Rev. C | Page 3 of 14
ADG774A
Data Sheet
VDD = 3 V ± 10%, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels, ∆RON
25°C
B Version
TMIN to TMAX
0 to 1.5
4
6
0.15
7
0.5
On Resistance Flatness, RFLAT(ON)
1.5
3
LEAKAGE CURRENTS
Source Off Leakage, IS (OFF)
Drain Off Leakage, ID (OFF)
Channel On Leakage, ID, IS(ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
±0.001
±0.1
±0.001
±0.1
±0.001
±0.1
tOFF, tOFF (EN)
Break-Before-Make Time Delay, tD
Off Isolation
Channel-to-Channel Crosstalk
Bandwidth −3 dB
Distortion
Charge Injection
CS (OFF)
CD (OFF)
CD, CS (ON)
POWER REQUIREMENTS
VD = 0 V to 1 V, IS = −10 mA
VD = 0 V to 1 V, IS = −10 mA
±0.25
2.0
0.4
V min
V max
μA typ
μA max
pF typ
VIN = VINL or VINH
±0.1
3
7
14
4
8
3
1
−65
−70
400
1.5
4
5
7.5
12
ns typ
ns max
ns typ
ns max
ns typ
ns min
dB typ
dB typ
MHz typ
% typ
pC typ
pF typ
pF typ
pF typ
CL = 35 pF, RL = 50 Ω, VS = 1.5 V, see Figure 22
±0.25
1
0.001
2
VD = 0 V to 1 V; IS = −10 mA
VD = 2 V/1 V, VS = 1 V/2 V, see Figure 17
VD = 2 V/1 V, VS = 1 V/2 V, see Figure 17
VD = VS = 2 V/1 V, see Figure 18
CL = 35 pF, RL = 50 Ω, VS = 1.5 V, see Figure 22
CL = 35 pF, RL = 50 Ω, VS1 = VS2 = 1.5 V, see Figure 23
f = 10 MHz, RL = 50 Ω
f = 10 MHz, RL = 50 Ω, see Figure 21
RL = 50 Ω, see Figure 19
RL = 100 Ω
CL = 1 nF, see Figure 24, VS = 0 V
VDD = 3.3 V
Digital inputs = 0 V or VDD
IDD
1
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
nA typ
nA max
nA typ
nA max
nA typ
nA max
±0.25
0.001
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tON, tON (EN)
Unit
μA max
μA typ
Temperature range for B version is −40°C to +85°C.
Guaranteed by design, not subject to production test.
Rev. C | Page 4 of 14
Data Sheet
ADG774A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameters
VDD to GND
Analog, Digital Inputs1
Continuous Current, S or D
Peak Current, S or D
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
Thermal Impedance, θJA
16-Lead QSSOP
16-Lead LFCSP (3 mm × 3 mm)
Lead Temperature Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Reflow Soldering (Pb-free)
Peak Temperature
Time at Peak Temperature
Rating
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V or 30 mA,
whichever occurs first
100 mA
300 mA (pulsed at 1 ms,
10% duty cycle max)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
105.44°C/W2
48.7°C/W2
215°C
220°C
260°C (+0°C/–5°C)
10 sec to 40 sec
1
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
2
Measured with the device soldered on a four-layer board.
Rev. C | Page 5 of 14
ADG774A
Data Sheet
13 S4B
4
5
S2B
6
11 S3A
D2
7
10 S3B
GND
8
12 D4
D3
ADG774A
11 S4B
S2A 3
TOP VIEW
(Not to Scale)
10 D4
9
D2 5
9
12 S4A
D1 2
S2B 4
02373-002
ADG774A
D1
S2A
TOP VIEW
(Not to Scale)
S1B 1
S3A
NOTES
1. THE EXPOSED PAD MUST BE
TIED TO GND.
Figure 2. QSOP Pin Configuration
02373-028
14 S4A
13 EN
3
14 VDD
S1B
D3 7
S1A
S3B 8
16 VDD
15 EN
16 S1A
1
2
GND 6
IN
15 IN
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
QSOP
LFCSP
1
15
2
16
3
1
4
2
5
3
6
4
7
5
8
6
9
7
10
8
11
9
12
10
13
11
14
12
15
13
16
14
Not applicable 17
Mnemonic
IN
S1A
S1B
D1
S2A
S2B
D2
GND
D3
S3B
S3A
D4
S4B
S4A
EN
VDD
EPAD
Function
Logic Control Input.
Source Terminal 1A. May be an input or output.
Source Terminal 1B May be an input or output.
Drain Terminal D1. May be an input or output.
Source Terminal 2A. May be an input or output.
Source Terminal 2B. May be an input or output.
Drain Terminal D2. May be an input or output.
Ground (0 V) Reference.
Drain Terminal D3. May be an input or output.
Source Terminal 3B. May be an input or output.
Source Terminal 3A. May be an input or output.
Drain Terminal D4. May be an input or output.
Source Terminal 4B. May be an input or output.
Source Terminal 4A. May be an input or output.
Logic Control Input. When high, all switches are disabled.
Most Positive Power Supply Potential.
Exposed Pad. The exposed pad must be tied to GND.
Table 5. Truth Table
EN
IN
D1
D2
D3
D4
Function
1
0
0
X
0
1
Hi-Z
S1A
S1B
Hi-Z
S2A
S2B
Hi-Z
S3A
S3B
Hi-Z
S4A
S4B
DISABLE
IN = 0
IN = 1
Rev. C | Page 6 of 14
Data Sheet
ADG774A
TYPICAL PERFORMANCE CHARACTERISTICS
20
20
VDD = 3V
TA = 25°C
16
15
12
RON (Ω)
RON (Ω)
VDD = 5.0V
VDD = 4.5V
10
8
+85°C
+25°C
5
VDD = 5.5V
4
0
1
2
3
4
5
VS/VD (V)
0
1.5
2.0
2.5
3.0
0.025
VDD = 5.0V
0.020 VSS = 0V
TEMP = 25°C
VD = VDD – VS
0.015
TA = 25°C
16
0.010
CURRENT (nA)
VDD = 3.0V
12
VDD = 2.7V
ID (OFF)
0.005
0
–0.005
IS (OFF)
–0.010
4
IS, ID (ON)
–0.015
VDD = 3.3V
0.5
1.0
1.5
2.0
2.5
3.0
VS/VD (V)
–0.025
Figure 5. On Resistance as a Function of Drain (VD) or Source (VS)
Voltage for VDD = 3 V ± 10%
20
VS
0
1
2
4
3
VS/VD (V)
02373-007
0
–0.020
02373-004
0
1.0
Figure 7. On Resistance as a Function of Drain (VD) or Source (VS) Voltage for
Different Temperatures with 3 V Single Supplies
20
RON (Ω)
0.5
VS/VD (V)
Figure 4. On Resistance as a Function of Drain (VD) or Source (VS) Voltage for
VDD = 5 V ± 10%
8
0
02373-003
0
02373-006
–40°C
Figure 8. Leakage Current as a Function of Drain (VD) or Source (VS) Voltage
for VDD = 5 V
0.025
VDD = 5V
VDD = 3.0V
VSS = 0V
TEMP = 25°C
VD = VDD – VS
0.020
0.015
15
CURRENT (nA)
10
+85°C
ID (OFF)
0.005
0
–0.005
IS (OFF)
–0.010
+25°C
–0.015
–40°C
0
0
1
IS, ID (ON)
2
3
–0.020
4
5
VS/VD (V)
Figure 6. On Resistance as a Function of Drain (VD) or Source (VS)
Voltage for Different Temperatures with 5 V Single Supplies
–0.025
VS
0
0.5
1.0
1.5
VS/VD (V)
2.0
2.5
3.0
02373-008
5
02373-005
RON (Ω)
0.010
Figure 9. Leakage Current as a Function of Drain (VD) or Source (VS) Voltage
for VDD = 3 V
Rev. C | Page 7 of 14
ADG774A
0.05
Data Sheet
0
VDD = 5.0V
VSS = 0V
TEMP = 25°C
VD = 3V/1V
VS = 1V/3V
0.04
0.03
–20
IS, ID (ON)
ATTENUATION (dB)
CURRENT (nA)
0.02
ID (OFF)
0.01
0
–0.01
IS (OFF)
–0.02
–40
–60
–0.03
–80
5
15
25
35
45
55
65
75
85
TEMPERATURE (°C)
–100
0.01
02373-009
–0.05
CURRENT (nA)
1000
100
1000
2.0
2.5
IS, ID (ON)
0.02
IS (OFF)
0.01
0
–0.01
100
Figure 13. Crosstalk vs. Frequency
ON RESPONSE (dB)
0.03
10
0
VDD = 3.0V
VSS = 0V
TEMP = 25°C
VD = 2V/1V
VS = 1V/2V
0.04
1
FREQUENCY (MHz)
Figure 10. Leakage Current as a Function of Temperature, VDD = 5 V
0.05
0.1
02373-012
–0.04
ID (OFF)
–0.02
–5
–10
–0.03
5
15
25
35
45
55
65
75
85
TEMPERATURE (°C)
–15
0.01
02373-010
–0.05
0.1
1
10
FREQUENCY (MHz)
Figure 11. Leakage Current as a Function of Temperature, VDD = 3 V
02373-013
–0.04
Figure 14. Bandwidth
0
0
–1
–2
QINJ (pC)
–40
–60
VDD = 3V
–3
–4
VDD = 5V
–5
–80
–100
0.01
0.1
1
10
100
FREQUENCY (MHz)
1000
Figure 12. Off Isolation vs. Frequency
–7
0
0.5
1.0
1.5
VOLTAGE (V)
Figure 15. Charge Injection vs. Source Voltage
Rev. C | Page 8 of 14
02373-014
–6
02373-011
ATTENUATION (dB)
–20
Data Sheet
ADG774A
TEST CIRCUITS
VDD
0.1µF
ADG774A
IDS
V1
S1A
50Ω
D
VS
IN
02373-019
RON = V1/IDS
VIN
VOUT
D1
EN
50Ω
GND
Figure 16. On Resistance
02373-024
S
VS
NETWORK
ANALYZER
Figure 19. Bandwidth
VDD
0.1µF
ADG774A
S
A
D
NETWORK
ANALYZER
ID (OFF)
S1A
A
VS
50Ω
50Ω
02373-020
VD
VS
IN
VIN
VOUT
D1
EN
50Ω
GND
Figure 17. Off Leakage
02373-025
IS (OFF)
Figure 20. Off Isolation
VDD
0.1µF
NETWORK
ANALYZER
ADG774A
S
D
A
VD
NC = NO CONNECT
VS
S2A
RL
50Ω
02373-021
VOUT
IN
D2
VIN
D1
EN
GND
50Ω
Figure 21. Channel-to-Channel Crosstalk
Figure 18. On Leakage
Rev. C | Page 9 of 14
02373-026
NC
50Ω
S1A
ID (ON)
ADG774A
Data Sheet
5V
0.1µF
VIN
3V
VDD
50%
S
VOUT
D
VS
RL
100Ω
IN
CL
35pF
50%
90%
90%
VOUT
tOFF
tON
02373-022
GND
EN
Figure 22. Switching Times
5V
0.1µF
VDD
3V
S1A
VS
VOUT
D1
S1B
RL
100Ω
VS
CL
35pF
DECODER
VIN
50%
50%
0V
VOUT
80%
VS
tD
EN
80%
tD
02373-023
GND
Figure 23. Break-Before-Make Time Delay
5V
VDD
VS
ADG774A
S1A
CL
1nF
S1B
S2A
CL
1nF
S2B
S3A
CL
1nF
S3B
S4A
CL
1nF
S4B
D1 VOUT
3V
VIN
D2 VOUT
VOUT
D3 VOUT
∆VOUT
QINJ = CL × ∆VOUT
D4 VOUT
1 OF 2
DECODER
EN
IN
02373-027
RS
Figure 24. Charge Injection
Rev. C | Page 10 of 14
Data Sheet
ADG774A
TERMINOLOGY
VDD
Most positive power supply potential.
VD (VS)
Analog voltage on the D and S terminals.
GND
Ground (0 V) reference.
CS (OFF)
Off switch source capacitance.
S
Source terminal. May be an input or output.
CD (OFF)
Off switch drain capacitance.
D
Drain terminal. May be an input or output.
CD, CS (ON)
On switch capacitance.
IN
Logic control input.
tON
Delay between applying the digital control input and the output
switching on. See Figure 22.
EN
Logic control input.
tOFF
Delay between applying the digital control input and the output
switching off.
RON
Ohmic resistance between D and S.
∆RON
On resistance match between any two channels, that is,
RON max − RON min.
tD
Off time or on time measured between the 80% points of both
switches when switching from one address state to another. See
Figure 23.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another because of parasitic capacitance.
IS (OFF)
Source leakage current with the switch off.
ID (OFF)
Drain leakage current with the switch off.
ID, IS (ON)
Channel leakage current with the switch on.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Bandwidth
Frequency response of the switch in the on state measured at
3 dB down.
Distortion
RFLAT(ON)/RL
Rev. C | Page 11 of 14
ADG774A
Data Sheet
APPLICATION CIRCUITS
10 BASE Tx+
10 BASE Tx–
Tx1
ADG774A
100 BASE Tx+
Tx2
100 BASE Tx–
RJ45
10 BASE Tx+
Rx1
10 BASE Tx–
TRANSFORMER
100 BASE Tx+
Rx2
100 BASE Tx–
02373-015
10 BASE Tx
100 BASE Tx
Figure 25. Full Duplex Transceiver
Tx1
Figure 26. Loop Back
Figure 27. Line Termination
Rev. C | Page 12 of 14
02373-018
100Ω
02373-017
02373-016
120Ω
Rx1
Figure 28. Line Clamp
Data Sheet
ADG774A
OUTLINE DIMENSIONS
0.197 (5.00)
0.193 (4.90)
0.189 (4.80)
16
9
0.158 (4.01)
0.154 (3.91)
0.150 (3.81)
1
8
0.010 (0.25)
0.006 (0.15)
0.069 (1.75)
0.053 (1.35)
0.065 (1.65)
0.049 (1.25)
0.010 (0.25)
0.004 (0.10)
COPLANARITY
0.004 (0.10)
0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
0.025 (0.64)
BSC
SEATING
PLANE
8°
0°
0.012 (0.30)
0.008 (0.20)
0.020 (0.51)
0.010 (0.25)
0.050 (1.27)
0.016 (0.41)
0.041 (1.04)
REF
09-12-2014-A
COMPLIANT TO JEDEC STANDARDS MO-137-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 29. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches and (millimeters)
0.30
0.25
0.20
0.50
BSC
13
PIN 1
INDICATOR
16
1
12
1.65
1.50 SQ
1.45
EXPOSED
PAD
9
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
4
8
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
01-26-2012-A
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-27)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG774ABRQ-REEL7
ADG774ABRQZ
ADG774ABRQZ-REEL
ADG774ABRQZ-REEL7
ADG774ABCPZ-REEL
ADG774ABCPZ-R2
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
Rev. C | Page 13 of 14
Package Option
RQ-16
RQ-16
RQ-16
RQ-16
CP-16-27
CP-16-27
ADG774A
Data Sheet
NOTES
©2001–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02373-0-4/16(C)
Rev. C | Page 14 of 14