High Voltage Latch-Up Proof,
Single SPST Switch
ADG5401
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Latch-up immune under all circumstances
Human body model (HBM) ESD rating: 8 kV
Low on resistance: 6.5 Ω
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VDD to VSS analog signal range
ADG5401
D
S
SWITCHES SHOWN FOR A LOGIC 1 INPUT
APPLICATIONS
11728-001
IN
Figure 1.
High voltage signal routing
Automatic test equipment
Analog front-end circuits
Precision data acquisition
Amplifier gain select
Industrial instrumentation
Relay replacement
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG5401 is a monolithic industrial, complementary metal
oxide semiconductor (CMOS) analog switch containing a latchup immune single-pole/single-throw (SPST) switch. The switch
conducts equally well in both directions when on, and has an
input signal range that extends to the power supplies. In the off
condition, signal levels up to the supplies are blocked.
1.
The ultralow on resistance and on-resistance flatness of these
switches make them ideal solutions for data acquisition and gain
switching applications, where low distortion is critical. The
latch-up immune construction and high ESD rating make these
switches more robust in harsh environments.
Rev. A
2.
3.
4.
5.
6.
7.
Trench isolation guards against latch-up. A dielectric trench
separates the P channel and N channel transistors, thereby
preventing latch-up even under severe overvoltage
conditions.
Low RON of 6.5 Ω.
Dual-supply operation. For applications where the analog
signal is bipolar, the ADG5401 can operate from dual
supplies of up to ±22 V.
Single-supply operation. For applications where the analog
signal is unipolar, the ADG5401 can operate from a singlerail power supply of up to 40 V.
3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
No VL logic power supply required.
Available in 8-lead MSOP package and 8-lead, 2 mm ×
3 mm LFCSP packages.
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Technical Support
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ADG5401
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Continuous Current per Channel, S or D ..................................7
Applications ....................................................................................... 1
Absolute Maximum Ratings ............................................................8
Functional Block Diagram .............................................................. 1
ESD Caution...................................................................................8
General Description ......................................................................... 1
Pin Configurations and Function Descriptions ............................9
Product Highlights ........................................................................... 1
Typical Performance Characteristics ........................................... 10
Revision History ............................................................................... 2
Test Circuits ..................................................................................... 13
Specifications..................................................................................... 3
Terminology .................................................................................... 15
±15 V Dual Supply ....................................................................... 3
Applications Information .............................................................. 16
±20 V Dual Supply ....................................................................... 4
Trench Isolation .......................................................................... 16
12 V Single Supply ........................................................................ 5
Outline Dimensions ....................................................................... 17
36 V Single Supply ........................................................................ 6
Ordering Guide .......................................................................... 17
REVISION HISTORY
1/15—Rev. 0 to Rev. A
Added 8-Lead LFCSP ......................................................... Universal
Changed Continuous Current, S or D Parameter to 8-Lead
MSOP, Table 5 ................................................................................... 7
Added Figure 2; Renumbered Sequentially .................................. 9
Changes to Table 7 ............................................................................ 9
Changes to Figure 4 ........................................................................ 10
Added Figure 19.............................................................................. 12
Changes to Figure 21 and Figure 26 ............................................ 13
Added AC Power Supply Rejection Ratio (ACPSRR),
Terminology Section ...................................................................... 15
Added Figure 30, Outline Dimensions ........................................ 17
Changes to Ordering Guide .......................................................... 17
9/13—Revision 0: Initial Version
Rev. A | Page 2 of 17
Data Sheet
ADG5401
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
6.5
8
1
1.4
±0.1
±0.5
±0.1
±0.5
±0.2
±1
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
VDD to VSS
V
Ω typ
Ω max
Ω typ
Ω max
VS = ±10 V, IS = −10 mA; see Figure 21
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −10 mA
10
12
1.7
2
±2
±20
±2
±20
±8
±40
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
6
V min
V max
µA typ
µA max
pF typ
Charge Injection, QINJ
160
193
175
207
220
Off Isolation
−50
dB typ
Total Harmonic Distortion + Noise
(THD + N)
−3 dB Bandwidth
Insertion Loss
0.01
% typ
170
−0.4
MHz typ
dB typ
22
24
75
pF typ
pF typ
pF typ
tOFF
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
ISS
45
55
0.001
VDD/VSS
1
nA typ
nA max
nA typ
nA max
nA typ
nA max
230
253
230
242
70
1
±9/±22
Guaranteed by design; not subject to production test.
Rev. A | Page 3 of 17
ns typ
ns max
ns typ
ns max
pC typ
µA typ
µA max
µA typ
µA max
V min/V max
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD =  10 V; see Figure 20
VS = ±10 V, VD =  10 V; see Figure 20
VS = VD = ±10 V; see Figure 23
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
VS = 0 V, RS = 0 Ω, CL = 1 nF; see
Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 22
RL = 1 kΩ, 15 V p-p, f = 20 Hz to
20 kHz; see Figure 24
RL = 50 Ω, CL = 5 pF; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 25
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
ADG5401
Data Sheet
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Flatness, RFLAT (ON)
25°C
−40°C to +85°C
−40°C to +125°C
Unit
VDD to VSS
V
Ω typ
6
7
1.2
1.7
9
11
2.1
2.5
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.1
±0.5
±0.1
±2
Drain Off Leakage, ID (Off )
±0.5
±0.2
±1
±2
±20
±8
±40
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
nA typ
±20
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
6
nA max
nA typ
VIN = VGND or VDD
−50
dB typ
Total Harmonic Distortion + Noise
(THD + N)
−3 dB Bandwidth
Insertion Loss
0.01
% typ
170
−0.5
MHz typ
dB typ
21
23
75
pF typ
pF typ
pF typ
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
ISS
50
70
0.001
VDD/VSS
214
223
110
1
±9/±22
Guaranteed by design; not subject to production test.
Rev. A | Page 4 of 17
VS = ±15 V, VD =  15 V; see
Figure 20
V min
V max
µA typ
µA max
pF typ
Off Isolation
219
VDD = +22 V, VSS = −22 V
VS = ±15 V, VD =  15 V; see
Figure 20
VS = VD = ±15 V; see Figure 23
Charge Injection, QINJ
207
VS = ±15 V, IS = −10 mA;
see Figure 21
VDD = +18 V, VSS = −18 V
VS = ±15 V, IS = −10 mA
nA max
nA typ
nA max
150
175
170
196
275
tOFF
1
Ω max
Ω typ
Ω max
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
pC typ
µA typ
µA max
µA typ
µA max
V min/V max
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
VS = 0 V, RS = 0 Ω, CL = 1 nF; see
Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 22
RL = 1 kΩ, 20 V p-p, f = 20 Hz to
20 kHz; see Figure 24
RL = 50 Ω, CL = 5 pF; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 25
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
Data Sheet
ADG5401
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Flatness, RFLAT (ON)
25°C
−40°C to +85°C
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
14
16
2.8
4
19
22
5.5
7
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.1
±0.5
±0.1
±2
Drain Off Leakage, ID (Off )
±0.5
±0.2
±1
±2
±20
±8
±40
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
nA typ
±20
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
6
nA max
nA typ
VIN = VGND or VDD
−50
dB typ
Total Harmonic Distortion + Noise
(THD + N)
−3 dB Bandwidth
Insertion Loss
0.02
% typ
190
−0.9
MHz typ
dB typ
28
30
60
pF typ
pF typ
pF typ
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
40
50
VDD
280
300
65
9/40
Guaranteed by design; not subject to production test.
Rev. A | Page 5 of 17
VS = 1 V to 10 V, VD = 10 V to 1 V;
see Figure 20
V min
V max
µA typ
µA max
pF typ
Off Isolation
454
VDD = +13.2 V, VSS = 0 V
VS = 1 V to 10 V, VD = 10 V to 1 V;
see Figure 20
VS = VD = 1 V to 10 V; see Figure 23
Charge Injection, QINJ
406
VS = 0 V to 10 V, IS = −10 mA; see
Figure 21
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
nA max
nA typ
nA max
260
327
200
244
95
tOFF
1
Ω max
Ω typ
Ω max
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
pC typ
µA typ
µA max
V min/V max
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 26
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 22
RL = 1 kΩ, 6 V p-p, f = 20 Hz to
20 kHz; see Figure 24
RL = 50 Ω, CL = 5 pF; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 25
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD
GND = 0 V, VSS = 0 V
ADG5401
Data Sheet
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Flatness, RFLAT (ON)
25°C
−40°C to +85°C
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
7
9
1.8
2.6
11
13
3
3.5
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.1
±0.5
±0.1
±2
Drain Off Leakage, ID (Off )
±0.5
±0.2
±1
±2
±20
±8
±40
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
nA typ
±20
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
6
nA max
nA typ
VIN = VGND or VDD
−50
dB typ
Total Harmonic Distortion + Noise
(THD + N)
−3 dB Bandwidth
Insertion Loss
0.01
% typ
170
−0.55
MHz typ
dB typ
26
28
65
pF typ
pF typ
pF typ
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
80
100
VDD
221
225
130
9/40
Guaranteed by design; not subject to production test.
Rev. A | Page 6 of 17
VS = 1 V to 30 V, VD = 30 V to 1 V; see
Figure 20
V min
V max
µA typ
µA max
pF typ
Off Isolation
230
VDD = +39.6 V, VSS = 0 V
VS = 1 V to 30 V, VD = 30 V to 1 V; see
Figure 20
VS = VD = 1 V to 30 V; see Figure 23
Charge Injection, QINJ
212
VS = 0 V to 30 V, IS = −10 mA; see
Figure 21
VDD = 32.4 V, VSS = 0 V
VS = 0 V to 30 V, IS = −10 mA
nA max
nA typ
nA max
160
187
180
213
255
tOFF
1
Ω max
Ω typ
Ω max
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
pC typ
µA typ
µA max
V min/V max
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 26
VS = 18 V, RS = 0 Ω, CL = 1 nF; see
Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 22
RL = 1 kΩ, 18 V p-p, f = 20 Hz to
20 kHz; see Figure 24
RL = 50 Ω, CL = 5 pF; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 25
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
Digital inputs = 0 V or VDD
GND = 0 V, VSS = 0 V
Data Sheet
ADG5401
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 5.
Parameter
8-LEAD MSOP
VDD = 15 V, VSS = −15 V
VDD = 20 V, VSS = −20 V
VDD = 12 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
8-LEAD LFCSP
VDD = 15 V, VSS = −15 V
VDD = 20 V, VSS = −20 V
VDD = 12 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
25°C
85°C
125°C
Unit
171
177
139
174
116
120.5
99
118
79
81
70
81
mA maximum
mA maximum
mA maximum
mA maximum
234
246
193
241
150
155
130
153
93
95
85
95
mA maximum
mA maximum
mA maximum
mA maximum
Test Condition/Comments
θJA = 133.1°C/W
θJA = 60.88°C/W
Rev. A | Page 7 of 17
ADG5401
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, S or D Pin
Continuous Current, S or D2
Temperature Range
Operating
Storage
Junction Temperature
Thermal Impedance, θJA
8-Lead MSOP (4-Layer Board)
8-Lead LFCSP
Reflow Soldering Peak
Temperature, Pb Free
Human Body Model (HBM) ESD
Rating
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
630 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data + 15%
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
133.1°C/W
60.88°C/W
As per JEDEC J-STD-020
8 kV
1
Overvoltages at the IN, S, and D pins are clamped by internal diodes. Limit
current to the maximum ratings given.
2
See Table 5.
Rev. A | Page 8 of 17
Data Sheet
ADG5401
S 1
S 1
8 D
ADG5401
GND 3
TOP VIEW
(Not to Scale)
VDD 4
7 VSS
6 IN
ADG5401
GND 3
TOP VIEW
(Not to Scale)
VDD 4
5 NC
NOTES
1. NC = NO CONNECT. NOT INTERNALLY CONNECTED.
2. THE EXPOSED PAD IS TIED TO SUBSTRATE, VSS.
8
D
7
VSS
6
IN
5
NC
NOTES
1. NC = NO CONNECT. NOT INTERNALLY CONNECTED.
11728-102
NC 2
NC 2
Figure 2. 8-Lead LFCSP Pin Configuration
Figure 3. 8-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
8-Lead LFCSP
1
2
3
4
5
6
7
8
Pin No.
8-Lead MSOP
1
2
3
4
5
6
7
8
Not applicable
Mnemonic
S
NC
GND
VDD
NC
IN
VSS
D
EPAD
Description
Source Terminal. This pin can be an input or output.
No Connect. Not internally connected.
Ground (0 V) Reference.
Most Positive Power Supply Potential.
No Connect. Not internally connected.
Logic Control Input.
Most Negative Power Supply Potential.
Drain Terminal. This pin can be an input or output.
The exposed pad is tied to substrate, VSS.
Table 8. Truth Table
IN
1
0
Switch Condition
On
Off
Rev. A | Page 9 of 17
11728-002
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADG5401
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
8
12
TA = 25°C
+125°C
+85°C
+25°C
–40°C
7
10
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
6
5
4
±13.5V
±15.0V
±16.5V
±18.0V
±20.0V
±22.0V
3
2
8
6
4
2
–20 –15
–5
–10
–5
0
5
10
15
20
25
VS, VD (V)
0
–20
11728-003
0
–25
–10
–5
0
5
10
15
20
VS, VD (V)
Figure 4. On Resistance as a Function of VS, VD (Dual Supply)
Figure 7. On Resistance as a Function of VS (VD) for Different Temperatures,
±20 V Dual Supply
20
16
TA = 25°C
+125°C
+85°C
+25°C
–40°C
18
14
+10.8V
+12.0V
+13.2V
+32.4V
+36.0V
+39.6V
10
16
ON RESISTANCE (Ω)
12
ON RESISTANCE (Ω)
–15
11728-006
1
8
6
14
12
10
8
6
4
4
2
5
10
15
20
25
VS, VD (V)
35
30
0
11728-004
0
6
8
10
12
Figure 8. On Resistance as a Function of VS (VD) for Different Temperatures,
12 V Single Supply
12
12
+125°C
+85°C
+25°C
–40°C
+125°C
+85°C
+25°C
–40°C
10
ON RESISTANCE (Ω)
10
ON RESISTANCE (Ω)
4
VS, VD (V)
Figure 5. On Resistance as a Function of VS, VD (Single Supply)
8
6
4
8
6
4
2
2
–10
–5
0
VS, VD (V)
5
10
15
0
11728-005
0
–15
2
0
Figure 6. On Resistance as a Function of VS (VD) for Different Temperatures,
±15 V Dual Supply
5
10
15
20
VS, VD (V)
25
30
35
11728-008
0
11728-007
2
0
Figure 9. On Resistance as a Function of VS (VD) for Different Temperatures,
36 V Single Supply
Rev. A | Page 10 of 17
Data Sheet
ADG5401
1.0
1.0
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
IS, ID (ON) + +
IS, ID (ON) – –
0.6
0.4
0.6
LEAKAGE CURRENT (nA)
LEAKAGE CURRENT (nA)
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
IS, ID (ON) + +
IS, ID (ON) – –
0.8
0.8
0.2
0
–0.2
0.4
0.2
0
–0.2
–0.4
–0.6
–0.4
25
50
75
100
125
TEMPERATURE (°C)
–1.0
11728-009
0
Figure 10. Leakage Currents as a Function of Temperature, ±15 V Dual Supply
0
50
75
100
125
TEMPERATURE (°C)
Figure 13. Leakage Currents as a Function of Temperature, 36 V Single
Supply
0
1.0
0.8
–20
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
IS, ID (ON) + +
IS, ID (ON) – –
0.6
0.4
0.2
OFF ISOLATION (dB)
LEAKAGE CURRENT (nA)
25
11728-012
–0.8
–0.6
0
–0.2
TA = 25°C
VDD = +15V
VSS = –15V
–40
–60
–80
–0.4
–100
0
25
50
75
100
125
TEMPERATURE (°C)
–120
11728-010
–0.8
1k
100k
1M
10M
100M
1G
30
40
FREQUENCY (Hz)
Figure 11. Leakage Currents as a Function of Temperature, ±20 V Dual
Supply
Figure 14. Off Isolation vs. Frequency
600
0.8
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
IS, ID (ON) + +
IS, ID (ON) – –
0.4
500
CHARGE INJECTION (pC)
0.6
0.2
0
VDD = 15V, VSS = –15V
VDD = 20V, VSS = –20V
VDD = 12V, VSS = 0V
VDD = 36V, VSS = 0V
400
300
200
–0.4
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 12. Leakage Currents as a Function of Temperature,
12 V Single Supply
0
–20
–10
0
10
20
VS (V)
Figure 15. Charge Injection vs. Source Voltage (VS)
Rev. A | Page 11 of 17
11728-014
100
–0.2
11728-011
LEAKAGE CURRENT (nA)
10k
11728-013
–0.6
ADG5401
Data Sheet
300
0.05
TA = 25°C
250
VDD
VDD
VDD
VDD
0.03
= 12V,
= 36V,
= 15V,
= 20V,
VSS
VSS
VSS
VSS
= 0V, VS = 6V p-p
= 0V, VS = 18V p-p
= –15V, VS = 15V p-p
= –20V, VS = 20V p-p
200
TIME (ns)
0.02
150
VDD = 12V, VSS = 0
VDD = 36V, VSS = 0V
VDD = 15V, VSS = –15V
VDD = 20V, VSS = –20V
100
0.01
0
5
10
15
20
FREQUENCY (kHz)
0
–40
11728-015
0
20
40
60
80
100
120
Figure 18. tTRANSITION Times vs. Temperature
0
0
–0.5
–20
–1.0
TA = 25°C
VDD = +15V
VSS = –15V
TA = 25°C
VDD = +15V
VSS = –15V
ACPSRR (dB)
–40
–2.0
–2.5
–3.0
NO DECOUPLING CAPACITORS
–60
–80
–3.5
DECOUPLING CAPACITORS
–4.0
–100
–4.5
–5.0
10k
100k
1M
10M
FREQUENCY (Hz)
100M
1G
11728-016
OFF ISOLATION (dB)
0
TEMPERATURE (°C)
Figure 16. THD + N vs. Frequency
–1.5
–20
11728-017
50
Figure 17. Bandwidth
–120
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 19. ACPSRR vs. Frequency
Rev. A | Page 12 of 17
10M
11728-119
THD + N (%)
0.04
Data Sheet
ADG5401
TEST CIRCUITS
A
S
D
ID (OFF)
A
VD
11728-018
VS
S
NC
D
ID (ON)
A
VD
NC = NO CONNECT
Figure 20. Off Leakage
11728-021
IS (OFF)
Figure 23. On Leakage
VDD
VSS
0.1µF
0.1µF
VDD
AUDIO PRECISION
VSS
RS
S
VS
V p-p
IN
V
D
VIN
D
GND
IDS
11728-019
RON = V ÷ IDS
Figure 21. On Resistance
VSS
VDD
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
S
0.1µF
VDD
NETWORK
ANALYZER
VSS
S
50Ω
50Ω
IN
VSS
0.1µF
50Ω
IN
VS
VS
D
D
RL
50Ω
GND
VOUT
VIN
OFF ISOLATION = 20 log
VOUT
VS
INSERTION LOSS = 20 log
Figure 22. Off Isolation
VDD
RL
50Ω
GND
11728-020
VIN
VSS
0.1µF
3V
VDD
VS
VIN
VSS
S
ADG5401
50%
50%
0V
VOUT
D
RL
300Ω
IN
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 25. Bandwidth
0.1µF
CL
35pF
VS
0.9 VS
VOUT
GND
tON
Figure 26. Switching Times, tON and tOFF
Rev. A | Page 13 of 17
90%
0.1 VS
0V
tOFF
VOUT
11728-023
VDD
Figure 24. THD + N
11728-024
VS
VOUT
RL
1kΩ
11728-022
S
ADG5401
Data Sheet
VS
VSS
VDD
VSS
S
D
VIN
ADG5401
ON
VOUT
OFF
CL
1nF
IN
GND
VOUT
QINJ = CL × ∆VOUT
Figure 27. Charge Injection
Rev. A | Page 14 of 17
∆VOUT
11728-025
RS
VDD
Data Sheet
ADG5401
TERMINOLOGY
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
IDD
IDD represents the positive supply current.
ISS
ISS represents the negative supply current.
CD (On), CS (On)
CD (On) and CS (On) represent the on switch capacitances,
which are measured with reference to ground.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal S, respectively.
CIN
CIN represents digital input capacitance.
RON
RON is the ohmic resistance between Terminal D and
Terminal S.
RFLAT (ON)
RFLAT (ON) represents the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
tON
tON represents the delay time between the 50% and 90% points
of the digital input and switch on condition.
tOFF
tOFF represents the delay time between the 50% and 90% points
of the digital input and switch off condition.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off channel.
IS (Off)
IS (Off) is the source leakage current with the switch off.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB from its dc value.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental is represented by THD + N.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR measures the ability of the device to avoid coupling
noise and spurious signals that appear on the supply voltage pin
to the output of the switch. The dc voltage on the device is
modulated by a sine wave of 0.62 V p-p. The ratio of the
amplitude of the signal on the output to the amplitude of the
modulation is the ACPSRR (see Figure 19).
Rev. A | Page 15 of 17
ADG5401
Data Sheet
APPLICATIONS INFORMATION
TRENCH ISOLATION
In the ADG5401, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction-isolated switches, are eliminated, and the result is a
latch-up immune switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. The two transistors form a
silicon-controlled rectifier (SCR) type circuit, causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up immune switch.
Rev. A | Page 16 of 17
NMOS
PMOS
P-WELL
N-WELL
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 28. Trench Isolation
11728-026
The ADG54xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, aerospace, and
other harsh environments that are prone to latch-up, which is an
undesirable high current state that can lead to device failure and
persists until the power supply is turned off. The ADG5401
high voltage switch allows single-supply operation from 9 V
to 40 V and dual-supply operation from ±9 V to ±22 V. The
ADG5401 (as well as other select devices within this family)
achieves an 8 kV human body model ESD rating, which
provides a robust solution, eliminating the need for separate
protection circuitry designs in some applications.
Data Sheet
ADG5401
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
6°
0°
0.40
0.25
0.80
0.55
0.40
0.23
0.09
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 29. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
1.75
1.65
1.50
2.00 BSC
5
3.00 BSC
8
1.90
1.80
1.65
EXPOSED
PAD
0.20 MIN
4
INDEX
AREA
0.50
0.40
0.30
TOP VIEW
0.80
0.75
0.70
COPLANARITY
0.08
0.30
0.25
0.20
0.50
0.05 MAX
0.02 NOM
PIN 1
INDICATOR
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
081806-A
SEATING
PLANE
0.15 REF
SIDE VIEW
1
BOTTOM VIEW
Figure 30. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
2 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG5401BRMZ
ADG5401BRMZ-RL7
ADG5401BCPZ-RL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
Z = RoHS Compliant Part.
©2013–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11728-0-1/15(A)
Rev. A | Page 17 of 17
Package Option
RM-8
RM-8
CP-8-4
Branding
S2M
S2M
BR