1 Ω On Resistance, ±15 V/+12 V/±5 V
iCMOS SPST Switches
ADG1401/ADG1402
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1 Ω on resistance
0.2 Ω on resistance flatness
Up to 430 mA continuous current
Fully specified at +12 V, ±15 V, ±5 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
8-lead MSOP and 8-lead, 3 mm × 2 mm LFCSP packages
ADG1401
D
S
SWITCHES SHOWN FOR A LOGIC 1 INPUT
08486-001
IN
Figure 1. ADG1401 Functional Block Diagram
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
Relay replacements
ADG1402
S
D
SWITCHES SHOWN FOR A LOGIC 1 INPUT
08486-002
IN
Figure 2. ADG1402 Functional Block Diagram
GENERAL DESCRIPTION
The ADG1401/ADG1402 contain a single-pole/single-throw
(SPST) switch. Figure 1 shows that with a logic input of 1, the
switch of the ADG1401 is closed and that of the ADG1402 is
open. Each switch conducts equally well in both directions when
on and has an input signal range that extends to the supplies. In
the off condition, signal levels up to the supplies are blocked.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. The iCMOS construction ensures
ultralow power dissipation, making the part ideally suited for
portable and battery-powered instruments.
The iCMOS® (industrial CMOS) modular manufacturing process
combines high voltage, complementary metal-oxide semiconductor
(CMOS) and bipolar technologies. It enables the development
of a wide range of high performance analog ICs capable of 33 V
operation in a footprint that no other generation of high voltage
parts has achieved. Unlike analog ICs using conventional CMOS
processes, iCMOS components can tolerate high supply voltages
while providing increased performance, dramatically lower
power consumption, and a reduced package size.
1.
2.
3.
4.
5.
PRODUCT HIGHLIGHTS
1.3 Ω maximum on resistance at 25°C.
Minimum distortion.
3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
No VL logic power supply required.
8-lead MSOP and 8-lead, 3 mm × 2 mm LFCSP packages.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
ADG1401/ADG1402
TABLE OF CONTENTS
Features .............................................................................................. 1 Continuous Current Per Channel, S or D ..................................6 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................7 Functional Block Diagram .............................................................. 1 Thermal Resistance .......................................................................7 General Description ......................................................................... 1 ESD Caution...................................................................................7 Product Highlights ........................................................................... 1 Pin Configuration and Function Descriptions..............................8 Revision History ............................................................................... 2 Typical Performance Characteristics ..............................................9 Specifications..................................................................................... 3 Test Circuits ..................................................................................... 12 ±15 V Dual Supply ....................................................................... 3 Terminology .................................................................................... 14 +12 V Single Supply ..................................................................... 4 Outline Dimensions ....................................................................... 15 ±5 V Dual Supply ......................................................................... 5 Ordering Guide .......................................................................... 15 REVISION HISTORY
10/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADG1401/ADG1402
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
−40°C to
+85°C
−40°C to
+125°C
VDD to VSS
1
1.3
0.2
0.23
±0.05
±0.4
±0.05
±0.4
±0.2
±1
1.6
1.8
0.26
0.3
±3
±150
±3
±150
±3
±150
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
tOFF
Charge Injection
Off Isolation
Total Harmonic Distortion + Noise
−3 dB Bandwidth
Insertion Loss
CS (Off )
CD (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
4
120
150
120
150
−12
−58
0.008
185
215
175
200
120
0.08
36
41
187
0.002
60
95
ISS
0.002
VDD/VSS
1
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
Ω max
VS = ±10 V, IS = −10 mA; see Figure 20
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V; IS = −10 mA
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns max
pC typ
dB typ
% typ
MHz typ
dB typ
pF typ
pF typ
pF typ
1.0
IDD
Unit
1.0
±4.5/±16.5
μA typ
μA max
μA typ
μA max
μA typ
μA max
V min/max
Guaranteed by design, not subject to production test.
Rev. 0 | Page 3 of 16
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD = ±10 V; see Figure 21
VS = ±10 V, VD = ±10 V; see Figure 21
VS = VD = ±10 V; see Figure 22
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 23
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 23
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 24
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25
RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz;
see Figure 27
RL = 50 Ω, CL = 5 pF; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V, 5 V, or VDD
Ground = 0 V
ADG1401/ADG1402
+12 V SINGLE SUPPLY
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
−40°C to
+85°C
−40°C to
+125°C
0 V to VDD
2
2.4
0.6
0.68
±0.05
±0.4
±0.05
±0.4
±0.2
±1
2.9
3.2
0.8
0.85
±3
±150
±3
±150
±3
±150
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
tOFF
Charge Injection
Off Isolation
−3 dB Bandwidth
Insertion Loss
CS (Off )
CD (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
4
180
235
140
185
57
−58
82
0.15
61
68
181
295
335
215
260
0.001
1.0
IDD
60
VDD
1
95
5/16.5
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to 10 V, IS = −10 mA; see Figure 20
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns max
pC typ
dB typ
MHz typ
dB typ
pF typ
pF typ
pF typ
μA typ
μA max
μA typ
μA max
V min/max
Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 16
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 21
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 21
VS = VD = 1 V or 10 V; see Figure 22
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 23
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 23
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 24
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25
RL = 50 Ω, CL = 5 pF; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Ground = 0 V, VSS = 0 V
ADG1401/ADG1402
±5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Flatness, RFLAT (ON)
25°C
−40°C to
+85°C
−40°C to
+125°C
0 V to VDD
2.3
2.7
0.65
0.72
3.3
3.7
0.85
0.9
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
Ω max
VS = ±4.5 V, IS = −10 mA; see Figure 20
VDD = +4.5 V, VSS = −4.5 V
VS = ±4.5 V, IS = −10 mA
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.02
±3
±150
Drain Off Leakage, ID (Off )
±0.4
±0.02
nA max
nA typ
±0.4
±0.1
±1
±3
±150
VS = VD = ±4.5 V; see Figure 22
±3
±150
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
VIN = VGND or VDD
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
VDD = +5.5 V, VSS = −5.5 V
nA typ
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
tOFF
Charge Injection
Off Isolation
Total Harmonic Distortion + Noise
−3 dB Bandwidth
Insertion Loss
CS (Off )
CD (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
4
290
375
235
305
145
−58
0.02
460
520
365
405
79
0.14
52
58
198
MHz typ
dB typ
pF typ
pF typ
pF typ
0.001
1.0
ISS
0.001
VDD/VSS
1
ns typ
ns max
ns typ
ns max
pC typ
dB typ
% typ
1.0
±4.5/±16.5
Guaranteed by design, not subject to production test.
Rev. 0 | Page 5 of 16
μA typ
μA max
μA typ
μA max
V min/max
VS = ±4.5 V, VD = ∓4.5 V; see Figure 21
VS = ±4.5 V, VD = ∓4.5 V; see Figure 21
RL = 300 Ω, CL = 35 pF
VS = 3 V; see Figure 23
RL = 300 Ω, CL = 35 pF
VS = 3 V; see Figure 23
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 24
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25
RL = 10 kΩ, 5 V p-p, f = 20 Hz to 20 kHz;
see Figure 27
RL = 50 Ω, CL = 5 pF; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +5.5 V, VSS = −5.5 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
Ground = 0 V
ADG1401/ADG1402
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 4.
Parameter
CONTINUOUS CURRENT, S or D 1
±15 V Dual Supply
8-Lead MSOP (θJA = 206°C/W)
8-Lead LFCSP (θJA = 50.8°C/W)
+12 V Single Supply
8-Lead MSOP (θJA = 206°C/W)
8-Lead LFCSP (θJA = 50.8°C/W)
±5 V Dual Supply
8-Lead MSOP (θJA = 206°C/W)
8-Lead LFCSP (θJA = 50.8°C/W)
1
25°C
85°C
125°C
Unit
275
430
190
275
125
160
mA maximum
mA maximum
255
355
180
235
120
145
mA maximum
mA maximum
250
340
175
225
120
140
mA maximum
mA maximum
Test Conditions/Comments
VDD = +13.5 V, VSS = −13.5 V
VDD = 10.8 V, VSS = 0 V
VDD = +4.5 V, VSS = −4.5 V
Guaranteed by design, not subject to production test.
Rev. 0 | Page 6 of 16
ADG1401/ADG1402
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 5.
Table 6. Thermal Resistance
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
1
Digital Inputs
Peak Current, S or D
(Pulsed at 1 ms, 10%
Duty-Cycle Maximum)
8-Lead MSOP (4-Layer Board)
8-Lead LFCSP
Continuous Current per
Channel, S or D
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak
Temperature, Pb Free
1
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Package Type
8-Lead MSOP (4-Layer Board)
8-Lead LFCSP
ESD CAUTION
500 mA
700 mA
Data in Table 4 + 15%
−40°C to +125°C
−65°C to +150°C
150°C
260°C
Over voltages at IN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 16
θJA
206
50.8
θJC
44
Unit
°C/W
°C/W
ADG1401/ADG1402
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADG1401/
ADG1402
GND 3
TOP VIEW
(Not to Scale)
VDD 4
8 D
7 VSS
6 IN
5 NC
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
2. NC = NO CONNECT.
08486-003
S 1
NC 2
Figure 3. ADG1401/ADG1402 Pin Configuration
Table 7. ADG1401/ADG1402 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
S
NC
GND
VDD
NC
IN
VSS
D
EPAD
Description
Source Terminal. This pin can be an input or output.
No Connect.
Ground (0 V) Reference.
Most Positive Power Supply Potential.
No Connect.
Logic Control Input.
Most Negative Power Supply Potential.
Drain Terminal. This pin can be an input or output.
Exposed pad tied to substrate, VSS, for LFCSP package.
Table 8. ADG1401/ADG1402 Truth Table
ADG1401 IN
1
0
ADG1402 IN
0
1
Switch Condition
On
Off
Rev. 0 | Page 8 of 16
ADG1401/ADG1402
TYPICAL PERFORMANCE CHARACTERISTICS
1.5
1.4
VDD = +12V
VSS = –12V
1.6
1.3
VDD = +13.5V
VSS = –13.5V
1.4
1.2
VDD = +15V
VSS = –15V
1.8
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
2.0
VDD = +10V
VSS = –10V
TA = 25°C
1.1
1.0
0.9
0.8
–11.5
–6.5
–1.5
3.5
8.5
TA = +25°C
0.8
TA = –40°C
0.6
0.2
VDD = +15V
VSS = –15V
0
–15
–10
08486-016
0.6
–16.5
TA = +85°C
1.0
0.4
VDD = +16.5V
VSS = –16.5V
0.7
TA = +125°C
1.2
13.5
VS, VD (V)
–5
0
5
10
15
VS, VD (V)
Figure 4. On Resistance as a Function of VD (VS) for Dual Supply
08486-012
1.6
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
±15 V Dual Supply
4.0
3.0
VDD = 5V
VSS = 0V
2.5
VDD = 12V
VSS = 0V
VDD = 8V
VSS = 0V
2.5
ON RESISTANCE (Ω)
VDD = 10.8V
VSS = 0V
3.0
VDD = 13.2V
VSS = 0V
VDD = 15V
VSS = 0V
2.0
TA = +85°C
1.5
TA = +25°C
TA = –40°C
1.0
0.5
1.0
0
4
6
8
10
12
14
16
VS, VD (V)
Figure 5. On Resistance as a Function of VD (VS) for Single Supply
0
3.5
VDD = +4.5V
VSS = –4.5V
ON RESISTANCE (Ω)
VDD = +5.5V
VSS = –5.5V
1.6
1.4
1.2
VDD = +7V
VSS = –7V
–1
1
3
5
7
12
VDD = +5V
VSS = –5V
2.5
TA = +125°C
TA = +85°C
2.0
TA = +25°C
1.5
TA = –40°C
1.0
VS, VD (V)
Figure 6. On Resistance as a Function of VD (VS) for Dual Supply
0
08486-015
–3
10
0.5
1.0
–5
8
3.0
VDD = +5V
VSS = –5V
–7
6
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
+12 V Single Supply
TA = 25°C
1.8
4
VS, VD (V)
2.4
2.0
2
–5
–4
–3
–2
–1
0
VS, VD (V)
1
2
3
4
5
08486-013
2
08486-011
VDD = 12V
VSS = 0V
0
ON RESISTANCE (Ω)
TA = +125°C
2.0
1.5
08486-014
ON RESISTANCE (Ω)
3.5
Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures,
±5 V Dual Supply
Rev. 0 | Page 9 of 16
ADG1401/ADG1402
90
80
IDD PER CHANNEL
TA = 25°C
80
70
60
60
50
50
40
IDD (µA)
IS (OFF) – +
ID (OFF) + –
IS (OFF) – +
ID (OFF) + –
ID, IS (ON) + +
ID, IS (ON) – –
30
20
40
VDD = +15V
VSS = –15V
VDD = 12V
VSS = 0V
30
20
10
VDD = +5V
VSS = –5V
10
0
0
0
20
40
60
80
100
120
TEMPERATURE (°C)
–10
08486-028
–10
0
2
4
6
8
10
12
08486-018
LEAKAGE CURRENT (nA)
VDD = +15V
VSS = –15V
70 VBIAS = ±10V
14
LOGIC LEVEL, IN (V)
Figure 10. Leakage Currents as a Function of Temperature,
±15 V Dual Supply
Figure 13. IDD vs. Logic Level
1000
70
VDD = 12V
VSS = 0V
60 VBIAS = 1V/10V
TA = 25°C
VDD = +5V
VSS = –5V
800
CHARGE INJECTION (pC)
LEAKAGE CURRENT (nA)
600
50
40
IS (OFF) + –
ID (OFF) – +
IS (OFF) – +
ID (OFF) + –
ID, IS (ON) + +
ID, IS (ON) – –
30
20
10
400
VDD = +12V
VSS = 0V
200
0
VDD = +15V
VSS = –15V
–200
–400
–600
0
20
40
60
80
100
120
TEMPERATURE (°C)
08486-029
0
–1000
–15
–5
0
5
10
15
VS (V)
Figure 11. Leakage Currents as a Function of Temperature,
+12 V Single Supply
Figure 14. Charge Injection vs. Source Voltage
60
350
VDD = +5V
VSS = –5V
50 VBIAS = ±4.5V
300
40
250
tOFF (±5V)
30
20
10
TIME (ns)
IS (OFF) + –
ID (OFF) – +
IS (OFF) – +
ID (OFF) + –
ID, IS (ON) + +
ID, IS (ON) – –
200
150
tON (±5V)
100
tON (12V)
tOFF (12V)
tOFF (±15V)
tON (±15V)
50
–10
0
20
40
60
80
100
120
TEMPERATURE (°C)
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 12. Leakage Currents as a Function of Temperature,
±5 V Dual Supply
Figure 15. tON/tOFF Times vs. Temperature
Rev. 0 | Page 10 of 16
100
120
08486-009
0
08486-027
LEAKAGE CURRENT (nA)
–10
08486-030
–800
–10
ADG1401/ADG1402
0
0.030
TA = 25°C
VDD = +15V
VSS = –15V
–20
0.025
–40
0.020
RL = 110Ω
TA = 25°C
0.015
–80
0.010
–100
0.005
–120
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
VDD = 15V, VSS = 15V, VS = 10V p-p
0
0
10k
15k
20k
FREQUENCY (Hz)
Figure 16. Off Isolation vs. Frequency
Figure 18. THD + N vs. Frequency
0
0
TA = 25°C
–10 VDD = +15V
VSS = –15V
TA = 25°C
VDD = +15V
VSS = –15V
–0.5
–20
–1.0
NO DECOUPLING
CAPACITORS
ACPSRR (dB)
–30
–1.5
–2.0
–40
–50
DECOUPLING
CAPACITORS
–60
–2.5
–80
–3.5
–90
–4.0
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1G
Figure 17. On Response vs. Frequency
–100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 19. ACPSRR vs. Frequency
Rev. 0 | Page 11 of 16
10M
08486-006
–70
–3.0
08486-004
INSERTION LOSS (dB)
5k
08486-008
THD + N (%)
–60
08486-005
OFF ISOLATION (dB)
VDD = 5V, VSS = 5V, VS = 5V p-p
ADG1401/ADG1402
TEST CIRCUITS
V
S
ID (ON)
D
NC
S
D
A
08486-019
VS
NC = NO CONNECT
Figure 20. On Resistance
ID (OFF)
S
A
Figure 22. On Leakage
D
A
VS
08486-020
IS (OFF)
VD
Figure 21. Off Leakage
VDD
VSS
0.1µF
VDD
VSS
S
VS
VIN
ADG1401
50%
50%
VIN
ADG1402
50%
50%
VOUT
D
CL
35pF
RL
300Ω
IN
90%
VOUT
90%
GND
tOFF
tON
08486-022
0.1µF
Figure 23. Switching Times, tON and tOFF
VS
VDD
VSS
VDD
VSS
S
D
VIN
CL
1nF
IN
GND
ADG1401
ON
VOUT
VIN
OFF
ADG1402
VOUT
QINJ = CL × ΔVOUT
Figure 24. Charge Injection
Rev. 0 | Page 12 of 16
ΔVOUT
08486-023
RS
VD
08486-021
IDS
ADG1401/ADG1402
VDD
VDD
VSS
0.1µF
0.1µF
VDD
VSS
0.1µF
0.1µF
AUDIO PRECISION
NETWORK
ANALYZER
VSS
VDD
VSS
RS
S
50Ω
IN
S
50Ω
IN
VS
D
GND
VOUT
VIN
GND
OFF ISOLATION = 20 LOG
VOUT
VS
Figure 25. Off Isolation
VDD
Figure 27. THD + N
VSS
0.1µF
VDD
NETWORK
ANALYZER
VSS
S
50Ω
IN
VS
D
RL
50Ω
GND
INSERTION LOSS = 20 LOG
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
08486-025
VIN
RL
10kΩ
Figure 26. Bandwidth
Rev. 0 | Page 13 of 16
VOUT
08486-026
RL
50Ω
08486-024
VIN
0.1µF
VS
V p-p
D
ADG1401/ADG1402
TERMINOLOGY
IDD
The positive supply current.
CD, CS (On)
ISS
The negative supply current.
CIN
The digital input capacitance.
VD (VS)
The analog voltage on Terminal D and Terminal S.
tON
Delay time between the 50% and 90% points of the digital input
and switch on condition. See Figure 23.
The on switch capacitance, measured with reference to ground.
RON
The ohmic resistance between Terminal D and Terminal S.
RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.
tOFF
Delay time between the 50% and 90% points of the digital input
and switch off condition. See Figure 23.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching. See Figure 24.
Off Isolation
A measure of unwanted signal coupling through an off switch.
See Figure 25.
ID (Off)
The drain leakage current with the switch off.
ID, IS (On)
The channel leakage current with the switch on.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
See Figure 26.
VINL
The maximum input voltage for Logic 0.
On Response
The frequency response of the on switch.
VINH
The minimum input voltage for Logic 1.
Insertion Loss
The loss due to the on resistance of the switch. See Figure 26.
IINL (IINH)
The input current of the digital input.
CS (Off)
The off switch source capacitance, measured with reference to
ground.
CD (Off)
The off switch drain capacitance, measured with reference to
ground.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental. See Figure 27.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR measures the ability of a part to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of the
signal on the output to the amplitude of the modulation is the
ACPSRR. See Figure 19.
Rev. 0 | Page 14 of 16
ADG1401/ADG1402
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
6°
0°
0.40
0.25
0.80
0.55
0.40
0.23
0.09
100709-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 28. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
1.75
1.65
1.50
2.00 BSC
5
3.00 BSC
8
1.90
1.80
1.65
EXPOSED
PAD
0.20 MIN
4
INDEX
AREA
0.50
0.40
0.30
TOP VIEW
0.80
0.75
0.70
0.30
0.25
0.20
0.50
COPLANARITY
0.08
0.05 MAX
0.02 NOM
PIN 1
INDICATOR
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
081806-A
SEATING
PLANE
0.15 REF
SIDE VIEW
1
Figure 29. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 2 mm Body, Very Very Thin, Dual Lead
(CP-8-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG1401BRMZ1
ADG1401BRMZ-REEL71
ADG1401BCPZ-REEL71
ADG1402BRMZ1
ADG1402BRMZ-REEL71
ADG1402BCPZ-REEL71
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
Z = RoHS Compliant Part.
Rev. 0 | Page 15 of 16
Package Option
RM-8
RM-8
CP-8-4
RM-8
RM-8
CP-8-4
Branding
S2T
S2T
2Y
S2U
S2U
1F
ADG1401/ADG1402
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08486-0-10/09(0)
Rev. 0 | Page 16 of 16