CREATING, ACQUIRING AND
INTEGRATING REUSABLE IP
Prof. Don Bouldin, Ph.D.
Electrical & Computer Engineering
University of Tennessee
Knoxville, TN 37996-2100
dbouldin@tennessee.edu
IEEE Boston
14 November 2007
http://vlsi1.engr.utk.edu/~bouldin/boston
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OUTLINE OF THIS PRESENTATION
• Design Productivity
• Intellectual Property Blocks
• Reuse Requirements
• The Changing Design Environment
• Acquiring IP Blocks
• Quality IP Metrics
• Collaborative Design
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ELECTRONIC PRODUCTS ARE
PERVASIVE AND ALWAYS IMPROVING
Moore’s
Moore’s Law:
Law: Every
Every 18
18 months
months integrated
integrated circuit
circuit manufacturing
manufacturing can
can produce
produce
2X
performance
for
the
same
price
or
the
same
performance
for
half
2X performance for the same price or the same performance for half the
the price.
price.
Price
Price
$1000--1X
$1000--1X
$1000--2X
$1000--2X
$500--1X
$500--1X
Performance
Performance
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A DESIGN PRODUCTIVITY CRISIS
WAS PREDICTED A DECADE AGO
10,000,000
100,000,000
Logic Tr./Chip
Tr./S.M.
1,000,000
100,000
10,000,000
1,000,000
58%/Yr. Compounded
Complexity growth rate
10,000
100,000
10,000
1,000
100
xx
21%/Yr. Compounded
Productivity growth rate
x
1,000
100
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
1
x
x
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xx
Productivity
Trans./Staff-Mo.
Logic Transistors per Chip
(K)
The Impending Design Productivity Crisis
Source: SEMATECH
Maya Rubeiz
USAF Wright Labs
maya.rubeiz@sn.wpafb.af.mil
http://rassp.scra.org
1997
44
DESIGN PRODUCTIVITY
HAS PROGRESSED RECENTLY
• 1947
• 3 Nobel Laureates
• 1 Transistor
• 2007
• 3 ECE Students
• 4M Transistors
Progress has been enabled by raising the
level of abstraction and reusing
previous sub-systems or blocks.
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66
WE BUILD SKYSCRAPERS USING
STANDARDIZED BLOCKS
So, let’s use standardized blocks to build systems
Sears
Sears Tower,
Tower, Chicago
Chicago
www.lego.com
www.lego.com
77
INTELLECTUAL PROPERTY BLOCKS
Design #1 without
Planned Reuse
Design #2 without
Planned Reuse
1.8
1.5
Design # 1 For Reuse
Design #2
WITH IP
IP blocks should have well-defined interfaces
Design #3 without
Planned Reuse
2.1
Design #3
WITH IP
Often, IP are more like patches that must be
stitched together like a quilt
88
IP IS CREATED USING A HARDWARE
DESCRIPTION LANGUAGE OR HDL
CASE y IS
WHEN A =>
IF w = '0' THEN y <= A ;
ELSE y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN y <= A ;
ELSE y <= C ;
END IF ;
WHEN C =>
IF w = '0' THEN y <= A ;
ELSE y <= C ;
END IF ;
END CASE ;
99
AN HDL DESIGN CAN BE TARGETED
TO MULTIPLE LAYOUTS
architecture behavior of control is
if left_paddle then
n_state <= hit_state
elsif n_state <= miss_state
end if;
SYNTHESIS
SCHEMATIC--A
TECH
A
AND
AND
LIBRARIES
SYNPLIFY_PRO
SYNPLIFY_PRO
HDL
OR
TECH
A
TECH
B
SCHEMATIC--B
OR
AND
OR
ALTERA
PLACE & ROUTE
XILINX
PLACE & ROUTE
PHYSICAL LAYOUT
PHYSICAL LAYOUT
TECH
B
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10
REQUIREMENTS FOR REUSABLE IP
• BASICS:
– HDL Models
– Functional Description
– Application Intent
– Interface
Specifications
– Authors and Owners
– Size, Delay, Power
Estimates
– Packaging Info
• ALSO NEED:
– Test Bench
(Input Stimuli/Output
Responses
– Tools and Versions
Used/Needed
– Foundry Used For Fab
– Size, Delay, Power
Measurements
– Testability Features
(BIST, JTAG, SCAN)
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11
THE DESIGN METHOD HAS CHANGED
CUSTOMER
Requirements
UNCHANGED
UNCHANGED
DESIGNER
Specifications
OLD
OLD METHOD
METHOD
NEW
NEW METHOD
METHOD
1.
Select ICs
1.
Select PCB with ICs
2.
Design/Fab PCB
2.
Select blocks for new IC
3.
Design blocks for new IC
3.
Design missing blocks
4.
Integrate blocks
4.
Integrate blocks
5.
System Integration
5.
System Integration
12
12
IP CAN ATTRACT BUSINESS AND
REDUCE RISK AND TIME-TO-MARKET
CUSTOMER
IP
Design Center
IP
Foundry
ASIC/FPGA
13
13
AN OPEN COMPETITIVE
MARKET EXISTS
CUSTOMER
PORTABLE IP
(Multiple
Suppliers)
REPOSITORY
Standards:
www.design-reuse.com
www.vsia.org
www.ieee.org
Foundry
Foundry
Foundry
ASIC/FPGA
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14
FREE OPEN-SOURCE CORES
• LEON is an open-source 32-bit
SPARC V8 CPU that was developed
by the European Space Agency and
is available for free at
www.gaisler.com
•• Other
Other cores
cores at
at www.opencores.org
www.opencores.org
–USB
–USB 2.0
2.0
–Ethernet
–Ethernet MAC
MAC
–DES/AES
–DES/AES Encryption
Encryption
–FIR/IIR
–FIR/IIR Filters
Filters
–Floating
–Floating Point
Point Unit
Unit
15
15
QUALITY INTELLECTUAL PROPERTY
• The VSI (Virtual Socket Interface) Alliance (VSIA) is
an open, international organization that includes
representatives from all segments of the SoC
industry: System houses, Semiconductor vendors,
Electronic Design Automation (EDA) companies, and
Intellectual Property (IP) providers. VSIA's mission
is to dramatically enhance the productivity of the SoC
design community.
• Quality Intellectual Property (QIP) Metric v3.0 is
available for free from the VSIA website:
www.vsia.org
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16
QIP METRICS
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17
DEVELOPING QUALITY IP
• Requirements should be mapped into an executable specification
which produces the desired golden reference responses.
• HDL and FPGA responses must match the golden responses
identically.
STIMULI
MATLAB or C
(fixed point)
RESPONSES
(golden ref.)
HDL SOURCE CODE
RESPONSES
(simulation)
FPGA
RESPONSES
(system)
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18
THE TESTBENCH CONTAINS THE
STIMULI, RESPONSES AND UUT
• Functional stimuli are developed by the designer to
mimic the system environment.
• The tester is written in HDL but is not synthesized
into the FPGA.
Testbench
Testbench (Tester
(Tester +
+ HDL
HDL Source
Source Code)
Code)
Tester
Tester
STIMULI
(manual)
HDL SOURCE CODE
RESPONSES
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19
RAPID VERIFICATION SAVES TIME
• Minimizing time-to-market encourages designers to develop only a
few tests for simulation and then proceed to testing the design
inside the FPGA in its real-world environment. The FPGA executes
tests 500x faster than the simulator and the real-world system
environment produces the tests automatically.
Tester
Tester
STIMULI
(manual)
HDL SOURCE CODE
RESPONSES
SIMULATION
REAL-WORLD SYSTEM ENVIRONMENT
STIMULI
(auto)
FPGA
RESPONSES
(actual)
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20
CONTROLLABILITY AND
OBSERVABILITY AID DEBUGGING
• When errors are encountered on the FPGA board where
tests are limited to the primary inputs and primary outputs,
the designer can return to simulation where complete
controllability and observability of all of the internal nodes
are available for debugging.
Primary
Inputs
Logic
Primary
Inputs
Gate
Logic
Gate
Primary
Outputs
Logic
Primary
Gate
Output
Internal
Nodes
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21
POLISHING FOR REUSE
• Once the HDL source code has been verified in the FPGA, the
design can be polished for reuse.
• This involves documenting the HDL and providing test access
mechanisms for reuse as an embedded core per IEEE 1500:
http://grouper.ieee.org/groups/1500
• Also, the tester code should be enhanced with assertion-based
tests to achieve the desired HDL code coverage.
• Constrained, random-generated tests can be produced
automatically for large HDL cores.
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22
COVERAGE-DRIVEN TESTS
The simulator can produce coverage reports and
identify missed statements in the code.
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ASSERTION-BASED VERIFICATION
The
The tester
tester code
code should
should include
include stimuli
stimuli and
and responses.
responses.
“Failure” stops simulation while “warning” does not.
“Note” is used to document a correct response.
wait_clock(16);
wait_clock(16);
IF
IF (left_seg
(left_seg =
= X"6")
X"6")
--- check
check second
second state
state of
of 7-segment
7-segment display
display
THEN
THEN
ASSERT
ASSERT false
false
REPORT
REPORT "Output
"Output signals
signals set
set correctly
correctly (7-segment
(7-segment second
second state)"
state)"
SEVERITY
SEVERITY note;
note;
ELSE
ELSE
ASSERT
ASSERT false
false
REPORT
REPORT "Output
"Output not
not set
set correctly
correctly (7-segment
(7-segment second
second state)"
state)"
SEVERITY
SEVERITY warning;
warning;
END
END IF;
IF;
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BUILT-IN SELF-TEST CODE
• The HDL source code can be augmented with Built-In Self-Test
(BIST) code.
• BIST code can verify that the I/O and other likely failure
modes are working properly or not.
• BIST code can also include functional test cases to assure
proper operation before execution or during “idle” times.
25
25
GRAPHICAL TOOLS CAN REUSE
AND CREATE IP BLOCKS
• Library cells (basic IP blocks) are integrated
into a larger block that itself can be reused.
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ACQUIRING IP
• STAR IP:
Blocks requiring 100+ staff years to design (like
ARM, MIPS ) have become bestsellers and come
with lots of support.
• Small IP:
Blocks requiring 1-2 staff years to design are
priced at 1/3 of the development cost.
Buyers are skeptical about the value and often
prefer to do these in-house.
• Medium IP:
Blocks requiring 5-10 staff years are profitable
for both seller and buyer. However, some
suppliers have been bought by foundries to add
to the foundries’ captive portfolios.
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ONCE UPON A TIME
Pastor
Snowy Road
Church
County
Road Dept.
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THE GLOBAL ECONOMY
The Earth is NOT
……. Flat
Boston or Bangalore or Knoxville
Actually, we live on a small planet.
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COLLABORATIVE DESIGN
Designer#1
Designer#3
Designer#2
Designer#4
Collaborative Design of a System-on-Chip
http://www.cs.wright.edu/~tkprasad/courses/soc.html
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DESIGN-FOR-REUSE and
DESIGN-WITH-REUSE
TEAM
APPLICATION REQUIREMENTS
PROJECT
DESIGN
FOR
HDL
HDL
HDL
HDL
FPGA
FPGA
FPGA
FPGA
REUSE
VERIFICATION
DESIGN WITH REUSE
SoC
SYSTEM INTEGRATION
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SUMMARY AND CONCLUSIONS
• Design Productivity
• Intellectual Property Blocks
• Reuse Requirements
• The Changing Design Environment
• Acquiring IP Blocks
• Quality IP Metrics
• Collaborative Design
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