Triple, 200 mA, Low Noise,
High PSRR Voltage Regulator
ADP320
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUITS
2.5V TO VBIAS
5.5V
1.8V TO VIN1/VIN2
5.5V
ADP320
+
+
VBIAS
1µF
1µF
EN1
LDO 1
ON
EN LD1
OFF
VOUT1
+
1µF
VBIAS
EN2
ON
OFF
LDO 2
EN LD2
VOUT2
+
1µF
VBIAS
1.8V TO VIN3
5.5V
+
1µF
EN3
ON
OFF
LDO 3
EN LD3
VOUT3
+
1µF
GND
09874-001
Bias voltage range (VBIAS): 2.5 V to 5.5 V
LDO input voltage range (VIN1/VIN2, VIN3): 1.8 V to 5.5 V
Three 200 mA low dropout voltage regulators
16-lead, 3 mm × 3 mm LFCSP
Initial accuracy: ±1%
Stable with 1 μF ceramic output capacitors
No noise bypass capacitor required
3 independent logic controlled enables
Over current and thermal protection
Key specifications
High PSRR
76 dB PSRR up to 1 kHz
70 dB PSRR 10 kHz
60 dB PSRR at 100 kHz
40 dB PSRR at 1 MHz
Low output noise
24 μV rms typical output noise at VOUT = 1.2 V
43 μV rms typical output noise at VOUT = 2.8 V
Excellent transient response
Low dropout voltage: 110 mV @ 200 mA load
85 μA typical ground current at no load, all LDOs enabled
100 μs fast turn-on circuit
Guaranteed 200 mA output current per regulator
−40°C to +125°C junction temperature
Figure 1. Typical Application Circuit
APPLICATIONS
Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
Portable medical devices
Post dc-to-dc regulation
GENERAL DESCRIPTION
The ADP320 200 mA triple output LDO combines high PSRR, low
noise, low quiescent current, and low dropout voltage in a voltage
regulator ideally suited for wireless applications with demanding
performance and board space requirements.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP320 triple LDO extend the battery life of
portable devices. The ADP320 triple LDO maintains power supply
rejection greater than 60 dB for frequencies as high as 100 kHz
while operating with a low headroom voltage. The ADP320 triple
Rev. B
LDO offers much lower noise performance than competing LDOs
without the need for a noise bypass capacitor.
The ADP320 triple LDO is available in a miniature 16-lead
3 mm × 3 mm LFCSP package and is stable with tiny 1 μF ±30%
ceramic output capacitors, resulting in the smallest possible board
area for a wide variety of portable power needs.
The ADP320 triple LDO is available in output voltage combinations ranging from 0.8 V to 3.3 V and offers over current and
thermal protection to prevent damage in adverse conditions.
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ADP320
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 15
Applications ....................................................................................... 1
Applications Information .............................................................. 16
Typical Application Circuits............................................................ 1
ADIsimPower Design Tool ....................................................... 16
General Description ......................................................................... 1
Capacitor Selection .................................................................... 16
Revision History ............................................................................... 2
Undervoltage Lockout ............................................................... 17
Specifications..................................................................................... 3
Enable Feature ............................................................................ 17
Input and Output Capacitor, Recommended Specifications .. 4
Current-Limit and Thermal Overload Protection ................. 18
Absolute Maximum Ratings ............................................................ 5
Thermal Considerations............................................................ 18
Thermal Resistance ...................................................................... 5
Printed Circuit Board Layout Considerations........................ 20
ESD Caution .................................................................................. 5
Outline Dimensions ....................................................................... 21
Pin Configurations and Function Descriptions ........................... 6
Ordering Guide .......................................................................... 21
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
11/14—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Figure 28, Figure 29, Figure 30, and Figure 31;
Added Figure 32; Renumbered Sequentially .............................. 11
Added Figure 33 and Figure 34; Changes to Figure 36,
Figure 37, and Figure 38 ................................................................ 12
Added Figure 39.............................................................................. 13
Added ADIsimPower Design Tool Section ................................. 16
4/11—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 20
6/10—Revision 0: Initial Version
Rev. B | Page 2 of 21
Data Sheet
ADP320
SPECIFICATIONS
VIN1/VIN2 = VIN3 = (VOUT + 0.5 V) or 1.8 V (whichever is greater), VBIAS = 2.5 V, EN1, EN2, EN3 = VBIAS, IOUT1 = IOUT2 = IOUT3 = 10 mA,
CIN = COUT1 = COUT2 = COUT3 = 1 µF, and TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT BIAS VOLTAGE RANGE
INPUT LDO VOLTAGE RANGE
GROUND CURRENT WITH ALL
REGULATORS ON
Symbol
VBIAS
VIN1/VIN2/ VIN3
IGND
Conditions
TJ = −40°C to +125°C
TJ = −40°C to +125°C
IOUT = 0 µA
Min
2.5
1.8
IBIAS
SHUTDOWN CURRENT
IGND-SD
OUTPUT VOLTAGE ACCURACY
VOUT
LINE REGULATION
∆VOUT/∆VIN
LOAD REGULATION1
∆VOUT/∆IOUT
DROPOUT VOLTAGE2
VDROPOUT
Max
5.5
5.5
Unit
V
V
µA
160
µA
µA
µA
µA
µA
µA
µA
µA
µA
%
%
85
IOUT = 0 µA, TJ = −40°C to +125°C
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 200 mA
IOUT = 200 mA, TJ = −40°C to +125°C
INPUT BIAS CURRENT
Typ
120
220
250
380
66
TJ = −40°C to +125°C
EN1 = EN2 = EN3 = GND
EN1 = EN2 = EN3 = GND, TJ = −40°C to +125°C
100 µA < IOUT < 200 mA, VIN = (VOUT + 0.5 V) to 5.5 V,
TJ = −40°C to +125°C
VIN = (VOUT + 0.5 V) to 5.5 V
VIN = (VOUT + 0.5 V) to 5.5 V, TJ = −40°C to +125°C
IOUT = 1 mA to 200 mA
IOUT = 1 mA to 200 mA, TJ = −40°C to +125°C
VOUT = 3.3 V
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 200 mA
IOUT = 200 mA, TJ = −40°C to +125°C
VOUT = 3.3 V, all VOUT initially off, enable one
VOUT = 0.8 V
VOUT = 3.3 V, one VOUT initially on, enable second
VOUT = 0.8 V
START-UP TIME3
TSTART-UP
CURRENT LIMIT THRESHOLD4
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
EN INPUT
EN Input Logic High
EN Input Logic Low
EN Input Leakage Current
ILIMIT
TSSD
TSSD-HYS
TJ rising
VIH
VIL
VI-LEAKAGE
2.5 V ≤ VBIAS ≤ 5.5 V
2.5 V ≤ VBIAS ≤ 5.5 V
EN1 = EN2 = EN3 = VIN or GND
EN1 = EN2 = EN3 = VIN or GND, TJ = −40°C to +125°C
UNDERVOLTAGE LOCKOUT
Input Bias Voltage (VBIAS) Rising
Input Bias Voltage (VBIAS) Falling
Hysteresis
OUTPUT NOISE
UVLO
UVLORISE
UVLOFALL
UVLOHYS
OUTNOISE
140
0.1
2.5
+1
+2
−1
−2
0.01
−0.03
+0.03
0.001
0.005
6
9
110
170
250
240
100
160
20
360
600
155
15
°C
°C
1.2
0.4
0.1
1
2.45
2.0
10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V
10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.8 V
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 2.5 V
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.2 V
Rev. B | Page 3 of 21
180
50
43
40
24
%/ V
%/ V
%/mA
%/mA
mV
mV
mV
mV
mV
µs
µs
µs
µs
mA
V
V
µA
µA
V
V
mV
µV rms
µV rms
µV rms
µV rms
ADP320
Parameter
POWER SUPPLY REJECTION RATIO
Data Sheet
Symbol
PSRR
Conditions
VIN = 1.8 V, VOUT = 0.8 V, IOUT = 100 mA
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
VIN = 3.3 V, VOUT = 2.8 V, IOUT = 100 mA
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
Min
Typ
Max
Unit
70
70
70
60
40
dB
dB
dB
dB
dB
68
62
68
60
40
dB
dB
dB
dB
dB
Based on an end-point calculation using 1 mA and 200 mA loads.
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 1.8 V.
3
Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 90% of its nominal value.
4
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
1
2
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
MINIMUM INPUT AND OUTPUT CAPACITANCE1
CAPACITOR ESR
1
Symbol
CMIN
RESR
Conditions
TA = −40°C to +125°C
TA = −40°C to +125°C
Min
0.70
0.001
Typ
Max
1
Unit
µF
Ω
The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with LDOs.
Rev. B | Page 4 of 21
Data Sheet
ADP320
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN1/VIN2, VIN3, VBIAS to GND
VOUT1, VOUT2 to GND
VOUT3 to GND
EN1, EN2, EN3 to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
–0.3 V to +6.5 V
–0.3 V to VIN1/VIN2
–0.3 V to VIN3
–0.3 V to +6.5 V
–65°C to +150°C
–40°C to +125°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP320 triple LDO can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature (TJ)
is within the specified temperature limits. In applications
with high power dissipation and poor thermal resistance the
maximum ambient temperature may have to be derated. In
applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits.
The junction temperature (TJ) of the device is dependent on
the ambient temperature (TA), the power dissipation of the
device (PD), and the junction-to-ambient thermal resistance of
the package (θJA). Maximum junction temperature (TJ) is
calculated from the ambient temperature (TA) and power dissipation (PD) using the following formula:
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a four-layer, 4-inch × 3-inch
circuit board. Refer to JEDEC JESD 51-9 for detailed information on the board construction. For additional information, see
the AN-617 Application Note, MicroCSP™ Wafer Level Chip
Scale Package.
ΨJB is the junction to board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information, states
that thermal characterization parameters are not the same as
thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation
from the package; factors that make ΨJB more useful in realworld applications. Maximum junction temperature (TJ) is
calculated from the board temperature (TB) and power
dissipation (PD) using the following formula
TJ = TB + (PD × ΨJB)
Refer to JEDEC JESD51-8 and JESD51-12 for more detailed
information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4.
Package Type
16-Lead 3 mm × 3 mm LFCSP
ESD CAUTION
Rev. B | Page 5 of 21
θJA
49.5
ΨJB
25.2
Unit
°C/W
ADP320
Data Sheet
13 NC
EN1 1
12 GND
VBIAS 2
11 GND
ADP320
VIN1/VIN2 3
10 VIN3
VIN1/VIN2 4
VIN3
NC 8
VOUT3 7
VOUT2 6
VOUT1 5
9
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
2. CONNECT EXPOSED PAD TO GROUND PLANE.
09874-002
14 NC
16 EN2
15 EN3
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
EN1
2
3
VBIAS
VIN1/VIN2
4
VIN1/VIN2
5
6
7
8
9
10
11
12
13
14
15
VOUT1
VOUT2
VOUT3
NC
VIN3
VIN3
GND
GND
NC
NC
EN3
16
EN2
EP
EP
Description
Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For
automatic startup, connect EN1 to VBIAS.
Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 μF or greater capacitor.
Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 μF or
greater capacitor.
Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 μF or
greater capacitor.
Regulated Output Voltage 1. Connect a 1 μF or greater output capacitor between VOUT1 and GND.
Regulated Output Voltage 2. Connect a 1 μF or greater output capacitor between VOUT2 and GND.
Regulated Output Voltage 3. Connect a 1 μF or greater output capacitor between VOUT3 and GND.
Not connected internally.
Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 μF or greater capacitor.
Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 μF or greater capacitor.
Ground Pin.
Ground Pin.
Not connected internally.
Not connected internally.
Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For
automatic startup, connect EN3 to VBIAS.
Enable Input for Regulator 2. Drive EN1 high to turn on Regulator 2; drive it low to turn off Regulator 2. For
automatic startup, connect EN2 to VBIAS.
Exposed pad for enhanced thermal performance. Connect to copper ground plane.
Rev. B | Page 6 of 21
Data Sheet
ADP320
TYPICAL PERFORMANCE CHARACTERISTICS
VIN1/VIN2 = VIN3 =VBIAS = 4 V, VOUT1 = 3.3 V, VOUT2 = 1.8 V, VOUT3 = 1.5 V, IOUT = 10 mA, CIN = COUT1 = COUT2 = COUT3 = 1 µF, TA = 25°C,
unless otherwise noted.
3.33
1.820
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
3.32
1.815
1.810
1.805
VOUT (V)
VOUT (V)
3.31
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
1.800
3.30
1.795
3.29
1.790
3.28
–40
125
85
25
–5
1.780
09874-003
3.27
TJ (°C)
1.820
3.315
1.815
VOUT (V)
125
3.310
1.810
100
10
1000
ILOAD (mA)
1.800
09874-004
1
Figure 7. Output Voltage vs. Load Current, VRIPPLE = 50 mV, COUT = 1 µF
1.820
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
1.815
VOUT (V)
3.315
3.310
3.305
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
1.810
1.805
3.8
4.0
4.2
4.4
4.6
VIN (V)
4.8
5.0
5.2
5.4
1.800
2.1
09874-005
3.300
3.6
1000
100
ILOAD (mA)
Figure 4. Output Voltage vs. Load Current, VRIPPLE = 50 mV, COUT = 1 µF
3.320
10
1
09874-007
1.805
3.305
2.5
2.9
3.3
3.7
VIN (V)
Figure 5. Output Voltage vs. Input Voltage, VRIPPLE = 50 mV, COUT = 1 µF
4.1
4.5
4.9
5.3
09874-008
VOUT (V)
85
Figure 6. Output Voltage vs. Junction Temperature, VRIPPLE = 50 mV, COUT = 1 µF
3.320
VOUT (V)
25
–5
TJ (°C)
Figure 3. Output Voltage vs. Junction Temperature, VRIPPLE = 50 mV, COUT = 1 µF
3.300
–40
09874-006
1.785
Figure 8. Output Voltage vs. Input Voltage, VRIPPLE = 50 mV, COUT = 1 µF
Rev. B | Page 7 of 21
ADP320
Data Sheet
1.520
1.500
1.495
1.490
60
40
–5
85
25
0
09874-009
–40
125
TJ (°C)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
25
–5
–40
85
125
TJ (°C)
Figure 9. Output Voltage vs. Junction Temperature, VRIPPLE = 50 mV, COUT = 1 µF
Figure 12. Ground Current vs. Junction Temperature, Single Output Loaded,
VRIPPLE = 50 mV, COUT = 1 µF
120
1.510
100
GROUND CURRENT (µA)
1.508
VOUT (V)
1.506
1.504
1.502
80
60
40
10
1
100
1000
ILOAD (mA)
Figure 10. Output Voltage vs. Load Current, VRIPPLE = 50 mV, COUT = 1 µF
1.508
VOUT (V)
1.502
3.40
3.80
VIN (V)
4.20
4.60
5.00
5.40
80
60
40
0
1.8
09874-011
3.00
1000
Figure 13. Ground Current vs. Load Current, Single Output Loaded,
VRIPPLE = 50 mV, COUT = 1 µF
20
2.60
100
100
1.504
2.20
10
120
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
1.506
1.500
1.80
1
ILOAD (mA)
GROUND CURRENT (µA)
1.510
0
09874-013
20
09874-010
1.500
80
20
1.485
1.480
100
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
2.2
2.6
3.0
3.4
3.8
VIN (V)
Figure 11. Output Voltage vs. Input Voltage, VRIPPLE = 50 mV, COUT = 1 µF
Rev. B | Page 8 of 21
4.2
4.6
5.0
5.4
09874-014
VOUT (V)
1.505
09874-012
1.510
120
GROUND CURRENT (µA)
1.515
140
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
Figure 14. Ground Current vs. Input Voltage, Single Output Loaded,
VRIPPLE = 50 mV, COUT = 1 µF
Data Sheet
ADP320
350
120
100
200
150
100
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
50
0
–5
–40
85
25
80
60
40
125
TJ (°C)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
20
0
–40
–5
85
25
09874-018
BIAS CURRENT (µA)
250
09874-015
GROUND CURRENT (µA)
300
125
TJ (°C)
Figure 18. Bias Current vs. Junction Temperature, Single Output Loaded,
VRIPPLE = 50 mV, COUT = 1 µF
Figure 15. Ground Current vs. Junction Temperature,
All Outputs Loaded Equally, VRIPPLE = 50 mV, COUT = 1 µF
100
300
90
80
BIAS CURRENT (µA)
GROUND CURRENT (µA)
250
200
150
100
70
60
50
40
30
20
50
10
100
1000
TOTAL LOAD CURRENT (mA)
0
250
74
BIAS CURRENT (µA)
76
200
150
100
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
2.1
2.5
2.9
1000
72
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
70
68
66
3.3
3.7
VIN (V)
4.1
4.5
4.9
5.3
64
2.5
09874-017
0
1.7
100
Figure 19. Bias Current vs. Load Current, Single Output Load,
VRIPPLE = 50 mV, COUT = 1 µF
300
50
10
ILOAD (mA)
Figure 16. Ground Current vs. Load Current, All Outputs Loaded Equally,
VRIPPLE = 50 mV, COUT = 1 µF
GROUND CURRENT (µA)
1
2.9
3.3
3.7
4.1
4.5
4.9
5.3
VIN (V)
Figure 17. Ground Current vs. Input Voltage, All Outputs Loaded Equally,
VRIPPLE = 50 mV, COUT = 1 µF
Rev. B | Page 9 of 21
Figure 20. Bias Current vs. Input Voltage, Single Output Load,
VRIPPLE = 50 mV, COUT = 1 µF
09874-020
1
09874-016
0
09874-019
10
ADP320
0.7
300
0.6
0.5
0.4
0.3
250
200
150
100
0.2
50
0.1
–25
0
25
50
75
100
125
TEMPERATURE (°C)
0
3.10
09874-021
0
–50
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
VIN (V)
Figure 21. Shutdown Current vs. Temperature at Various Input Voltages,
VRIPPLE = 50 mV, COUT = 1 µF
09874-024
SHUTDOWN CURRENT (µA)
0.8
350
3.6
3.8
4.2
4.4
4.8
5.5
GROUND CURRENT (µA)
0.9
Data Sheet
Figure 24. Ground Current vs. Input Voltage (in Dropout), VOUT1 = 3.3 V,
VRIPPLE = 50 mV, COUT = 1 µF
300
100
90
250
80
DROPOUT (mV)
DROPOUT (mV)
70
60
50
40
30
200
150
100
20
50
1
10
100
1000
LOAD (mA)
3.25
1000
1.85
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
1.80
1.75
1.70
VOUT (V)
3.15
1.65
3.10
1.60
3.05
1.55
3.00
1.50
3.15
3.20
3.25
3.30
3.35
3.40
3.45
VIN (V)
3.50
09874-023
VOUT (V)
100
LOAD (mA)
3.20
2.95
3.10
10
Figure 23. Output Voltage vs. Input Voltage (In Dropout),
VOUT1 = 3.3 V, VRIPPLE = 50 mV, COUT = 1 µF
1.45
1.70
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
1.80
1.90
2.00
2.10
VIN (V)
Figure 26. Output Voltage vs. Input Voltage (in Dropout),
VOUT2 = 1.8 V, VRIPPLE = 50 mV, COUT = 1 µF
Rev. B | Page 10 of 21
09874-026
3.30
1
Figure 25. Dropout Voltage vs. Load Current and Output Voltage,
VOUT2 = 1.8 V, VRIPPLE = 50 mV, COUT = 1 µF
Figure 22. Dropout Voltage vs. Load Current and Output Voltage,
VOUT1 = 3.3 V, VRIPPLE = 50 mV, COUT = 1 µF
3.35
0
09874-022
0
09874-025
10
ADP320
160
0
140
–10
–30
PSRR (dB)
100
80
60
–70
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
1.80
–80
–90
1.90
2.00
2.10
VIN (V)
–100
–30
–30
–40
–40
PSRR (dB)
–20
–50
–60
–80
–80
–90
–90
–100
–100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–40
PSRR (dB)
–30
–40
–50
–60
–80
–80
–90
–90
1k
10k
FREQUENCY (Hz)
100k
1M
10M
100
1k
10k
100k
1M
10M
–60
–70
100
10
–50
–70
09874-129
PSRR (dB)
–30
10
10M
10mA
100mA
200mA
–10
–20
1
1
0
–20
–100
1M
Figure 31. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V,
VIN = 3.8 V, VRIPPLE = 50 mV, COUT = 1 µF
10mA
100mA
200mA
–10
100k
FREQUENCY (Hz)
Figure 28. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.8 V,
VIN = 2.8 V, VRIPPLE = 50 mV, COUT = 1 µF
0
10k
–60
–70
100
1k
–50
–70
10
100
10mA
100mA
200mA
–10
09874-028
PSRR (dB)
0
–20
1
10
Figure 30. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V,
VIN = 4.3 V, VRIPPLE = 50 mV, COUT = 1 µF
10mA
100mA
200mA
–10
1
FREQUENCY (Hz)
Figure 27. Ground Current vs. Input Voltage in Dropout), VOUT2 = 1.8 V,
VRIPPLE = 50 mV, COUT = 1 µF
0
–60
09874-029
0
1.70
–50
09874-131
20
–40
Figure 29. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.8 V,
VIN = 2.3 V, VRIPPLE = 50 mV, COUT = 1 µF
–100
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
10M
09874-030
40
10mA
100mA
200mA
–20
120
09874-027
GROUND CURRENT (µA)
Data Sheet
Figure 32. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.5 V,
VIN = 2.5 V, VRIPPLE = 50 mV, COUT = 1 µF
Rev. B | Page 11 of 21
ADP320
0
Data Sheet
10k
–10
NOISE SPECTRAL DENSITY (nV/√Hz)
10mA
100mA
200mA
–20
PSRR (dB)
–30
–40
–50
–60
–70
–80
1.5V
1.8V
2.5V
3.3V
1k
100
10
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
1
09874-133
1
100
1k
10k
100k
1M
10M
Figure 36. Output Noise Spectral Density, VIN = 5 V, ILOAD = 10 mA,
VRIPPLE = 50 mV, COUT = 1 µF
50
10mA
100mA
200mA
–10
10
FREQUENCY (Hz)
Figure 33. Power Supply Rejection Ratio vs. Frequency, VOUT= 1.5 V,
VIN = 2.0 V, VRIPPLE = 50 mV, COUT = 1 µF
0
1
09874-032
–90
–100
–20
40
NOISE (µV rms)
PSRR (dB)
–30
–40
–50
–60
30
1.5V
1.8V
2.5V
3.3V
20
–70
–80
10
10
100
1k
100k
10k
1M
10M
FREQUENCY (Hz)
Figure 34. Power Supply Rejection Ratio vs. Frequency, VOUT= 1.2 V,
VIN = 2.2 V, VRIPPLE = 50 mV, COUT = 1 µF
–20
0.1
1
10
100
1000
Figure 37. 10 Hz to 100 kHz Output Noise vs. Load Current and Output Voltage,
VIN = 5 V, VRIPPLE = 50 mV, COUT = 1 µF
50
1V HEADROOM
1.8V PSRR
1.2 XTALK
40
–40
–50
–60
30
20
1.5V
1.8V
2.5V
3.3V
–70
–80
10
–100
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 35. Power Supply Rejection Ratio vs. Frequency,
Channel to Channel Crosstalk, VRIPPLE = 50 mV, COUT = 1 µF
0
0.001
0.01
0.1
1
10
LOAD CURRENT (mA)
100
1000
09874-138
–90
09874-031
PSRR (dB)
–30
1.8V/200mA
1.8V/100mA
1.8V/10mA
1.2V/200mA
1.2V/100mA
1.2V/10mA
0.01
LOAD CURRENT (mA)
NOISE (µV rms)
0
–10
0
0.001
09874-134
1
09874-033
–90
–100
Figure 38. 100 Hz to 100 kHz Output Noise vs. Load Current and Output Voltage,
VIN = 5 V, VRIPPLE = 50 mV, COUT = 1 µF
Rev. B | Page 12 of 21
Data Sheet
ADP320
50
ILOAD2
NOISE (µV rms)
40
1
30
1µA
10µA
100µA
1mA
10mA
100mA
200mA
20
VOUT2
2
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
OUTPUT VOLTAGE (V)
CH1 200mA Ω
B
W
B
W
M40µs
A CH1
84mA
T 10.4%
Figure 39. Output Noise vs. Output Voltage, Different Load Currents, VIN = 5 V,
VRIPPLE = 50 mV, COUT = 1 µF
Figure 42. Load Transient Response,
ILOAD2 = 1 mA to 200 mA, COUT2 = 1 μF,
CH1 = ILOAD2, CH2 = VOUT2, VRIPPLE = 50 mV, COUT = 1 µF
ILOAD3
ILOAD1
1
1
2
CH2 50mV
09874-036
0
0.8
09874-139
10
VOUT1
VOUT3
2
VOUT2
3
CH1 100mA Ω
CH3 10mV
B
B
W
W
CH2 50mV
CH4 10mV
B
B
W
W
M40µs A CH1
T 9.8%
44mA
CH1 200mA Ω
B
W
CH2 50mV
B
W
M40µs A CH1
T 10.2%
124mA
Figure 40. Load Transient Response,
ILOAD1 = 1 mA to 200 mA, ILOAD2 = ILOAD3 = 1 mA,CH1 = ILOAD1,
CH2 = VOUT1, CH3 = VOUT2 , CH4 = VOUT3, VRIPPLE = 50 mV, COUT = 1 µF
Figure 43. Load Transient Response,
ILOAD3 = 1 mA to 200 mA, COUT3 = 1 μF,
CH1 = ILOAD3, CH2 = VOUT3, VRIPPLE = 50 mV, COUT = 1 µF
ILOAD1
VIN
09874-037
VOUT3
09874-034
1
1
VOUT1
2
VOUT1
2
VOUT2
3
VOUT3
CH1 200mA Ω
B
W
CH2 50mV
B
W
M40µs
A CH1
124mA
T 10.2%
09874-035
4
CH1 1V
CH3 10mV
B
W
B
W
CH2 10mV
CH4 10mV
B
B
W
M1µs
W
T 15%
A CH1
4.62V
Figure 44. Line Transient Response,
VIN = 4 V to 5 V, ILOAD1 = ILOAD2 = ILOAD3 =100 mA,
CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3,
VRIPPLE = 50 mV, COUT = 1 µF
Figure 41. Load Transient Response,
ILOAD1 = 1 mA to 200 mA, COUT1 = 1 μF,
CH1 = ILOAD1, CH2 = VOUT1, VRIPPLE = 50 mV, COUT = 1 µF
Rev. B | Page 13 of 21
09874-038
4
ADP320
Data Sheet
VIN
VEN
VOUT1
1
1
VOUT1
2
VOUT2
VOUT3
VOUT2
3
VOUT3
4
B
B
W
W
CH2 10mV
CH4 10mV
B
B
W
M2µs
W
T 12%
A CH1
4.58V
CH1 1V
CH3 500mV
Figure 45. Line Transient Response,
VIN = 4 V to 5 V, ILOAD1 = ILOAD2 = ILOAD3 =1 mA,
CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3,
VRIPPLE = 50 mV, COUT = 1 µF
B
W
B
W
CH2 500mV
CH4 500mV
B
B
W
M100µs A CH1
W
T 10.2%
540mV
Figure 46. Turn On Response,
ILOAD1 = ILOAD2 = ILOAD3 =100 mA,
CH1 = VEN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3,
VRIPPLE = 50 mV, COUT = 1 µF
Rev. B | Page 14 of 21
09874-040
CH1 1V
CH3 10mV
09874-039
2
Data Sheet
ADP320
THEORY OF OPERATION
The ADP320 triple LDO is a low quiescent current, low dropout
linear regulator that operates from 1.8 V to 5.5 V on VIN1/VIN2
and VIN3 and provides up to 200 mA of current from each
output. Drawing a low 250 μA quiescent current (typical) at full
load makes the ADP320 triple LDO ideal for battery-operated
portable equipment. Shutdown current consumption is typically
100 nA.
Optimized for use with small 1 µF ceramic capacitors, the
ADP320 triple LDO provides excellent transient performance.
VOUT1
VIN1/VIN2
EN1
SHUTDOWN
VOUT1
EN2
SHUTDOWN
VOUT2
EN3
SHUTDOWN
VOUT3
OVERCURRENT
0.5V
REF
VOUT2
OVERCURRENT
0.5V
REF
VOUT3
VIN3
GND
The ADP320 triple LDO is available in multiple output voltage
options ranging from 0.8 V to 3.3 V. The ADP320 triple LDO
uses the EN1, EN2, and EN3 enable pins to enable and disable
the VOUT1/VOUT2/VOUT3 pins under normal operating
conditions. When the enable pins are high, VOUT1/VOUT2/
VOUT3 turn on; when enable pins are low, VOUT1/VOUT2/
VOUT3 turn off. For automatic startup, the enable pins can be
tied to VBIAS.
OVERCURRENT
0.5V
REF
09874-041
VBIAS
INTERNAL BIAS
VOLTAGES/CURRENTS,
UVLO AND THERMAL
PROTECT
Internally, the ADP320 triple LDO consist of a reference,
three error amplifiers, three feedback voltage dividers, and
three PMOS pass transistors. Output current is delivered
via the PMOS pass device, which is controlled by the error
amplifier. The error amplifier compares the reference voltage
with the feedback voltage from the output and amplifies the
difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to flow and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the gate
of the PMOS device is pulled higher, allowing less current to
flow and decreasing the output voltage.
Figure 47. Internal Block Diagram
Rev. B | Page 15 of 21
ADP320
Data Sheet
APPLICATIONS INFORMATION
ADIsimPOWER DESIGN TOOL
Input Bypass Capacitor
The ADP323 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic, bill of materials,
and calculate performance in minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and parts count,
taking into consideration the operating conditions and limitations
of the IC and all real external components. For more information
about, and to obtain ADIsimPower design tools, visit
www.analog.com/ADIsimPower.
Connecting a 1 µF capacitor from VIN1/VIN2, VIN3, and
VBIAS to GND reduces the circuit sensitivity to the PCB layout,
especially when long input traces or high source impedance are
encountered. If an output capacitance greater than 1 µF is
required, the input capacitor should be increased to match it.
CAPACITOR SELECTION
Output Capacitor
The ADP320 triple LDO is designed for operation with small,
space-saving ceramic capacitors, but the parts function with
most commonly used capacitors as long as care is taken in
regards to the effective series resistance (ESR) value. The ESR
of the output capacitor affects stability of the LDO control loop.
A minimum of 0.70 µF capacitance with an ESR of 1 Ω or less
is recommended to ensure stability of the ADP320 triple LDO.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP320 triple LDO to
large changes in the load current. Figure 48 show the transient
response for an output capacitance value of 1 µF.
Input and Output Capacitor Properties
Any good quality ceramic capacitor may be used with the ADP320
triple LDO, as long as the capacitor meets the minimum capacitance and maximum ESR requirements. Ceramic capacitors are
manufactured with a variety of dielectrics, each with a different
behavior over temperature and applied voltage. Capacitors must
have an adequate dielectric to ensure the minimum capacitance
over the necessary temperature range and dc bias conditions.
X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are
recommended. Y5V and Z5U dielectrics are not recommended,
due to their poor temperature and dc bias characteristics.
Figure 49 depicts the capacitance vs. voltage bias characteristic
of an 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of the package or voltage rating.
1.2
ILOAD1
1.0
CAPACITANCE (µF)
1
VOUT1
2
0.8
0.6
0.4
VOUT2
3
0.2
CH1 100mA
CH3 10mV
B
W
W
CH2 50mV
CH4 10mV
B
B
W
W
M40µs
T 9.8%
A CH1
44mA
09874-042
0
ΩB
0
2
4
6
VOLTAGE (V)
8
Figure 49. Capacitance vs. Voltage Bias Characteristic
Figure 48. Output Transient Response,
ILOAD1 = 1 mA to 200 mA, ILOAD2 = 1 mA, ILOAD3 = 1 mA,
CH1 = ILOAD1, CH2 = VOUT1, CH3 = VOUT2 , CH4 = VOUT3
Rev. B | Page 16 of 21
10
09874-043
VOUT3
4
Data Sheet
ADP320
Use Equation 1 to determine the worst-case capacitance
accounting for capacitor variation over temperature, component tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
As shown in Figure 50, the ENx pin has built-in hysteresis.
This prevents on/off oscillations that can occur due to noise
on the ENx pin as it passes through the threshold points.
(1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
The active/inactive thresholds of the ENx pin are derived
from the VBIAS voltage. Therefore, these thresholds vary with
changing input voltage. Figure 51 shows typical ENx active/
inactive thresholds when the input voltage varies from 2.5 V
to 5.5 V.
In this example, TEMPCO over −40°C to +85°C is assumed
to be 15% for an X5R dielectric. TOL is assumed to be 10%,
and CBIAS is 0.94 μF at 1.8 V from the graph in Figure 49.
1.00
0.95
Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
To guarantee the performance of the ADP320 triple LDO, it is
imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors are evaluated for each
application.
0.85
0.80
0.75
VEN RISE
VEN FALL
0.70
0.65
0.60
0.55
0.50
2.5
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
UNDERVOLTAGE LOCKOUT
The ADP320 triple LDO has an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage bias, VBIAS, is less than approximately 2.2 V. This
ensures that the inputs of the ADP320 triple LDO and the
output behave in a predictable manner during power-up.
ENABLE FEATURE
The ADP320 triple LDO uses the ENx pins to enable and disable
the VOUTx pins under normal operating conditions. Figure 50
shows a rising voltage on EN crossing the active threshold, then
VOUTx turns on. When a falling voltage on ENx crosses the
inactive threshold, VOUTx turns off.
Figure 51. Typical ENx Pins Thresholds vs. Input Voltage
The ADP320 triple LDO utilizes an internal soft start to limit the
inrush current when the output is enabled. The start-up time
for the 2.8 V option is approximately 220 µs from the time the
ENx active threshold is crossed to when the output reaches 90%
of its final value. The start-up time is somewhat dependent on
the output voltage setting and increases slightly as the output
voltage increases.
VEN
VOUT1
1
1.4
VOUT2
VOUT @ 4.5VIN
1.2
VOUT3
0.8
0.6
0.4
CH1 1V
CH3 500mV
0.2
B
W
B
W
CH2 500mV
CH4 500mV
B
B
W
M100µs A CH1
W
T 10.2%
540mV
Figure 52. Typical Start-Up Time,
ILOAD1 = ILOAD2 = ILOAD3 = 100 mA,
CH1 = VEN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3
0
0.5
0.6
0.7
0.8
0.9
1.0
ENABLE VOLTAGE (V)
1.1
1.2
Figure 50. Typical ENx Pin Operation
Rev. B | Page 17 of 21
09874-046
2
09874-054
VOUT (V)
1.0
0.4
09874-053
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
ENABLE THRESHOLDS
0.90
Substituting these values into Equation 1 yields
ADP320
Data Sheet
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP320 triple LDO is protected against damage due to
excessive power dissipation by current and thermal overload
protection circuits. The ADP320 triple LDO is designed to
current limit when the output load reaches 300 mA (typical).
When the output load exceeds 300 mA, the output voltage is
reduced to maintain a constant current limit.
Thermal overload protection is built-in, which limits the
junction temperature to a maximum of 155°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature starts to
rise above 155°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
140°C, the output is turned on again and the output current
is restored to its nominal value.
Consider the case where a hard short from VOUTx to GND
occurs. At first, the ADP320 triple LDO current limits, so that
only 300 mA is conducted into the short. If self-heating of the
junction is great enough to cause its temperature to rise above
155°C, thermal shutdown activates turning off the output and
reducing the output current to zero. As the junction temperature cools and drops below 140°C, the output turns on and
conducts 300 mA into the short, again causing the junction
temperature to rise above 155°C. This thermal oscillation
between 140°C and 154°C causes a current oscillation between
0 mA and 300 mA that continues as long as the short remains
at the output.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
so junction temperatures do not exceed 125°C.
THERMAL CONSIDERATIONS
In most applications, the ADP320 triple LDO does not dissipate
a lot of heat due to high efficiency. However, in applications
with a high ambient temperature and high supply voltage to output voltage differential, the heat dissipated in the package is
large enough that it can cause the junction temperature of the
die to exceed the maximum junction temperature of 125°C.
When the junction temperature exceeds 155°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 140°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown
in Equation 2.
To guarantee reliable operation, the junction temperature of
the ADP320 triple LDO must not exceed 125°C. To ensure that
the junction temperature stays below this maximum value, the
user needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal
resistances between the junction and ambient air (θJA). The θJA
number is dependent on the package assembly compounds used
and the amount of copper to which the GND pins of the package
are soldered on the PCB. Table 6 shows typical θJA values for the
ADP320 triple LDO for various PCB copper sizes.
Table 6. Typical θJA Values
Copper Size (mm2)
JEDEC1
100
500
1000
1
ADP320 Triple LDO (°C/W)
49.5
83.7
68.5
64.7
Device soldered to JEDEC standard board.
The junction temperature of the ADP320 triple LDO can be
calculated from the following equation:
TJ = TA + (PD × θJA)
(2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = Σ[(VIN − VOUT) × ILOAD] + Σ(VIN × IGND)
(3)
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are input and output voltages, respectively.
Power dissipation due to ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to
TJ = TA + {Σ[(VIN − VOUT) × ILOAD] × θJA}
(4)
As shown in Equation 4, for a given ambient temperature,
input-to-output voltage differential, and continuous load
current, there exists a minimum copper size requirement
for the PCB to ensure the junction temperature does not rise
above 125°C. Figure 53 to Figure 56 show junction temperature
calculations for different ambient temperatures, total power
dissipation, and areas of PCB copper.
In cases where the board temperature is known, the thermal
characterization parameter, ΨJB, may be used to estimate the
junction temperature rise. TJ is calculated from TB and PD using
the formula
TJ = TB + (PD × ΨJB)
The typical ΨJB value for the 16-lead 3 mm × 3 mm LFCSP is
25.2°C/W.
Rev. B | Page 18 of 21
(5)
ADP320
140
120
120
80
60
40
1000mm 2
500mm 2
100mm 2
50mm 2
JEDEC
TJ MAX
20
0
0
0.2
0.4
0.6
0.8
1.0
1.2
TOTAL POWER DISSIPATION (W)
80
60
40
120
JUNCTION TEMPERATURE, TJ (°C)
120
60
40
1000mm 2
500mm 2
100mm 2
50mm 2
JEDEC
TJ MAX
20
0
0
0.2
0.4
0.6
0.8
TOTAL POWER DISSIPATION (W)
1.0
1.2
1.0
0.8
0.6
0.4
1.2
Figure 55. Junction Temperature vs. Total Power Dissipation, TA = 85°C
140
80
0.2
0
TOTAL POWER DISSIPATION (W)
140
100
1000mm 2
500mm 2
100mm 2
50mm 2
JEDEC
TJ MAX
20
0
09874-048
JUNCTION TEMPERATURE, TJ (°C)
Figure 53. Junction Temperature vs. Total Power Dissipation, TA = 25°C
100
Figure 54. Junction Temperature vs. Total Power Dissipation, TA = 50°C
Rev. B | Page 19 of 21
100
80
60
40
TB = 25°C
TB = 50°C
TB = 85°C
TJ MAX
20
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
TOTAL POWER DISSIPATION (W)
1.6
1.8
09874-050
100
09874-049
JUNCTION TEMPERATURE, TJ (°C)
140
09874-047
JUNCTION TEMPERATURE, TJ (°C)
Data Sheet
Figure 56. Junction Temperature vs. Total Power Dissipation and
Board Temperature
ADP320
Data Sheet
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins of the
ADP320 triple LDO. However, as can be seen from Table 6, a
point of diminishing returns eventually is reached, beyond
which an increase in the copper size does not yield significant
heat dissipation benefits.
09874-051
Place the input capacitor as close as possible to the VINx and
GND pins. Place the output capacitors as close as possible to
the VOUTx and GND pins. Use 0402 or 0603 size capacitors
and resistors to achieve the smallest possible footprint solution
on boards where area is limited.
09874-052
Figure 57. Example of PCB Layout, Top Side
Figure 58. Example of PCB Layout, Bottom Side
Rev. B | Page 20 of 21
Data Sheet
ADP320
OUTLINE DIMENSIONS
0.30
0.25
0.20
0.50
BSC
PIN 1
INDICATOR
16
13
1
12
EXPOSED
PAD
1.65
1.50 SQ
1.45
9
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
4
5
8
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.20 MIN
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
01-26-2012-A
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
Figure 59. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very, Very Thin Quad
(CP-16-27)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADP320ACPZ331815R7
ADP320ACPZ-110-R7
Temperature Range
−40°C to +125°C
−40°C to +125°C
Output Voltage (V)2
3.3, 1.8, 1.5
3.3, 3.3, 1.5
1
Z = RoHS Compliant Part.
2
For additional voltage options, contact a local sales or distribution representative.
©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09874-0-11/14(B)
Rev. B | Page 21 of 21
Package Description
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
Package Option
CP-16-27
CP-16-27
Branding
LGP
L15