Progress and challenges in the direct monolithic
integration of III-V devices and Si CMOS on silicon
substrates
The MIT Faculty has made this article openly available. Please share
how this access benefits you. Your story matters.
Citation
Kazior, T.E. et al. “Progress and challenges in the direct
monolithic integration of III–V devices and Si CMOS on silicon
substrates.” Indium Phosphide & Related Materials, 2009. IPRM
'09. IEEE International Conference on. 2009. 100-104. © 2009
IEEE
As Published
http://dx.doi.org/10.1109/ICIPRM.2009.5012452
Publisher
Institute of Electrical and Electronics Engineers
Version
Final published version
Accessed
Wed May 25 23:15:08 EDT 2016
Citable Link
http://hdl.handle.net/1721.1/54683
Terms of Use
Article is made available in accordance with the publisher's policy
and may be subject to US copyright law. Please refer to the
publisher's site for terms of use.
Detailed Terms
TuA1.3 (Invited)
9:15 AM - 9:45 AM
Progress and Challenges in the Direct Monolithic Integration of III-V Devices
and Si CMOS on Silicon Substrates
T.E. Kazior*1, J.R. LaRoche1, D. Lubyshev2, J. M. Fastenau2, W. K. Liu2, M. Urteaga3, W. Ha3, J. Bergman3,
M. J. Choe3, M. T. Bulsara4, E. A. Fitzgerald4, D. Smith5, D. Clark5, R. Thompson5, C. Drazek6, N. Daval6,
L. Benaissa7 and E. Augendre7
1
Raytheon Integrated Defense Systems, Andover, Massachusetts, USA; 2IQE Inc., Bethlehem, Pennsylvania,
USA; 3Teledyne Scientific Company, Thousand Oaks, California, USA; 4Department of Materials Science
and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts, USA; 5Raytheon
Systems Limited, Glenrothes, Fife, United Kingdom; 6SOITEC, Bernin, France; 7CEA-LETI, MINATEC,
Grenoble, France
Abstract
We present results on the direct monolithic integration of III-V devices and Si CMOS on a silicon
substrate. Through optimization of device fabrication and material growth processes III-V devices with
electrical performance comparable to devices grown on native III-V substrates were grown directly in
windows adjacent to CMOS transistors on silicon template wafers or SOLES (Silicon on Lattices
Engineered Substrates). While the results presented here are for InP HBTs, our direct heterogeneously
integration approach is equally applicable to other III-V electronic (FETs, HEMTs) and opto-electronic
(photodiodes, VSCLS) devices and opens the door to a new class of highly integrated, high performance,
mixed signal circuits.
Index Terms — CMOS integrated circuits, Heterojunction bipolar transistors, Indium Phosphide,
Monolithic integrated circuits, Silicon
CMOS on a silicon substrate. As a demonstration vehicle we
designed and fabricated a high speed, low power dissipation
differential amplifier which serves as the basic building block
for high performance mixed signal circuits such as ADCs and
DACs.
I. INTRODUCTION
The future of integrated circuits will include the integration
of high performance III-V electronic and/or opto-electronic
devices with standard Si CMOS. While traditional hybrid
approaches, such as wire bonded or flip chip multi-chip
assemblies (Fig 1, left), may provide short term solutions, the
variability and losses of the interconnects and the limitation in
the placement of III-V devices relative to CMOS transistors
will limit the performance and utility of these approaches.
Recently, investigators have successfully demonstrated
heterogeneous integration of InP HBTs and Silicon CMOS
using variations on wafer bonding techniques [1,2] where the
III-V eptaxial layers or completed devices are bonded to the
surface of a completed Si CMOS wafer. A more attractive
approach is the direct integration of CMOS and III-V devices
on a common silicon substrate (Fig 1, right). In this way
circuit performance can be optimized by the strategic
placement of III-V devices adjacent to CMOS transistors and
cells. While the direct growth and fabrication of III-V devices
on silicon substrates has been pursued for over 30 years [3],
recent advances in strain and lattice engineered materials and
epitaxial growth techniques have enabled the direct growth of
high quality III-V device layers on silicon substrates.
In this work we present the challenges and recent progress
on the direct heterogeneous integration of InP HBTs and Si
978-1-4244-3433-6/09/$25.00©2009 IEEE
Si multilayer interconnect
TFN
Si CMOS
TFN
III-V
TFN
Multilayer Substrate
Today’s Hybrid
Technology
(“chip and wire” or flip chip
with thin film networks or
TFNs)
Si CMOS
Revolutionary
Developments
Enable System
on a Chip
III-V
Si CMOS
Si Substrate
III-V CMOS
Integration
III-V devices embedded in a Si
wafer using III-V templates and
standard Si multilayer
interconnects and processing
Fig. 1. Traditional hybrid assembly (left) and direct
monolithic integration of III-V and CMOS on SOLES
substrate (right).
II. RESULTS AND DISCUSSION
Our direct integration approach is based on a unique
“engineered” silicon substrate which is similar to a standard
SOI wafer. The SOLES (Silicon-on-Lattice Engineered
Substrate), invented at MIT [4,5] and manufactured by
SOITEC using their Smart-CutTM Process [6, 7], contains a
buried III-V template layer that enables the direct growth of
high quality III-V epitaxial material in windows directly on the
100
Authorized licensed use limited to: MIT Libraries. Downloaded on April 21,2010 at 14:59:35 UTC from IEEE Xplore. Restrictions apply.
silicon substrate (Figure 2). At present the buried III-V
template layer is Ge, although the substrate fabrication process
is compatible with GaAs or InP template layers as well.
SOLES have been successfully scaled to 200mm diameter
wafers and are compatible with and can be readily inserted
into a standard silicon CMOS foundry.
SOLES Wafer
BPSG
Si
S iO
III-V
D e v ic e s
2
material due to nucleation and growth of III-V material on
impurities at the windows edge. High quality III-V epitaxy,
well defined windows edges and repeatable (wafer to wafer),
uniform growth across a 100mm diameter wafer in windows as
small as 15um x 15um are readily obtained with an optimized
process (Figures 5 right, 6).
A detailed report on the growth of high quality InP HBT
epitaxial material in windows on SOLES has been previously
published [8].
With optimized growth conditions low
dislocation density (<107) material with good surface
morphology (surface roughness < 1nm as measured by AFM)
and well defined X-ray spectra are easily achieved.
BPSG
Si
S iO
2
G e
S iO
2
( 1 0 0 ) S i H a n d le W a f e r
Fig. 2. Schematic cross section of SOLES wafers showing
placement of of III-V device in windows.
HBT
HBT
While our main efforts have focused on the fabrication of
InP HBTs on SOLES, effectively creating a high performance
InP BiCMOS process (similar to the SiGe BiCMOS process),
the approach is equally applicable to other III-V electronic
(FETs, HEMTs) and opto-electronic (photodiodes, VSCLS)
devices. In fact the process flow is similar to a SiGe BiCMOS
process flow: 1) Si CMOS device fabrication; 2) HBT
epitaxial growth and device fabrication; 3) multilayer
interconnect fabrication. In our approach, after the completion
of CMOS device fabrication, windows are lithography
defined and etched into the SOLES wafer to reveal the III-V
template layer. Since the III-V growth windows are defined as
part of the CMOS fabrication process, the III-V epitaxial
material can be grown selectively and arbitrarily across the
substrate as required for the particular circuit or applications.
Figure 3 shows an example of a SEM image of a completed
InP HBT in close proximity to a CMOS transistor prior to
interconnect formation. To facilitate the interconnecting of the
III-V devices and CMOS transistors, the thickness of the III-V
epitaxial layers and depth of the windows are optimized such
that the III-V devices and CMOS transistors are planar.
Figure 4 shows an example of a daisy chain tech structure
interconnecting InP HBTs and Si CMOS. With this truly
planar approach, interconnect lengths (III-V – CMOS
separation) as small 2.5 um have been demonstrated.
One of the biggest challenges of this approach is the growth
of high quality III-V epitaxial material in windows on the Ge
template layer. (Note: all of the III-V epitaxial material
reported in this work is grown by MBE.) For the InP HBT,
we first grow a GaAs nucleation layer, whose growth
conditions are optimized to minimize the formation of antiphase domains (APDs). GaAs is chosen as it is nearly lattice
matched to Ge. Then a metamorphic buffer layer is grown
followed by the InP device layers. Optimization of the
windows etch and epitaxial growth processes are key to
achieving high quality device layers. Figure 5 (left) shows an
example of III-V growth in windows for unoptimized windows
etch and epitaxial growth processes. Note the surface
roughness, poor edge definition and formation of nanowire
CMOS
CMOS
5m
mm
Fig. 3. SEM image of a completed InP HBT in close
proximity to a Si CMOS transistor prior to heterogeneous
interconnect formation.
CMOS Metal
< 2.5µm
HBT Coll Metal
Fig. 4. SEM image of a heterogeneous interconnect daisy
chain test prior to final interconnect metallization. InP HBT
– Si CMOS interconnect spacing is < 2.5um.
Poly
crystal
on BPSG
Single crystal inside
growth window
Fig. 5. SEM Image of InP HBT device epitaxy material
grown in windows on SOLES for unoptimized process (left.
Note nanowire growth) and optimized process (right. Note:
well defined windows down to 15um x 15um windows
dimensitions)
101
Authorized licensed use limited to: MIT Libraries. Downloaded on April 21,2010 at 14:59:35 UTC from IEEE Xplore. Restrictions apply.
The electrical performance of InP HBTs fabricated on
SOLES is comparable to HBTs grown directly on native InP
substrates [9]. Figures 7 and 8 shows the Gummel
characteristics and small signal parameters of a 0.5 x 5 um2
emitter HBT grown in a 15 x 15 um2 window on a SOLES
substrate. Gain (beta), ft and fmax of 40, > 200GHz and >
200GHz, respectively are achieved.
AE = 0.5x5 mm2
IC = 7.8 mA
VCE = 1.5V
ft = 224 GHz
fmax = 219 GHz
Fig. 8. Measured small signal RF characteristics of a 0.5x5
um2 InP-HBT on SOLES substrate
Using the InP HBT described above and standard CMOS a
differential amplifier test vehicle was designed and fabricated.
Figure 9 shows an optical image of a completed differential
amplifier circuit. In addition to the core differential amplifier,
the circuit contains a bias circuit and all HBT output buffer.
The role of the output buffer is to attenuate the output of the
core differential amplifier to facilitate the characterization of
the differential amplifier.
Fig. 6. Micrograph of InP HBT growth in windows on
100mm diameter SOLES. Note: uniform growth across entire
wafer. Large area in center of wafer is RHEED window for
use during MBE growth.
Core Diff Amp
Output Buffer
pMOS
AE=0.5x5 mm2
b = 40
InP HBT
nMOS
pMOS
InP HBT
Fig.9 Optical image of core differential amplifier with
output buffer and bias circuit
Because of our truly monolithically integrated, planar
approach we were able to include multiple design variants
within a reticle on a wafer, effectively creating a design
optimization design of experiments (DOE) within the reticle.
Each design variant is step and repeated across the 100mm
SOLES wafer. The planar approach also facilities automated
on-wafer probing for circuit characterization and the collection
of circuit performance and uniformity data for the different
design variants
The following test results are for one of these design
variants which utilizes a 3-2x5um2 HBT in each diff amp
branch (6-total) with 6-finger (2um gate length, 19.2um wide)
PMOS devices for the amplifier loads. For all the
measurements that are shown, the differential amplifier core
was biased at a Vss= 6V and Iss=10mA (Pdiss=60mW).
Fig. 7. Measured Gummel characteristics and RF gains of a
0.5x5 um2 InP-HBT on SOLES substrate
102
Authorized licensed use limited to: MIT Libraries. Downloaded on April 21,2010 at 14:59:35 UTC from IEEE Xplore. Restrictions apply.
Separate DC supply inputs are provided for the amplifier core
and output buffer circuits to ensure an accurate measurement
of the dissipated power of the core.
4-port S-parameter measurements were made to determine
the low frequency amplifier gain and unity-gain bandwidth.
Measurements were made from 1MHz-20 GHz using on-wafer
differential GSGSG probes. A probe tip calibration was
performed using a GGB Industries calibration substrate.
Measurements from 1-50MHz were used to extract the low
frequency gain of the differential amplifier. The low frequency
voltage gain of the differential amplifier core was determined
by measuring the gain of the chain of the differential amplifier
with output buffer and correcting for the attenuation of the
amplifier such that Av,diff amp = S21,chain-S21,buffer. The
output buffer amplifier has a low frequency attenuation of
~25dB – a values that agreed well with simulations
Figure 10 shows the low-frequency gain of the core
differentail amplifier. A peak low frequency gain of 454V/V
was measured. At lower frequencies, the gain is observed to
decrease slightly. We believe this is due to device self-heating
(increased output conductance of HBT).
frequency response was not utilized. Instead, the unity gain
frequency was extrapolated from the intercept of data taken
from 1-15 GHz. A unity-gain frequency of >25 GHz was
extracted from the measurement shown in Figure 11. From the
DC-gain measurement, the DC-gain*unity gain bandwidth
product is measured to be 1.1x104 V/V GHz.
50
40
Gain (dB)
20
10
S21,chain
0
-10
-20
S21,O/B
-30
-40
1.00E+08
1.00E+09
1.00E+10
1.00E+11
Freq (Hz)
60
A,v,DA
50
Fig. 11. Measured S21 of amplifier chain and output buffer
test circuits at high frequencies. Scalar determination of diff
amp gain is determined as S21,DA=S21,chain – S21,O/B.
Core diff amp utilized 3-2x5um2 HBT in each diff amp branch
with 6-finger 2um PMOS devices. Iss = 10mA, Vss = -6V.
40
30
S21 (dB)
S21,chain-S21,O/B
30
S21,chain
20
10
0
-10
Slew-rate measurements were made on the same amplifier
show in Figures 10 and 11. For the slew rate measurement, a
250 MHz input signal was provided from a signal generator. A
differential input signal was generated using a 180° balun.
Both outputs from the amplifier were provided to a high-speed
Agilent sampling oscilloscope and the differential amplifier
output was determined using the mathematical functions of the
oscilloscope. Figure 12 shows the measured output waveform
of the amplifier when driven to saturation. A peak output
swing of 420mV was measured from the output buffer stage.
Correcting for the measured attenuation of the output buffer
(25.5dB from S-parameters) the corresponding voltage swing
of the amplifier core is 9V peak to peak (4.5V single ended).
The rise time and fall time (10%-90%) of the amplifier were
determined using the internal math functions of oscilloscope.
For the measurement in Figure 12, the average rise/fall time
was 510psec. Based on the signal swing of the amplifier core,
this corresponds to a measured slew rate of 1.26x104 V-usec.
Similar results were achieved for other differential amplifier
design variants and for different wafers highlighting the
manufacturability of our approach.
S21,O/B
-20
-30
0
1E+07 2E+07
3E+07 4E+07 5E+07 6E+07
Freq. (Hz)
Fig. 10. Measured S21 of amplifier chain and output buffer
test circuits at low frequencies. Low frequency gain AV,DA is
given by AV,DA=S21,chain – S21,O/B. Core diff amp utilized
3-2x5um2 HBT in each diff amp branch with 6-finger 2um
PMOS devices. Iss = 10mA, Vss = -6V.
The high frequency gain measurements are extracted using a
similar scalar approach for determining the core amplifier
characteristics. Figure 11 shows the corrected high frequency
characteristics for the same amplifier as shown in Figure 10.
A deviation in the slope of the roll-off was observed at the
higher end of the frequency band. The cause of this
discrepancy has not been determined. To determine the unity
gain cut-off frequency of the amplifier, this portion of the
103
Authorized licensed use limited to: MIT Libraries. Downloaded on April 21,2010 at 14:59:35 UTC from IEEE Xplore. Restrictions apply.
(COSMOS) Program” 2008 Compound Semiconductor
Integrated Circuits Symposium (CSICS ’08) 12-15 Oct
2008, 10.1109/CSICS.2008.6
[2]
Li, J.C.; Elliott, K.R.; Matthews, D.S.; Hitko, D.A.;
Zehnder, D.M.; Royter, Y.; Patterson, P.R.; Hussain, T.;
Jensen, J.F., “100GHz+ Gain-Bandwidth Differential
Amplifiers in a Wafer Scale Heterogeneously Integrated
Technology using 250nm InP DHBTs and 130nm
CMOS” 2008 Compound Semiconductor Integrated
Circuits Symposium (CSICS ’08) 12-15 Oct 2008,
10.1109/CSICS.2008.53
[3]
S. F. Fang, K. Adomi, S. Iyer, H. Morkoç, H. Zabel, C.
Choi and N. Otsuka, “Gallium arsenide and other
compound semiconductors on silicon” J. Appl. Phys. 68
(1990) R31 and references therein
[4]
C. L. Dohrman, K. Chilukuri, D. M. Isaacson, M. L. Lee,
E.A Fitzgerald, “Fabrication of silicon on latticeengineered substrate (SOLES) as a platform for
monolithic integration of CMOS and optoelectronic
devices” Materials Science and Engineering B, 135
(2006) 235-237
[5]
K. Chilukuri, M. J. Mori, C. L. Dohrman and, E. A.
Fitzgerald, “ Monolithic CMOS-compatible AlGaInP
visibile LED arrays on silicon on lattice-engineered
substrates (SOLES)” Semicond. Sci. Tech. 22 (2007), 2934
Low frequency voltage swing 9V
250 MHz Rise Time = 510psec
Fig. 12. Measured output waveform for slew rate
measurements of amplifier (same amplifier as that measured
in Figures 10 and 11). 250MHz differential input signal is
provided to saturate the amplifier. A peak output voltage
swing of 420mV was measured from the output buffer
corresponding to an internal input swing of 9.0V. An average
rise/fall time of 510psec is measured.
III. SUMMARY
In this work we presented results on the direct
monolithic integration of InP HBTs with Si CMOS on a
silicon substrate. Our direct growth approach yields InP HBTs
with similar RF performance to HBTs fabricated on InP
substrates. Our truly planar approach allows tight device
placement (InP HBTs - Si CMOS transistors separation as
small as 2.5um) and the use os standard wafer level multilayer
interconnects. While the results presented here are for InP
HBTs directly integrated onto the silicon substrate, the
approach is equally applicable to other III-V electronic (FETs,
HEMTs) and opto-electronic (photodiodes, VSCLS) devices
and opens the door to a new class of highly integrated, high
performance, mixed signal circuits.
C. Maleville and C. Mazuré, “Smart Cut technology:
From 300 mm ultrathin SOI production to advanced
engineered substrates.” Solid State Electron. 48 (2004)
1055.-1063
[7] Smart-Cut™ is a registered trademark of Soitec.
[8] W. K. Liu, D. Lubyshev, J. M. Fastenau, Y. Wu, M. T.
Bulsara, E. A. Fitzgerald, M. Urteaga, W. Ha, J. Bergman,
B. Brar, W. E. Hoke, J. R. LaRoche, K. J. Herrick, T. E.
Kazior, D. Clark, D. Smith, R. F. Thompson, C. Drazek,
and N. Daval, “Monolithic Integration of InP-based
Transistors on Si substrates using MBE” Journal of
Crystal Growth XX (2009) in press
[9] W. Ha, M. Urteaga, J. Bergman, B. Brar, W. K. Liu,
D. Lubyshev, J. M. Fastenau, Y. Wu, M. T. Bulsara,
E. A. Fitzgerald, W. E. Hoke, J. R. LaRoche, K. J.
Herrick, T. E. Kazior, D. Clark, D. Smith, R. F.
Thompson, C. Drazek, and N. Daval, “Small-area InP
DHBTs grown on patterned lattice-engineered silicon
substrates” 66th Device Research Conference, Santa
Barbara, CA, Jun 23–25, 2008 (IV.B-9).
[6]
ACKNOWLEDGEMENT
This work is supported in part by the DARPA COSMOS
Program (Contract Number N00014-07-C-0629). The authors
would like to thank Mark Rosker (DARPA), Harry Dietrich
(ONR) and Karl Hobart (NRL).
REFERENCES
[1]
M. J. Rosker, V. Greanya, T-H Chang., “The DARPA
Compound Semiconductor Materials On Silicon
104
Authorized licensed use limited to: MIT Libraries. Downloaded on April 21,2010 at 14:59:35 UTC from IEEE Xplore. Restrictions apply.