ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JC
rel
JNC rel
JB
bit,rel
JNB
bit,rel
JBC
bit,rel
JZ
rel
JNZ
rel
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
CJNE @Ri,#data,rel
DJNZ Rn,rel
DJNZ direct, rel
NOP
call subroutine
return from sub.
return from int.
jump
jump if C set
jmp if C not set
jump if bit set
jmp if bit not set
jmp&clear if set
jump if A = 0
jump if A not 0
compare and
jump if not
equal
decrement and
jump if not zero
no operation
2
3
1
1
2
3
2
1
2
2
3
3
3
2
2
3
3
3
3
2
3
1
3
4
4
4
3
4
3
3
3
3
4
4
4
3
3
4
4
4
4
3
4
1
Legend
Rn
register addressing using R0-R7
@Ri
indirect addressing using R0 or R1
direct
8-bit internal address (00h-FFh)
#data
8-bit constant included in instruction
#data16 16-bit constant included in instruction
bit
8-bit direct address of bit
rel
signed 8-bit offset
addr11
11-bit address in current 2K page
addr16
16-bit address
x
any of: Rn, @Ri, direct, #data
Instructions That Affect Flags
ADD A,x
C = carry out of bit 7
AC = carry out of bit 3
OV = carry out of bit 6, but not 7
ADDC A,x C = carry out of bit 7
AC = carry out of bit 3
OV = carry out of bit 6, but not 7
SUBB A,x C = borrow into bit 7
AC = borrow into bit 3
OV = borrow into bit 6, but not 7
MUL AB
C=0
OV = (result>255)
DIV AB
C=0
OV = divide by zero
DA A
RRC A
RLC A
SETB C
CLR C
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
CJNE x,y,rel
C = C or (x>100)
C = ACC.7
C = ACC.0
C=1
C=0
C = C and bit
C = C and NOTbit
C = C or bit
C = C or NOTbit
C = bit
C = (x<y)
AIN9 (CSP package only)
27
29
SDATA (I2C)
40
43
EA
16
AIN10 (CSP package only)
28
30
P2.0 / SCLOCK (SPI)
41
44
PSEN
15
17
RESET
29
31
P2.1 / MOSI (SPI)
42
45
ALE
16
18
P3.0 / RxD
30
32
P2.2 / MISO (SPI)
43
46
P0.0 / AD0
17
19
P3.1 / TxD
31
33
P2.3 / SS / T2
44
47
P0.1 / AD1
18
20
P3.2 / INT0
32
34
XTAL1 (in)
45
48
P0.2 / AD2
19
21
P3.3 / INT1
33
35
XTAL2 (out)
46
49
P0.3 / AD3
20
22
DVDD
34
36
DVDD
47
50
DGND
21
23
DGND
35
37
DGND
48
51
DVDD
22
24
P3.4 / T0
-
38
DGND
49
52
P0.4 / AD4
23
25
P3.5 / T1
36
39
P2.4 / T2EX
50
53
P0.5 / AD5
24
26
P3.6 / WR
37
40
P2.5 / PWM0
51
54
P0.6 / AD6
25
27
P3.7 / RD
38
41
P2.6 / PWM1
52
55
P0.7 / AD7
26
28
SCLK (I C)
39
42
P2.7 / PWMCLK
1
56
P1.0 / AIN1
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AINCOM
internal
code space
0000h
8
7
REFIN2+
REFIN2-
2
3
P3.0 (RxD)
P3.1 (TxD)
P3.2 (INT0)
P3.3 (INT1)
P3.4 (T0)
P3.5 (T1)
P3.6 (WR)
P3.7 (RD)
18
19
20
21
24
25
26
27
Flash/EE
62K x 8
code
Flash/EE
VREF
detect
& mux
baudrate timer
2K x 8
user “XRAM”
256 x 8
user RAM
1-clock
8052
16-bit
counter
timers
watchdog
timer
MCU
core
power supply
monitor
downloader
debugger
internal
code space
2000h
1FFFh
32kB
Flash/EE
0000h
Interrupt Name
PSMCON.5
WDS
IE0
RDY0/RDY1
TF0
IE1
TF1
ISPI/I2CI
RI/TI
TF2/EXF2
TIMECON.2
Power Supply Monitor Interrupt
WatchDog Timer Interrupt
External Interrupt 0
End of ADC Conversion Interrupt
Timer0 Overflow Interrupt
External Interrupt 1
Timer1 Overflow Interrupt
SPI/I2C Interrupt
UART Interrupt
Timer2 Interrupt
Time Interval Counter Interrupt
DAC
40
PWM0
41
PWM1
24
T0
25
T1
33
T2
39
T2EX
20
INT0
21
INT1
* pin numbers refer to CSP package
internal
code space
8kB
Flash/EE
A Precision Analog Flash MCU
The ADuC845/ADuC847/ADuC848 is:
ADC:
Interrupt Vector Addresses
Interrupt Bit
35
(NOP instructions)
8000h
7FFFh
34
(NOP instructions)
14
OSC &
PLL
XTAL2
12
I2 C
SPI
XTAL1
IEXC2
FFFFh
asynchronous
serial port
(UART)
POR
33
11
time
interval
counter
28
29
8
IEXC1
BUF
PWM
4K x 8
data
bandgap
reference
DAC
SS
32
0000h
© 2004 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the
property of their respective owners.
Purchase of licensed I2C components of Analog
Devices or one of its sublicensed Associated
Companies conveys a license for the purchaser
under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the
system conforms to the I2C Standard Specification
as defined by Philips.
Printed in the U.S.A.
G04923-4-6/04(0)
DAC
control
ADC
control
&
calibration
SD ADC
(65,536 counts
per oC)
REFIN+
REFIN-
ADuC845 only
24-bit
200µA / 400µA
FFFFh
62kB
Flash/EE
(auxillary ADC)
ADuC845/7/8
ADC
control
&
calibration
SD ADC
SCLK
SDATA
(NOP instructions)
AIN
MUX
16-bit on ADuC848
24-bit
PGA
30
31
32
F800h
F7FFh
(primary ADC)
BUF
SCLOCK
MOSI
MISO
62
56
1
2
3
9
10
11
12
15
16
13
TEMP
sensor
Code Memory Space Options
FFFFh
P2.0 (A8 / A16)
P2.1 (A9 / A17)
P2.2 (A10 / A18)
P2.3 (A11 / A19)
P2.4 (A12 / A20)
P2.5 (A13 / A21)
P2.6 (A14 / A22)
P2.7 (A15 / A23)
FP
15
-
2
30
31
32
33
39
40
41
42
Q
Q
M
C
-
single-pin
emulator
DAC
45
44
43
14
ALE
PSEN
EA
AINCOM / DAC
14
19
13
18
P1.7 / AIN8 / IEXC2
13
M
56
55
54
53
52
51
50
49
48
47
46
45
44
43
52
51
50
49
48
47
46
45
44
43
42
41
40
P1.6 / AIN7 / IEXC1
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P1.5 / AIN6
11
12
FP
10
11
12
TxD
10
FUNCTIONAL
BLOCK
DIAGRAM
P1.0 (AIN1)
P1.1 (AIN2 / REFIN2+)
P1.2 (AIN3 / REFIN2-)
P1.3 (AIN4)
P1.4 (AIN5)
P1.5 (AIN6)
P1.6 (AIN7 / IEXC1)
P1.7 (AIN8 / IEXC2)
P1.4 / AIN5
56
1
2
3
9
10
11
12
9
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
REFIN+
9
46
47
48
49
52
53
54
55
REFIN-
8
®
SP
7
8
ADuC845
52-pin MQFP
TOP VIEW
(not to scale)
ADuC845/ADuC847/ADuC848
MicroConverter Quick Reference Guide
C
7
ADuC845
56-pin CSP
TOP VIEW
(not to scale)
39
38
37
36
35
34
33
32
31
30
29
28
27
14
15
16
17
18
19
20
21
22
23
24
25
26
AGND
FP
AGND
6
Q
5
pin 1 identifier
M
6
SP
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
C
FP
Q
SP
M
C
4
42
41
40
39
38
37
36
35
34
33
32
31
30
29
pin 1 identifier
SP
by
te
s
O
S
pe C
rio
d
s
clear A to zero
complement A
rotate A left
...through C
rotate A right
...through C
swap nibbles
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RxD
by
te
s
O
S
pe C
rio
d
Program Branching
logical XOR
P1.3 / AIN4 / REFIN2-
17
move bit to bit
logical OR
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
3
1
1
1
1
1
1
1
3
RESET
AND bit with C
AND (NOTbit) with C
OR bit with C
OR (NOTbit) with C
logical AND
1
1
2
2
2
3
1
1
2
2
2
3
1
1
2
2
2
3
1
1
1
1
1
1
1
P1.2 / AIN3 / REFIN2+
4
23
37
38
50
complement bit
1
2
1
2
1
2
2
2
2
2
2
2
A,Rn
A,@Ri
A,direct
A,#data
direct,A
direct,#data
A,Rn
A,@Ri
A,direct
A,#data
direct,A
direct,#data
A,Rn
A,@Ri
A,direct
A,#data
direct,A
direct,#data
A
A
A
A
A
A
A
P1.1 / AIN2
2
DGND
set bit to one
1
2
1
2
1
2
2
2
2
2
2
2
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
RLC
RR
RRC
SWAP
1
3
DVDD
clear bit to zero
multiply A by B
divide A by B
decimal adjust
2
5
6
C
bit
C
bit
C
bit
C,bit
C,/bit
C,bit
C,/bit
C,bit
bit,C
decrement
Logical Operations
s
CLR
CLR
SETB
SETB
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
increment
* INC DPTR increments the 24bit value DPP/DPH/DPL
by
te
s
O
S
pe C
rio
d
Boolean Variable Manipulation
subtract from A
with borrow
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
3
1
1
2
2
9
9
2
22
36
51
exchg low digits
add with carry
1
1
2
2
1
1
2
2
1
1
2
2
1
1
1
2
1
1
1
1
2
1
1
1
4
exchange bytes
add source to A
AVDD
push onto stack
pop from stack
A,Rn
A,@Ri
A,direct
A,#data
A,Rn
A,@Ri
A,direct
A,#data
A,Rn
A,@Ri
A,direct
A,#data
A
Rn
@Ri
direct
DPTR *
A
Rn
@Ri
direct
AB
AB
A
Pin Functions
AGND
move to/from
data memory
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
INC
INC
INC
INC
DEC
DEC
DEC
DEC
MUL
DIV
DA
1
2
2
2
1
2
2
2
2
2
3
3
2
2
2
3
4
4
4
4
4
4
2
2
1
2
2
2
s
move from
code memory
Arithmetic Operations
by
te
s
O
S
pe C
rio
d
move
1
1
2
2
1
2
2
2
2
2
3
3
1
2
2
3
1
1
1
1
1
1
2
2
1
1
2
1
s
MOV A,Rn
MOV A,@Ri
MOV A,direct
MOV A,#data
MOV Rn,A
MOV Rn,direct
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct,@Ri
MOV direct,direct
MOV direct,#data
MOV @Ri,A
MOV @Ri,direct
MOV @Ri,#data
MOV DPTR,#data16
MOVC A,@A+DPTR
MOVC A,@A+PC
MOVX A,@Ri
MOVX A,@DPTR
MOVX @Ri,A
MOVX @DPTR,A
PUSH direct
POP direct
XCH A,Rn
XCH A,@Ri
XCH A,direct
XCHD A,@Ri
by
te
s
O
S
pe C
rio
d
Data Transfer Operations
s
Instruction Set
Vector
Address
Relative
Priority
43h
5Bh
03h
33h
0Bh
13h
1Bh
3Bh
23h
2Bh
53h
1
2
3
4
5
6
7
8
9
10
11
24-bit* primary ADC, differential w/ programmable gain
24-bit auxiliary ADC, single-ended w/ fixed gain (ADuC845 only)
10-channel input mux
(*ADC is 16bit on ADuC848)
DAC:
12-bit, 15µs, voltage output
<1LSB DNL
Flash/EEPROM:
up to 62kB Flash/EE program memory
4kB Flash/EE data memory
Microcontroller:
“single-cycle” 8052, up to 12.6MIPS
32 I/O lines, programmable PLL clock
(98.3kHz to 12.6MHz from 32kHz crystal)
Embedded Tools Support:
on-chip download/debug & single-pin emulation functions
Other on-chip features:
temperature sensor, power supply monitor, watchdog timer,
flexible serial interface ports, voltage reference, time interval
counter, dual 8-/16-bit PWM, power-on-reset
REV. 0
ADCMODE
lower RAM
details
SPR1
F9h
0
SPR0
F8h
0
SPICON
F8h
04h
* calibration coefficients are preconfigured at power-up to factory-calibrated values
00h
PCON
87h
(reserved)
ADC Mode register
60Hz reject filter enable (0=disable)
primary ADC enable bit (0=disable)
auxiliary ADC enable bit (0=disable)
chop mode disable bit (1=disable)
ADC mode bits:
[off, idle, single-conv, continuous-conv,
zero-cal, fs-cal, sys-zero-cal, sys-fs-cal]
ADCSTAT
RDY0
RDY1
CAL
NOXREF
ERR0
ERR1
ADC Status register
ADC0 ready indicator flag
ADC1 ready indicator flag
calibration start control bit (set to begin cal)
no external reference flag (only valid if ADC active)
primary ADC error flag (indicates result is clamped)
auxiliary ADC error flag (indicates result is clamped)
00h 83h
07h 82h
FFh 81h
80h
1
80h
1
ADC0 Control register #1
buffer configuration bits:
[00=buffered, 10=unbuffered, others reserved]
unipolar select bit (0=bipolar)
range select bits:
[±20mV, ±40mV, ±80mV, ±160mV,
±320mV, ±640mV, ±1.28V, ±2.56V]
ADC0CON2
ADC0CON2.7
ADC0CON2.6
ADC0CON2.3
ADC0CON2.2
ADC0CON2.1
ADC0CON2.0
ADC0 Control register #2
reference select bits
[internal, REFIN pins, REFIN2 pins, reserved]
channel select bits
[1-COM, 2-COM, 3-COM, 4-COM, 5-COM,
6-COM, 7-COM, 8-COM, 9-COM, 10-COM,
1-2, 3-4, 5-6, 7-8, 9-10, COM-COM]
ADC1CON
ADC1CON.6
ADC1CON.5
ADC1CON.3
ADC1CON.2
ADC1CON.1
ADC1CON.0
ADC1 Control register
REFIN select bit (0=internal reference)
unipolar select bit (0=bipolar)
channel select bits
[1-COM, 2-COM, 3-COM, 4-COM, 5-COM,
6-COM, 7-COM, 8-COM, 9-COM, 10-COM,
1-2, 3-4, 5-6, 7-8, tempsens, COM-COM]
SF Sync Filter Register:
fADC = 4,096Hz / (3·SF)
fADC = 4,096Hz / (SF)
(chop on)
(chop off)
OF0H,OF0M,OF0L
ADC0 offset coefficient
OF1H,OF1L
ADC1 offset coefficient
GN0H,GN0M,GN0L ADC0 gain coefficient
GN1H,GN1L
ADC1 gain coefficient
ADC0H,ADC0M,ADC0L
ADC0 data
ADC1H,ADC1M,ADC1L
ADC1 data
ICON
Current Source Control Register
ICON.6
ICON.3
ICON.2
ICON.1
ICON.0
burnout current enable bit (0=disable)
IEXC2 pin select bit [0=AIN8 / 1=AIN7]
IEXC1 pin select bit [0=AIN7 / 1=AIN8]
IEXC2 enable bit (0=disable)
IEXC1 enable bit (0=disable)
DACCON
DAC Control register
DACCON.4
DACCON.3
DACCON.2
DACCON.1
DACCON.0
DAC pin select bit [0=DAC pin, 1=AINCOM pin]
ModeSelect (0=12bit, 1=8bit)
RangeSelect (0=2.5V, 1=AVDD)
Clear DAC (0=0V, 1=normal operation)
PowerDown DAC (0=off, 1=on)
DACH,DACL
PLLCON
DAC data registers
PLL Control register
PLLCON.7
PLLCON.6
PLLCON.4
PLLCON.3
PLLCON.2
PLLCON.1
PLLCON.0
oscillator powerdown control bit (0=XTAL on)
PLL lock indicator flag (0=out of lock)
returns state of EA pin latched at power-up
“fast interrupt” control bit (0=normal)
3-bit clock divider value, “CD” (default=3):
FCORE = 12,582,912Hz / 2CD
TIMECON Time Interval Counter Control Register
TIMECON.6
TIMECON.5
TIMECON.4
TIMECON.3
TIMECON.2
TIMECON.1
TIMECON.0
24-hour mode select (0=0..255hour, 1=0..23hour)
INTVAL timebase select bits
[128th sec, seconds, minutes, hours]
single time interval control bit (0=reload&restart)
time interval interrupt bit, “TII”
time interval enable bit (0=disable&clear)
time clock enable bit (0=disable)
INTVAL
TIC Interval Register
HTHSEC
SEC
MIN
HOUR
TIC Elapsed 128th Second Register
TIC Elapsed Seconds Register
TIC Elapsed Minutes Register
TIC Elapsed Hours Register
ECON
Data Flash/EE comand register
01h
02h
04h
05h
06h
81h READ byte
82h PROGRAM byte
0Fh EXIT ULOAD mode
F0h ENTER ULOAD mode
(all others reserved)
82h
READ page
PROGRAM page
VERIFY page
ERASE page
ERASE ALL
1
1
81h
ADC0CON1.7
ADC0CON1.6
ADC0CON1.5
ADC0CON1.2
ADC0CON1.1
ADC0CON1.0
EADRH,EADRL Data Flash/EE address registers
EDATA1,EDATA2,EDATA3,EDATA4
ISPI
WCOL
SPE
SPIM
CPOL
CPHA
SPR1
SPR0
SPIDAT
1
84h
SPICON
1
83h
Data Flash/EE data registers
SPI Control register
SPI interrupt (set by hardware at end of SPI transfer)
write collision error flag
SPI enable (0=I2C enable, 1=SPI enable)
master mode select (0=slave)
clock polarity select (0=SCLK idles low)
clock phase select (0=leading edge latch)
SPI bitrate select bits
bitrate = FCORE / [2,4,8,16] (slave: SPR0=SS)
SPI Data register
T3CON
85h
1
86h
1
master mode SDATA output bit
master mode SDATA output enable (0=disable)
master mode SCLK output bit
master mode SDATA input bit
master mode select bit (0=slave mode)
serial port reset
transmission direction status (0=RX,1=TX)
serial interface interrupt
I2CADD,I2CADD1 I2C slave Address registers
I2CDAT I2C Data register
PWMCON PWM Control register
PWMCON.6 PWM mode bits [0=disabled, 1=single/var.res.,
PWMCON.5
2=twin/8bit, 3=twin/16bit, 4=dual/16bitNRZ,
PWMCON.4
5=dual/8bit, 6=dual/16bitRZ, 7=reset/disable]
PWMCON.3 PWM clock divide bits
PWMCON.2
PWM counter = clock / [1,4,16,64]
PWMCON.1 PWM clock source bits [0=FXTAL/15, 1=FXTAL,
PWMCON.0
2=ext.clk. on P2.7, 3=FVCO(12.583MHz)]
PWM0H,PWM0L PWM0 data registers
PWM1H,PWM1L PWM1 data registers
DPCON
DPCON.6
DPCON.5
DPCON.4
DPCON.3
DPCON.2
DPCON.1
DPCON.0
Data Pointer Control register
data pointer auto-toggle enable (0=disable)
shadow data pointer mode control bits
[1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
main data pointer mode control bits
[1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
(not implemented to allow INC DPCON toggling)
data pointer select [0=main, 1=shadow]
Timer 3 baud rate enable (0=disable)
binary divide factor (DIV)
DIV = log[FCORE/(16·baudrate)] / log2
(rounded down)
T3FD
Timer 3 Fractional Divider register
T3FD = (2·FCORE) / (baudrate·2(DIV-1)) - 64
CHIPID Chip ID Register
(AX hex = ADuC845/7/8)
CFG845/CFG847/CFG848 Config. Register
CFG84x.7
CFG84x.0
extended stack-pointer enable (0=disable)
internal XRAM select (0=external XRAM)
WDCON
PRE3
PRE2
PRE1
PRE0
WDIR
WDS
WDE
WDWR
Watchdog Timer control register
watchdog timeout selection bits
0-7=[15.6,31.2,62.5,125,250,500,1000,2000]ms
8=0ms (immediate reset)
>8=reserved
watchdog interrupt response bit
watchdog status flag (1 indicates watchdog timeout)
watchdog enable control (0=disabled)
watchdog write enable bit (set to enable write)
PSMCON
PSMCON.7
PSMCON.6
PSMCON.5
PSMCON.4
PSMCON.3
PSMCON.2
PSMCON.1
PSMCON.0
Power Supply Monitor control register
DVDD status bit (1=above / 0=below trip point)
AVDD status bit (1=above / 0=below trip point)
PSM interrupt bit
DVDD trip point select bits
[4.63V, 3.08V, 2.93V, 2.63V]
AVDD trip point select bits
[4.63V, 3.08V, 2.93V, 2.63V]
PSM enable (1=on / 0=off)
SP
Stack Pointer
SPH
Stack Pointer High byte
IE
Interrupt Enable register #1
EA
EADC
ET2
ES
ET1
EX1
ET0
EX0
enable interrupts (0=all interrupts disabled)
enable ADCI (ADC interrupt)
enable TF2/EXF2 (Timer2 overflow interrupt)
enable RI/TI (serial port interrupt)
enable TF1 (Timer1 overflow interrupt)
enable IE1 (external interrupt 1)
enable TF0 (Timer0 overflow interrupt)
enable IE0 (external interrupt 0)
IEIP2 Interrupt Enable/Priority register #2
IEIP2.6
IEIP2.5
IEIP2.4
IEIP2.3
IEIP2.2
IEIP2.1
IEIP2.0
priority of TII interrupt (time interval)
priority of PSMI interrupt (power supply monitor)
priority of ISPI/I2CI interrupt (serial interface)
(this bit must contain zero)
enable TII interrupt (time interval)
enable PSMI interrupt (power supply monitor)
enable ISPI/I2CI interrupt (serial interface)
IP
Interrupt Priority register
PADC
PT2
PS
PT1
PX1
PT0
PX0
priority
priority
priority
priority
priority
priority
priority
TMOD
of ADCI (ADC interrupt)
of TF2/EXF2 (Timer2 overflow interrupt)
of RI/TI (serial port interrupt)
of TF1 (Timer1 overflow interrupt)
of IE1 (external interrupt 1)
of TF0 (Timer0 overflow interrupt)
of IE0 (external interrupt 0)
Timer Mode register
TMOD.3/.7
gate control bit (0=ignore INTx)
TMOD.2/.6
counter/timer select bit (0=timer)
TMOD.1/.5
timer mode selecton bits
TMOD.0/.4
[13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]
(upper nibble = Timer1, lower nibble = Timer0)
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer Control register
Timer1 overflow flag (auto cleared on vector
Timer1 run control (0=off, 1=run)
Timer0 overflow flag (auto cleared on vector
Timer0 run control (0=off, 1=run)
external INT1 flag (auto cleared on vector to
IE1 type (0=level trig, 1=edge trig)
external INT0 flag (auto cleared on vector to
IE0 type (0=level trig, 1=edge trig)
TH0,TL0
Timer0 registers
TH1,TL1
Timer1 registers
T2CON
Timer2 Control register
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CNT2
CAP2
to ISR)
to ISR)
ISR)
ISR)
overflow flag
external flag
receive clock enable (0=Timer1 used for RxD clk)
transmit clock enable (0=Timer1 used for TxD clk)
external enable (0=ignore T2EX, 1=cap/rld on T2EX)
run control (0=stop, 1=run)
timer/counter select (0=timer, 1=counter)
capture/reload select (0=reload, 1=capture)
TH2,TL2
Timer2 register
RCAP2H,RCAP2L Timer2 Reload/Capture
P0
Port0 register (also A0-A7 & D0-D7)
P1
Port1 register (analog & digital inputs)
T2EX
T2
timer/counter 2 capture/reload trigger
timer/counter 2 external input
P2
Port2 register (also A8-A15 & A16-A23)
P3
Port3 register
RD
WR
T1
T0
INT1
INT0
TxD
RxD
external data memory read strobe
external data memory write strobe
timer/counter 1 external input
timer/counter 0 external input
external interrupt 1
external interrupt 0
serial port transmit data line
serial port receive data line
SCON
SM0
SM1
I2CCON I C Control register
MDO
MDE
MCO
MDI
I2CM
I2CRS
I2CTX
I2CI
Timer 3 Control register
T3CON.7
T3CON.2
T3CON.1
T3CON.0
2
87h
(reserved)
(reserved)
(reserved)
00h
00h 84h
DPP
DPH
DPL
SP
00h
mnemonic
reset value
address
P0
TH1
00h 8Dh
TH0
00h 8Ch
TL1
00h 8Bh
TL0
00h 8Ah
TMOD
00h 89h
88h
0
88h
0
89h
0
8Ah
0
8Bh
0
8Ch
0
8Dh
0
8Eh
0
8Fh
FFh
90h
1
TCON
IT0
90h
1
91h
1
IE0
IT1
92h
1
93h
1
IE1
TR0
94h
1
95h
1
TF0
TR1
96h
1
97h
TF1
00h
(reserved)
00h 9Fh
(reserved)
00h 9Eh
(reserved)
9Dh
(reserved)
55h
(reserved)
00h 9Bh
(reserved)
00h 9Ah
(reserved)
00h 99h
0
98h
P1
T2
98h
0
99h
0
9Ah
0
9Bh
0
9Ch
0
9Dh
0
9Eh
0
9Fh
these bits are contained in this byte
mnemonic
address
reset value
ADCMODE.6
ADCMODE.5
ADCMODE.4
ADCMODE.3
ADCMODE.2
ADCMODE.1
ADCMODE.0
ADC0CON1
T2EX
00h
EWAIT
00h A7h
T3CON
00h A6h
T3FD
00h A5h
(reserved)
00h A4h
I2CADD
00h A3h
I2CDAT
00h A2h
SBUF
FFh A1h
SCON
A0h
1
1
A0h
RI
TI
A1h
1
A2h
1
RB8
TB8
A3h
1
A4h
1
REN
SM2
A5h
1
SM1
A6h
1
A7h
SM0
00h
DPCON
00h AFh
INTVAL
HOUR
MIN
SEC
HTHSEC
AEh
A0h
TIMECON
P2
00h A9h
A8h
0
A8h
0
A9h
0
AAh
0
ABh
0
ACh
0
ADh
0
AEh
0
AFh
00h
00h
PWMCON CFG845/7/8
(reserved)
B7h
00h
(reserved)
00h B4h
(reserved)
00h B3h
(reserved)
00h B2h
IEIP2
IE
FFh B1h
B0h
1
B0h
1
EX0
ET0
B1h
1
B2h
1
EX1
ET1
B3h
1
B4h
1
ES
ET2
B5h
1
B6h
1
EADC
SPH
00h BFh
(reserved)
00h BEh
(reserved)
00h BDh
PWM1H
PWM1L
PWM0H
BCh
00h
PWM0L
00h B9h
B8h
0
P3
RXD
B8h
0
B9h
0
TXD
INT0
BAh
0
BBh
0
INT1
T0
BCh
0
BDh
0
BEh
T1
PX0
PT0
PX1
PT1
PS
PT2
PADC
WR
IP
10h
C0h
0
C0h
0
C1h
0
C2h
0
C3h
1
C4h
0
C5h
0
C6h
0
0
00h
EDATA4
EDATA3
EDATA2
EDATA1
(reserved)
(reserved)
ECON
EADRH
00h C7h
EADRL
C6h
AXh
C2h
00h
(reserved)
00h CDh
(reserved)
00h CCh
(reserved)
00h CBh
CHIPID
CAh
(reserved)
00h
WDCON
C8h
0
WDWR
C8h
0
C9h
0
WDE
WDS
CAh
0
WDIR
CBh
0
CCh
0
PRE0
PRE1
CDh
0
CEh
0
PRE2
53h
(reserved)
D7h
(reserved)
00h
TH2
45h 0h
TL2
00h D4h
RCAP2H
07h D3h
RCAP2L
08h D2h
(reserved)
00h D1h
T2CON
D0h
0
D0h
CAP2
DEh
PLLCON
(reserved)
ICON
SF
ADCMODE ADC0CON1 ADC1CON
PSW
PSMCON
00h DFh
00h DEh
00h DDh
00h DCh
00h DBh
00h DAh
00h D9h
D8h
00h
ADC1L
ADC1H
ADC1M
ADC0CON2 (reserved)
*xxh E6h
*xxh
OF1H
*xxh E5h
*xxh EDh
OF1L
*xxh E4h
00h
SPIDAT
F7h
(reserved)
*xxh ECh
OF0H
ADC0H
ADC0M
ADC0L
ADCSTAT
F8h
SFR details
EA
R0
B7h
00h
RD
0
BFh
R1
C7h
R2
01h
PRE3
02h
1
000h
CFh
2
00h
0
R3
CNT2
03h
D1h
R4
3
0
R5
04h
TR2
05h
4
D2h
5
0
R6
EXEN2
06h
D3h
6
128 bytes
lower RAM
(direct or
indirect
addressing)
0
R7
TCLK
07h
(16MB
addressable)
D4h
7
2kB
0
R0
RCLK
R1
08h
external
data
memory
D5h
09h
8
internal
data
memory
0
9
CFG84x.0=0
EXF2
R2
CFG84x.0=1
D6h
0Ah
128 bytes
SFRs
upper RAM
(direct
(indirect
addressing
addressing
only)
only)
0
10
FFh
TF2
R3
D7h
R4
0Bh
P
0Ch
11
F1
12
OV
R5
RS0
0Dh
RS1
13
RAM & SFRs
F0
R6
AC
0Eh
CY
14
7FFh
0
R7
D8h
R0
0Fh
0
10h
15
( page 0 )
D9h
16
000h
0
R1
DAh
11h
0
17
DBh
R2
0
12h
DCh
18
0
R3
DDh
R4
13h
0
14h
19
DEh
20
0
R5
DFh
15h
ERR1
21
4kB
(1K pages)
data
Flash/EE
(accessible
through
SFRs)
NOXREF ERR0
R6
CAL
R7
16h
RDY1
17h
22
MAP KEY
23
0
R0
SPR0
18h
F8h
24
0
R1
SPR1
19h
FFFFFFh
( page 1023 )
F9h
25
3FFh
1
R2
CPHA
1Ah
FAh
26
0
R3
0
1Bh
“XRAM”
extended RAM space
ISPI
27
Flash/EE
data space
FFh
R4
Register Bank 2
R5
1Ch
Register Bank 1
1Dh
28
Register Bank 0
29
00h
RDY0
R6
01h
E0h
1Eh
02h
*xxh E3h
30
03h
*xxh EBh
04h
OF0M
05h
*xxh E2h
06h
R7
08h
*xxh EAh
07h
1Fh
09h
OF0L
20h
31
0Ah
00h E1h
32
0Bh
00h E9h
0Ch
ACC
0Dh
10h
E8h
0Eh
18h
11g
0
0Fh
19h
E0h
21h
1Ah
12h
0
33
1Bh
13h
E1h
14h
20h
0
1Ch
15h
21h
0
1Dh
16h
22g
F6h
1Eh
17h
23h
SPICON
1Fh
22h
24h
CPOL
23h
34
25h
28h
FBh
35
26h
29h
0
27h
2Ah
30h
SPIM
24h
Register Bank 3
36
2Bh
31h
E2h
2Ch
32h
FCh
2Dh
33h
0
2Eh
34h
SPE
2Fh
35h
FDh
25h
36h
0
37h
WCOL
37
26h
FEh
38
0
38h
E3h
40h
39h
0
41h
3Ah
E4h
42h
3Bh
0
43h
3Ch
E5h
44h
3Dh
0
45h
3Eh
E6h
46h
3Fh
0
47h
27h
E7h
28h
39
(reserved)
40
GN1H
48h
GN1L
49h
GN0H
4Ah
GN0M
4Bh
GN0L
4Ch
I2CCON
4Dh
0
4Eh
I2CI
4Fh
Bit Addressable
Area
E8h
29h
0
41
I2CTX
50h
E9h
51h
0
52h
I2CRS
53h
EAh
54h
0
55h
I2CM
56h
EBh
57h
0
2Ah
MDI
42
ECh
58h
0
59h
MCO
5Ah
EDh
5Bh
0
5Ch
MDE
5Dh
EEh
5Eh
0
5Fh
MDO
2Bh
EFh
43
(reserved)
60h
7Fh
68h
61h
F2h
69h
62h
00h
6Ah
63h
F0h
6Bh
64h
0
6Ch
65h
F0h
6Dh
66h
0
6Eh
67h
F1h
6Fh
2Ch
0
2Dh
44
F2h
45
0
70h
F3h
71h
0
72h
F4h
73h
0
74h
F5h
75h
0
76h
F7h
77h
(reserved)
2Eh
00h
46
(reserved)
78h
(reserved)
79h
(not used)
7Ah
I2CADD1
7Bh
(reserved)
7Ch
(bit addresses)
DACCON
7Dh
00h FDh
7Eh
DACH
7Fh
00h FCh
2Fh
DACL
MSB
address
47
General Purpose
Area
FBh
30h
(reserved)
...
48
(reserved)
...
05h
7Fh
LSB
address
127
B
(reserved)
SFR Map
Lower RAM
HEX
address
decimal
address
Data Memory: RAM, SFRs, user Flash/EE (all read/write)
SM2
REN
TB8
RB8
TI
RI
Serial communications Control register
UART mode control bits baud rate:
00 - 8bit shift register - FCORE/12
01 - 8bit UART
- variable
10 - 9bit UART
- FCORE/64(x2)
11 - 9bit UART
- variable
in modes 2&3, enables multiprocessor communication
receive enable control bit
in modes 2&3, 9th bit transmitted
in modes 2&3, 9th bit received
transmit interrupt flag
receive interrupt flag
SBUF
PCON
PCON.7
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
Serial port Buffer register
Power Control register
double baud rate control
ALE disable (0=normal, 1=forces ALE high)
general purpose flag
general purpose flag
power-down control bit (recoverable with hard reset)
idle-mode control (recoverable with enabled interrupt)
PSW
Program Status Word
CY
AC
F0
RS1
RS0
OV
F1
P
carry flag
auxiliary carry flag
general purpose flag 0
register bank select control bits
active register bank = [0,1,2,3]
overflow flag
general purpose flag 1
parity of ACC
DPP
Data Pointer Page
DPH,DPL (DPTR)
Data Pointer
ACC
Accumulator
B
auxiliary math register