return from sub.
return from int.
jump
jump if C set
jmp if C not set
jump if bit set
jmp if bit not set
jmp&clear if set
jump if A = 0
jump if A not 0
compare and
jump if not
equal
decrement and
jump if not zero
no operation
Legend
Rn
register addressing using R0-R7
@Ri
indirect addressing using R0 or R1
direct
8bit internal address (00h-FFh)
#data
8bit constant included in instruction
#data16 16bit constant included in instruction
bit
8bit direct address of bit
rel
signed 8bit offset
addr11
11bit address in current 2K page
addr16
16bit address
x
any of: Rn, @Ri, direct, #data
Instructions That Affect Flags
ADD A,x
C = carry out of bit 7
AC = carry out of bit 3
OV = carry out of bit 6, but not 7
ADDC A,x C = carry out of bit 7
AC = carry out of bit 3
OV = carry out of bit 6, but not 7
SUBB A,x C = borrow into bit 7
AC = borrow into bit 3
OV = borrow into bit 6, but not 7
MUL AB
C=0
OV = (result>255)
DIV AB
C=0
OV = divide by zero
DA A
RRC A
RLC A
SETB C
CLR C
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
CJNE x,y,rel
C = C or (x>100)
C = ACC.7
C = ACC.0
C=1
C=0
C = C and bit
C = C and NOTbit
C = C or bit
C = C or NOTbit
C = bit
C = (x<y)
52
51
50
49
48
47
46
45
44
43
42
41
40
15
P1.6 / ADC6
14
16
P1.7 / ADC7
27
29
SDATA / MOSI
40
43
EA
15
17
RESET
28
30
P2.0 / A8 / A16
41
44
PSEN
16
18
P3.0 / RxD
29
31
P2.1 / A9 / A17
42
45
ALE
17
19
P3.1 / TxD
30
32
P2.2 / A10 / A18
43
46
P0.0 / AD0
18
20
P3.2 / INT0
31
33
P2.3 / A11 / A19
44
47
P0.1 / AD1
19
21
P3.3/INT1/MISO/PWM1
32
34
XTAL1 (in)
45
48
P0.2 / AD2
20
22
DVDD
33
35
XTAL2 (out)
46
49
P0.3 / AD3
21
23
DGND
34
36
DVDD
47
50
DGND
22
24
P3.4 / T0 / PWMC /
PWM0 / EXTCLK
35 37,38 DGND
48
51
DVDD
23
25
P3.5 / T1 / CONVST
36
39
P2.4 / A12 / A20
49
52
P0.4 / AD4
24
26
P3.6 / WR
37
40
P2.5 / A13 / A21
50
53
P0.5 / AD5
SP
62
F800h
F7FFh
(NOP instructions)
internal
code space
0000h
62K x 8
program
Flash/EE
baudrate timer
P0.7 / AD7
VREF
8
CREF
7
(NOP instructions)
(NOP instructions)
8000h
7FFFh
internal
code space
2000h
1FFFh
32K bytes
Flash/EE
0000h
Interrupt Name
PSMCON.5
WDS
IE0
ADCI
TF0
IE1
TF1
ISPI/I2CI
RI/TI
TF2/EXF2
TIMECON.2
Power Supply Monitor Interrupt
WatchDog Timer Interrupt
External Interrupt 0
End of ADC Conversion Interrupt
Timer0 Overflow Interrupt
External Interrupt 1
Timer1 Overflow Interrupt
SPI/I2C Interrupt
UART Interrupt
Timer2 Interrupt
Time Interval Counter Interrupt
BUF
10
DAC1
38
PWM0
39
PWM1
22
T0
23
T1
1
T2
2
T2EX
asynchronous
serial port
(UART)
18
INT0
19
INT1
256 x 8
user RAM
1-clock
8052
watchdog
timer
MCU
core
power supply
monitor
synchronous
serial interfaces
2
(SPI & I C)
16bit
counter
timers
time
interval
counter
OSC &
PLL
* pin numbers refer to MQFP package
internal
code space
8K bytes
Flash/EE
A Precision Analog Flash MCU
The ADuC842/ADuC843 is:
ADC:
Interrupt Vector Addresses
Interrupt Bit
DAC1
2K x 8
user “XRAM”
downloader
debugger
BUF
8
FFFFh
0000h
© 2003 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the
property of their respective companies.
Purchase of licensed I2C components of Analog
Devices or one of its sublicensed Associated
Companies conveys a license for the purchaser
under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the
system conforms to the I2C Standard Specification
as defined by Philips.
Printed in the U.S.A.
G03602-4-12/03(0)
Flash/EE
2.5V
bandgap
reference
P0.6 / AD6
32
62K bytes
Flash/EE
4K x 8
data
(-3 mV/oC)
POR
FFFFh
DAC0
PWM
TEMP
sensor
Code Memory Space Options
FFFFh
9
33
55
BUF
32
54
AIN
MUX
DAC0
DAC
control
XTAL2
52
C
FP
Q
M
P2.7/A15/A23/PWM1
51
12bit ADC
T/H
XTAL1
42
P2.6/A14/A22/PWM0
DACs on ADuC842 only
ADC
control
&
calibration
12
39
41
1
2
3
4
11
12
13
14
SS
SCLOCK
SP
FP
Q
38
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
®
ADuC842/ADuC843
26
27
19
28
P3.7 / RD
23
SCLOCK
SDATA / MOSI
MISO
26
27
C
M
25
hardware
CONVST
P3.0 (RxD)
P3.1 (TxD)
P3.2 (INT0)
P3.3 (INT1 / MISO / PWM1)
P3.4 (T0/PWMC/PWM0/EXTCLK)
P3.5 (T1 / CONVST)
P3.6 (WR)
P3.7 (RD)
P1.5 / ADC5 / SS
13
16
17
18
19
22
23
24
25
P1.4 / ADC4
14
P2.0 (A8 / A16)
P2.1 (A9 / A17)
P2.2 (A10 / A18)
P2.3 (A11 / A19)
P2.4 (A12 / A20)
P2.5 (A13 / A21)
P2.6 (A14 / A22 / PWM0)
P2.7 (A15 / A23 / PWM1)
13
14
15
16
17
18
19
20
21
22
23
24
25
26
11
12
28
29
30
31
36
37
38
39
DAC0
DAC1
single-pin
emulator
11
12
42
41
40
9
10
FUNCTIONAL
BLOCK
DIAGRAM
ALE
PSEN
EA
VREF
P1.0 (ADC0 / T2)
P1.1 (ADC1 / T2EX)
P1.2 (ADC2)
P1.3 (ADC3)
P1.4 (ADC4)
P1.5 (ADC5 / SS)
P1.6 (ADC6)
P1.7 (ADC7)
CREF
10
ADuC842
52pin MQFP
TOP VIEW
(not to scale)
1
2
3
4
11
12
13
14
9
8
15
16
17
18
19
20
21
22
23
24
25
26
27
28
7
56pin CSP
TOP VIEW
(not to scale)
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
AVDD
56
55
54
53
52
51
50
49
48
47
46
45
44
43
4,5
42
41
40
39
38
37
36
35
34
33
32
31
30
29
pin 1 identifier
ADuC842
43
44
45
46
49
50
51
52
FP
Q
SP
M
C
by
te
s
O
S
pe C
rio
d
s
clear A to zero
complement A
rotate A left
...through C
rotate A right
...through C
swap nibbles
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADuC842/843 MicroConverter
Quick Reference Guide
17
3
4
4
4
3
4
3
3
3
3
4
4
4
3
3
4
4
4
4
3
4
1
P1.3 / ADC3
39
38
37
36
35
34
33
32
31
30
29
28
27
16
2
3
1
1
2
3
2
1
2
2
3
3
3
2
2
3
3
3
3
2
3
1
3
pin 1 identifier
TxD
call subroutine
logical XOR
4
1
2
3
4
5
6
7
8
9
10
11
12
13
RxD
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JC
rel
JNC rel
JB
bit,rel
JNB
bit,rel
JBC
bit,rel
JZ
rel
JNZ
rel
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
CJNE @Ri,#data,rel
DJNZ Rn,rel
DJNZ direct, rel
NOP
by
te
s
O
S
pe C
rio
d
Program Branching
P1.2 / ADC2
15
move bit to bit
logical OR
1
2
2
2
2
3
1
2
2
2
2
3
1
2
2
2
2
3
1
1
1
1
1
1
1
2
RESET
AND bit with C
AND (NOTbit) with C
OR bit with C
OR (NOTbit) with C
logical AND
1
1
2
2
2
3
1
1
2
2
2
3
1
1
2
2
2
3
1
1
1
1
1
1
1
3
21
35
47
complement bit
1
2
1
2
1
2
2
2
2
2
2
2
A,Rn
A,@Ri
A,direct
A,#data
direct,A
direct,#data
A,Rn
A,@Ri
A,direct
A,#data
direct,A
direct,#data
A,Rn
A,@Ri
A,direct
A,#data
direct,A
direct,#data
A
A
A
A
A
A
A
P1.1 / ADC1 / T2EX
DGND
set bit to one
1
2
1
2
1
2
2
2
2
2
2
2
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
RLC
RR
RRC
SWAP
P1.0 / ADC0 / T2
1
DVDD
clear bit to zero
multiply A by B
divide A by B
decimal adjust
56
2
6
C
bit
C
bit
C
bit
C,bit
C,/bit
C,bit
C,/bit
C,bit
bit,C
decrement
Logical Operations
s
CLR
CLR
SETB
SETB
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
increment
1
6 6,7,8 AGND
* INC DPTR increments the 24bit value DPP/DPH/DPL
by
te
s
O
S
pe C
rio
d
Boolean Variable Manipulation
subtract from A
with borrow
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
3
1
1
2
2
9
9
2
20
34
48
exchg low digits
add with carry
1
1
2
2
1
1
2
2
1
1
2
2
1
1
1
2
1
1
1
1
2
1
1
1
5
exchange bytes
add source to A
AVDD
push onto stack
pop from stack
A,Rn
A,@Ri
A,direct
A,#data
A,Rn
A,@Ri
A,direct
A,#data
A,Rn
A,@Ri
A,direct
A,#data
A
Rn
@Ri
direct
DPTR *
A
Rn
@Ri
direct
AB
AB
A
Pin Functions
AGND
move to/from
data memory
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
INC
INC
INC
INC
DEC
DEC
DEC
DEC
MUL
DIV
DA
1
2
2
2
1
2
2
2
2
2
3
3
2
2
2
3
4
4
4
4
4
4
2
2
1
2
2
2
s
move from
code memory
Arithmetic Operations
by
te
s
O
S
pe C
rio
d
move
1
1
2
2
1
2
2
2
2
2
3
3
1
2
2
3
1
1
1
1
1
1
2
2
1
1
2
1
s
MOV A,Rn
MOV A,@Ri
MOV A,direct
MOV A,#data
MOV Rn,A
MOV Rn,direct
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct,@Ri
MOV direct,direct
MOV direct,#data
MOV @Ri,A
MOV @Ri,direct
MOV @Ri,#data
MOV DPTR,#data16
MOVC A,@A+DPTR
MOVC A,@A+PC
MOVX A,@Ri
MOVX A,@DPTR
MOVX @Ri,A
MOVX @DPTR,A
PUSH direct
POP direct
XCH A,Rn
XCH A,@Ri
XCH A,direct
XCHD A,@Ri
by
te
s
O
S
pe C
rio
d
Data Transfer Operations
s
Instruction Set
Vector
Address
Relative
Priority
43h
5Bh
03h
33h
0Bh
13h
1Bh
3Bh
23h
2Bh
53h
1
2
3
4
5
6
7
8
9
10
11
12bit, 5µs, 8channel, self calibrating
0.5LSB INL & 70dB SNR
DAC (ADuC842 only):
dual, 12bit, 15µs, voltage output
<1LSB DNL
Flash/EEPROM:
62K bytes Flash/EE program memory
4K bytes Flash/EE data memory
Microcontroller:
“single-cycle” 8052, up to 16.8MIPS
32 I/O lines, programmable PLL clock
(131KHz to 16.8MHz from 32KHz crystal)
Embedded Tools Support:
on-chip download/debug & single-pin emulation functions
Other on-chip features:
temperature monitor, power supply monitor, watchdog
timer, flexible serial interface ports, voltage reference,
time interval counter, dual 8/16bit PWM, power-on-reset
REV. 0
ADCCON1
lower RAM
details
SFR details
00h
PCON
87h
(reserved)
00h 83h
07h 82h
FFh 81h
80h
(reserved)
(reserved)
00h
(reserved)
00h
00h 84h
DPP
00h 8Dh
00h 8Ch
00h 8Bh
DPH
DPL
SP
00h 8Ah
00h 89h
88h
P0
TH1
(not used)
00h
TH0
TL1
TL0
00h 93h
00h 92h
TMOD
FFh 91h
90h
TCON
00h
(not used)
00h 9Eh
(not used)
9Dh
(not used)
55h
I2CADD3
00h 9Bh
I2CADD2
00h 9Ah
I2CADD1
00h 99h
00h
(not used)
T3CON
T3FD
DPCON
INTVAL
00h A6h
00h A5h
AEh
HOUR
00h
PWMCON
00h A7h
B7h
00h
CFG842
CFG843
00h AFh
00h
00h
(reserved)
SPH
(not used)
00h BDh
00h BEh
(not used)
00h BFh
00h
EDATA3
EDATA2
00h CDh
EDATA4
EADRH
00h C7h
EADRL
00h
C6h
(reserved)
53h
(reserved)
D7h
(reserved)
00h
(reserved)
(reserved)
TH2
DEh
PLLCON
PSMCON
DFh
40h
(reserved)
EFh
00h
SPIDAT
F7h
ADCCON1
ADCCON2
ADCI
DMA
CCONV
SCONV
CS3
CS2
CS1
CS0
SPR1
F9h
0
SPR0
F8h
0
SPICON
F8h
04h
* calibration coefficients are preconfigured at power-up to factory calibrated values
ADCCON3
ADCCON3.7
ADCCON3.6
ADCCON3.5
ADCCON3.4
ADCCON3.3
ADCCON3.2
ADCCON3.1
ADCCON3.0
ADCDATAH
ADCDATAL
DAC1H,DAC1L
DAC1 data registers
DAC0H,DAC0L
DAC0 data registers
PLLCON
PLL Control register
PLLCON.7
PLLCON.6
PLLCON.5
PLLCON.4
PLLCON.3
PLLCON.2
PLLCON.1
PLLCON.0
oscillator powerdown control bit (0=XTAL on)
PLL lock indicator flag (0=out of lock)
(this bit must contain zero)
(this bit must contain zero)
“fast interrupt” control bit (0=normal)
3-bit clock divider value, “CD” (default=3):
FCORE = 16,777,216Hz / 2CD
TIMECON Time Interval Counter Control Register
TIMECON.6
TIMECON.5
TIMECON.4
TIMECON.3
TIMECON.2
TIMECON.1
TIMECON.0
24-hour mode select (0=0..255hour, 1=0..23hour)
INTVAL timebase select bits
[128th sec, seconds, minutes, hours]
single time interval control bit (0=reload&restart)
time interval interrupt bit, “TII”
time interval enable bit (0=disable&clear)
time clock enable bit (0=disable)
INTVAL
TIC Interval Register
HTHSEC
SEC
MIN
HOUR
TIC Elapsed 128th Second Register
TIC Elapsed Seconds Register
TIC Elapsed Minutes Register
TIC Elapsed Hours Register
1
80h
Data Flash/EE comand register
01h
02h
04h
05h
06h
READ page
PROGRAM page
VERIFY page
ERASE page
ERASE ALL
EADRH,EADRL
82h PROGRAM byte
0Fh EXIT ULOAD mode
F0h ENTER ULOAD mode
(all others reserved)
Data Flash/EE address registers
EDATA1,EDATA2,EDATA3,EDATA4
Data Flash/EE data registers
1
81h
1
PSMCON.6
PSMCON.5
PSMCON.4
PSMCON.3
PSMCON.2
PSMCON.1
PSMCON.0
Power Supply Monitor control register
PSM status bit (1=normal / 0=fault)
PSM interrupt bit
trip point select bits
[(reserved), 3.08V, 2.93V, (reserved)]
(this bit must contain zero)
(reserved)
PSM powerdown control (1=on / 0=off)
SP
Stack Pointer
DAC Control register
ModeSelect (0=12bit, 1=8bit)
DAC1 RangeSelect (0=VREF, 1=VDD)
DAC0 RangeSelect (0=VREF, 1=VDD)
Clear DAC1 (0=0V, 1=normal operation)
Clear DAC0 (0=0V, 1=normal operation)
SynchronousUpdate (1=asynchronous)
PowerDown DAC1 (0=off, 1=on)
PowerDown DAC0 (0=off, 1=on)
ISPI
WCOL
SPE
SPIM
CPOL
CPHA
SPR1
SPR0
SPI Control register
SPI interrupt (set by hardware at end of SPI transfer)
write collision error flag
SPI enable (0=I2C enable, 1=SPI enable)
master mode select (0=slave)
clock polarity select (0=SCLK idles low)
clock phase select (0=leading edge latch)
SPI bitrate select bits
bitrate = FCORE / [2,4,8,16] (slave: SPR0=SS)
SPIDAT
1
SPI Data register
83h
84h
1
PSMCON
DACCON
DACCON.7
DACCON.6
DACCON.5
DACCON.4
DACCON.3
DACCON.2
DACCON.1
DACCON.0
slave mode stop interrupt enable bit (0=disable)
slave mode general call status flag
slave mode interrupt decode bits
[start, repeated-start, data, stop]
master mode select bit (0=slave mode)
serial port reset
transmission direction status (0=RX,1=TX)
serial interface interrupt
MDO
MDE
MCO
MDI
I2CM
master
master
master
master
master
mode
mode
mode
mode
mode
SDATA output bit
SDATA output enable (0=disable)
SCLK output bit
SDATA input bit
select bit (0=slave mode)
85h
1
86h
Watchdog Timer control register
watchdog timeout selection bits
0-7=[15.6,31.2,62.5,125,250,500,1000,2000]ms
8=0ms (immediate reset)
>8=reserved
watchdog interrupt response bit
watchdog status flag (1 indicates watchdog timeout)
watchdog enable control (0=disabled)
watchdog write enable bit (set to enable write)
enable
enable
enable
enable
enable
enable
enable
enable
8Dh
1
PRE3
PRE2
PRE1
PRE0
WDIR
WDS
WDE
WDWR
Interrupt Enable register #1
I2CADD I2C slave Address register
87h
WDCON
EA
EADC
ET2
ES
ET1
EX1
ET0
EX0
1
0
extended stack-pointer enable (0=disable)
PWM pins select (0=P2.6/P2.7,1=P3.4/P3.3)
DAC output buffer bypass (0=buffer enabled)
external clock select (0=internal clock)
(this bit must contain 0)
(this bit must contain 0)
select SPI pins (0=default, 1=P3.3/P3.4/P3.5)
internal XRAM select (0=external XRAM)
IE
8Bh
8Ch
CFG842.7
CFG842.6
CFG842.5
CFG842.4
CFG842.3
CFG842.2
CFG842.1
CFG842.0
ADC Offset
calibration coefficients
I2CCON I2C Control register (in master mode)
0
(AX hex = ADuC842/843)
CFG842/CFG843 ADuC84x Config. Register
ADCOFSH
ADCOFSL
0
8Eh
0
CHIPID Chip ID Register
SPH
I2C secondary slave Address registers
PWMCON PWM Control register
PWMCON.7
PWMCON.6
PWMCON.5
PWMCON.4
PWMCON.3
PWMCON.2
PWMCON.1
PWMCON.0
disable P2.6/P3.4 PWM output (0=enable)
PWM mode bits [0=disabled, 1=single/var.res.,
2=twin/8bit, 3=twin/16bit, 4=dual/16bitNRZ,
5=dual/8bit, 6=dual/16bitRZ, 7=(reserved)]
PWM clock divide bits
PWM counter = clock / [1,4,16,64]
PWM clock source bits [0=FXTAL/15, 1=FXTAL,
2=T0 ext.int.rate, 3=FVCO(16.777MHz)]
PWM0H,PWM0L PWM0 data registers
PWM1H,PWM1L PWM1 data registers
mnemonic
reset value
address
Timer 3 Fractional Divider register
T3FD = (2·FCORE) / (baudrate·2(DIV-1)) - 64
ADC Gain
calibration coefficients
SPICON
82h
0
88h
0
89h
0
DMA address pointer
T3FD
ADCGAINH
ADCGAINL
0
8Ah
ADC Data registers
DMAP,DMAH,DMAL
I2CDAT I2C Data register
8Fh
1
90h
1
IT0
IE0
91h
1
92h
1
IT1
IE1
93h
1
94h
1
TR0
TF0
95h
1
96h
1
97h
ADC Control register #3
busy indicator flag (0=ADC not active)
(this bit must contain zero)
number of averages selection bits:
[15,1,31,63]
(this bit must contain zero)
(this bit must contain one when calibrating)
cal type select (0=offset, 1=gain)
start calibration bit, cleared by hardware
I2CADD1,I2CADD2,I2CADD3
TR1
9Bh
0
9Ch
0
9Dh
0
9Eh
0
9Fh
ADC Control register #2
ADC interrupt flag
DMA mode enable
continuous conversion enable bit
single conversion start bit
input channel select bits:
0 - 7 = ADC0 - ADC7
8 = temperature sensor
9=DAC0, A=DAC1, B=AGND, C=VREF
I2CSI
I2CGC
I2CID1
I2CID0
I2CM
I2CRS
I2CTX
I2CI
these bits are contained in this byte
mnemonic
address
reset value
ADC Control register #1
ADC mode (0=off, 1=on)
external Vref select bit (0=on-chip Vref)
conversion time = 16 / ADCclk
ADCclk = 16,777,216Hz / [32,4,8,2]
acquisition time select bits
acq time = [1,2,3,4] / ADCclk
Timer2 convert enable
external CONVST enable
I2CCON I2C Control register (in slave mode)
TF1
0
9Ah
0
T2
98h
0
0
99h
TI
RB8
TB8
REN
SM2
SM1
SM0
A4h
1
A5h
1
A6h
1
A7h
T2EX
RI
1
A0h
1
A1h
1
A2h
A3h
1
1
0
A8h
0
A9h
0
AAh
0
ABh
0
ACh
0
ADh
0
AEh
0
AFh
1
B0h
1
EX0
ET0
B1h
1
B2h
1
EX1
ET1
B3h
1
B4h
1
ES
ET2
B5h
1
B6h
1
EADC
EA
B7h
0
B8h
0
RXD
TXD
B9h
0
BAh
0
INT0
INT1
BBh
0
BCh
0
T0
T1
BDh
0
BEh
0
WR
PX0
PT0
PX1
PT1
PS
PT2
PADC
BFh
RD
0
C0h
0
C1h
0
C2h
0
C3h
1
C4h
0
C5h
0
C6h
0
C7h
0
WDWR
C8h
0
C9h
0
WDE
WDS
CAh
0
WDIR
CBh
0
CCh
0
PRE0
PRE1
CDh
0
CEh
0
PRE2
PRE3
TR2
D2h
0
EXEN2
D3h
0
TCLK
D4h
0
RCLK
D5h
0
EXF2
D6h
0
TF2
D7h
CFh
0
CAP2
0
D1h
CNT2
0
D0h
P
F1
OV
RS0
RS1
F0
AC
CY
0
CS0
D8h
0
CS1
D9h
0
CS2
DAh
0
CS3
DBh
DDh
0
DCh
0
CCONV SCONV
0
DMA
DEh
0
ADCI
DFh
0
E0h
0
E1h
0
E2h
0
E3h
0
E4h
0
E5h
0
E6h
R0
0
00h
E7h
0
0
R1
I2CI
01h
E8h
R2
1
0
R3
02h
I2CTX
03h
2
000h
E9h
3
00h
0
R4
I2CRS
04h
EAh
4
0
R5
I2CM
R6
05h
(16M bytes
addressable)
EBh
06h
5
2K bytes
I2CID0
6
128 bytes
lower RAM
(direct or
indirect
addressing)
ECh MDI 0
R7
I2CID1
07h
EDhMCO 0
R0
7
external
data
memory
I2CGC
R1
08h
internal
data
memory
EEh MDE 0
09h
8
CFG842.0=0
I2CSI
9
128 bytes
SFRs
upper RAM
(direct
(indirect
addressing
addressing
only)
only)
CFG842.0=1
EFh MDO 0
R2
0
0Ah
F0h
10
FFh
0
R3
F1h
0Bh
0
11
F2h
R4
0
R5
0Ch
F3h
0Dh
12
0
13
RAM & SFRs
F4h
R6
0
R7
0Eh
7FFh
F5h
0Fh
14
( page 0 )
0
15
000h
F6h
R0
0
R1
10h
F7h
11h
16
MAP KEY
17
SPICON
R2
F8h
R3
12h
0
13h
18
SPR0
19
F8h
R4
0
R5
14h
SPR1
15h
20
F9h
21
1
R6
CPHA
16h
FAh
22
ADCCON1.7
ADCCON1.6
ADCCON1.5
ADCCON1.4
ADCCON1.3
ADCCON1.2
ADCCON1.1
ADCCON1.0
ECON
4K bytes
(1K pages)
data
Flash/EE
(accessible
through
SFRs)
0
R7
CPOL
R0
17h
FBh
18h
23
0
24
SPIM
R1
FCh
19h
( page 1023 )
0
25
3FFh
SPE
R2
FDh
1Ah
0
26
FFFFFFh
WCOL
R3
FEh
1Bh
“XRAM”
extended RAM space
0
27
Flash/EE
data space
ISPI
R4
FFh
1Ch
Register Bank 3
R5
28
Register Bank 2
R6
1Dh
Register Bank 1
1Eh
29
Register Bank 0
30
P1
00h
98h
01h
(not used)
02h
I2CADD
03h
I2CDAT
04h
SBUF
05h
SCON
06h
R7
00h A4h
07h
1Fh
00h A3h
20h
31
00h A2h
32
FFh A1h
08h
A0h
09h
MIN
0Ah
SEC
0Bh
HTHSEC
0Ch
A0h
0Dh
TIMECON
0Eh
00h A9h
0Fh
P2
21h
A8h
33
(reserved)
10h
00h B4h
11g
(reserved)
12h
00h B3h
13h
(reserved)
14h
00h B2h
15h
IEIP2
16h
FFh B1h
17h
IE
22h
B0h
34
PWM1H
18h
BCh
20h
19h
PWM1L
21h
1Ah
PWM0H
22g
1Bh
00h
23h
1Ch
PWM0L
24h
1Dh
00h B9h
25h
1Eh
P3
26h
1Fh
B8h
27h
23h
EDATA1
24h
35
(reserved)
36
(reserved)
28h
ECON
30h
29h
IP
31h
2Ah
AXh
32h
2Bh
C2h
33h
2Ch
10h
34h
2Dh
C0h
35h
2Eh
(reserved)
36h
2Fh
00h CCh
37h
25h
(reserved)
26h
37
00h CBh
38
CHIPID
38h
CAh
39h
(reserved)
3Ah
00h
3Bh
WDCON
3Ch
C8h
3Dh
TL2
3Eh
00h D4h
3Fh
RCAP2H
27h
00h D3h
40h
RCAP2L
48h
41h
D2h
49h
42h
(reserved)
4Ah
43h
00h
4Bh
44h
T2CON
4Ch
45h
D0h
4Dh
46h
DMAP
4Eh
47h
DMAH
4Fh
DMAL
39
Bit Addressable
Area
(reserved)
28h
PSW
29h
40
(reserved)
41
(reserved)
50h
(reserved)
51h
00h
52h
00h DAh
53h
00h D9h
54h
00h
55h
D8h
56h
E0h
57h
ADCCON2 ADCDATAL ADCDATAH (reserved)
2Ah
(reserved)
42
(reserved)
58h
(reserved)
59h
(reserved)
5Ah
(reserved)
5Bh
(reserved)
5Ch
00h
5Dh
ACC
5Eh
E8h
5Fh
(reserved)
2Bh
(reserved)
43
(reserved)
60h
(reserved)
68h
61h
(reserved)
69h
62h
(reserved)
6Ah
63h
I2CCON
6Bh
64h
(reserved)
6Ch
65h
00h
6Dh
66h
*00h F5h
6Eh
67h
*00h F4h
6Fh
2Ch
*20h F3h
2Dh
44
*00h F2h
45
00h F1h
70h
F0h
78h
71h
(reserved)
79h
72h
04h
7Ah
73h
ADCOFSL ADCOFSH ADCGAINL ADCGAINH ADCCON3
7Bh
74h
DACCON
7Ch
75h
00h FDh
7Dh
76h
DAC1H
7Eh
77h
00h FCh
7Fh
2Eh
DAC1L
2Fh
46
(bit addresses)
00h FBh
MSB
address
47
General Purpose
Area
DAC0H
30h
00h FAh
...
48
DAC0L
...
04h F9h
7Fh
LSB
address
127
B
(reserved)
SFR Map
Lower RAM
HEX
address
decimal
address
Data Memory: RAM, SFRs, user Flash/EE (all read/write)
DPCON
DPCON.6
DPCON.5
DPCON.4
DPCON.3
DPCON.2
DPCON.1
DPCON.0
T3CON
T3CON.7
T3CON.2
T3CON.1
T3CON.0
Data Pointer Control register
data pointer auto-toggle enable (0=disable)
shadow data pointer mode control bits
[1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
main data pointer mode control bits
[1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
(not implemented to allow INC DPCON toggling)
data pointer select [0=main, 1=shadow]
Timer 3 Control register
Timer 3 baud rate enable (0=disable)
binary divide factor (DIV)
DIV = log[FCORE/(16·baudrate)] / log2
(rounded down)
Stack Pointer High byte
interrupts (0=all interrupts disabled)
ADCI (ADC interrupt)
TF2/EXF2 (Timer2 overflow interrupt)
RI/TI (serial port interrupt)
TF1 (Timer1 overflow interrupt)
IE1 (external interrupt 1)
TF0 (Timer0 overflow interrupt)
IE0 (external interrupt 0)
IEIP2 Interrupt Enable/Priority register #2
IEIP2.6
IEIP2.5
IEIP2.4
IEIP2.3
IEIP2.2
IEIP2.1
IEIP2.0
priority of TII interrupt (time interval)
priority of PSMI interrupt (power supply monitor)
priority of ISPI interrupt (serial interface)
(this bit must contain zero)
enable TII interrupt (time interval)
enable PSMI (power supply monitor interrupt)
enable ISPI interrupt (serial interface)
IP
Interrupt Priority register
PADC
PT2
PS
PT1
PX1
PT0
PX0
priority
priority
priority
priority
priority
priority
priority
TMOD
of
of
of
of
of
of
of
ADCI (ADC interrupt)
TF2/EXF2 (Timer2 overflow interrupt)
RI/TI (serial port interrupt)
TF1 (Timer1 overflow interrupt)
IE1 (external interrupt 1)
TF0 (Timer0 overflow interrupt)
IE0 (external interrupt 0)
Timer Mode register
TMOD.3/.7
gate control bit (0=ignore INTx)
TMOD.2/.6
counter/timer select bit (0=timer)
TMOD.1/.5
timer mode selecton bits
TMOD.0/.4
[13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]
(upper nibble = Timer1, lower nibble = Timer0)
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer Control register
Timer1 overflow flag (auto cleared on vector
Timer1 run control (0=off, 1=run)
Timer0 overflow flag (auto cleared on vector
Timer0 run control (0=off, 1=run)
external INT1 flag (auto cleared on vector to
IE1 type (0=level trig, 1=edge trig)
external INT0 flag (auto cleared on vector to
IE0 type (0=level trig, 1=edge trig)
TH0,TL0
Timer0 registers
TH1,TL1
Timer1 registers
T2CON
Timer2 Control register
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CNT2
CAP2
to ISR)
to ISR)
ISR)
ISR)
overflow flag
external flag
receive clock enable (0=Timer1 used for RxD clk)
transmit clock enable (0=Timer1 used for TxD clk)
external enable (0=ignore T2EX, 1=cap/rld on T2EX)
run control (0=stop, 1=run)
timer/counter select (0=timer, 1=counter)
capture/reload select (0=reload, 1=capture)
TH2,TL2
Timer2 register
RCAP2H,RCAP2L Timer2 Reload/Capture
P0
Port0 register (also A0-A7 & D0-D7)
P1
Port1 register (analog & digital inputs)
T2EX
T2
timer/counter 2 capture/reload trigger
timer/counter 2 external input
P2
Port2 register (also A8-A15 & A16-A23)
P3
Port3 register
RD
WR
T1
T0
INT1
INT0
TxD
RxD
external data memory read strobe
external data memory write strobe
timer/counter 1 external input
timer/counter 0 external input
external interrupt 1
external interrupt 0
serial port transmit data line
serial port receive data line
SCON
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Serial communications Control register
UART mode control bits baud rate:
00 - 8bit shift register - FCORE/12
01 - 8bit UART
- variable
10 - 9bit UART
- FCORE/64(x2)
11 - 9bit UART
- variable
in modes 2&3, enables multiprocessor communication
receive enable control bit
in modes 2&3, 9th bit transmitted
in modes 2&3, 9th bit received
transmit interrupt flag
receive interrupt flag
SBUF
PCON
PCON.7
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
Serial port Buffer register
Power Control register
double baud rate control
ALE disable (0=normal, 1=forces ALE high)
general purpose flag
general purpose flag
power-down control bit (recoverable with hard reset)
idle-mode control (recoverable with enabled interrupt)
PSW
Program Status Word
CY
AC
F0
RS1
RS0
OV
F1
P
carry flag
auxiliary carry flag
general purpose flag 0
register bank select control bits
active register bank = [0,1,2,3]
overflow flag
general purpose flag 1
parity of ACC
DPP
Data Pointer Page
DPH,DPL (DPTR)
Data Pointer
ACC
Accumulator
B
auxiliary math register