BIG MEMORY
56
P1.0 / T2 / PWM0
A,source
1,2
12
Rn
register addressing using R0-R7
2
1
P1.1 / T2EX / PWM1
ADD
A,#data
bit
8bit direct address of bit
8
10
1,2
12
rel
signed 8bit offset
9
11
P1.4 / AIN1
1
24
addr11
11bit address in current 2K page
10
12
P1.5 / AIN2
addr16
16bit address
44
PSEN
42
45
ALE
3
24
17
19
P3.1 / TxD
30
32
P2.2 / A10 / A18
43
46
P0.0 / AD0
A,source
1,2
12
18
20
P3.2 / INT0
31
33
P2.3 / A11 / A19
44
47
P0.1 / AD1
A,#data
2
12
19
21
P3.3 / INT1
32
34
XTAL1 (in)
45
48
P0.2 / AD2
2
12
20
22
DVDD
33
35
XTAL2 (out)
46
49
P0.3 / AD3
3
24
21
23
DGND
34
36
DVDD
47
50
DGND
1,2
12
22
24
P3.4 / T0 / PWMclk
35 37,38 DGND
48
51
DVDD
25
P3.5 / T1
36
39
P2.4 / A12 / A20
49
52
P0.4 / AD4
MOVX A,@Ri
1
24
XRL
direct,#data
MOVX A,@DPTR
MOVX @Ri,A
move to/from
data memory
MOVX @DPTR,A
logical XOR
2
12
2
12
24
26
P3.6 / WR
37
40
P2.5 / A13 / A21
50
53
P0.5 / AD5
3
24
25
27
P3.7 / RD
38
41
P2.6 / A14 / A22
51
54
P0.6 / AD6
26
28
SCLOCK
39
42
P2.7 / A15 / A23
52
55
P0.7 / AD7
1
24
CLR
A
clear A to zero
1
12
1
24
CPL
A
complement A
1
12
1
24
RL
A
rotate A left
1
12
push onto stack
2
24
RLC
A
...through C
1
12
POP
direct
pop from stack
2
24
RR
A
rotate A right
1
12
XCH
A,source
exchange bytes 1,2
12
RRC
A
...through C
1
12
exchg low digits
12
SWAP A
swap nibbles
1
12
1
Program Branching
ACALL addr11
LCALL addr16
call subroutine
Boolean Variable Manipulation
2
24
CLR
C
3
24
CLR
bit
RET
return from sub.
1
24
SETB C
RETI
return from int.
1
24
SETB bit
AJMP addr11
LJMP addr16
SJMP rel
jump
clear bit to zero
set bit to one
1
12
1
12
2
12
1
12
2
12
2
24
CPL
C
3
24
CPL
bit
2
24
ANL
C,bit
AND bit with C
2
24
1
24
ANL
C,/bit
...NOTbit with C
2
24
C,bit
OR bit with C
2
24
...NOTbit with C
2
24
2
12
2
24
complement bit
@A+DPTR
JZ
rel
jump if A = 0
2
24
ORL
JNZ
rel
jump if A not 0
2
24
ORL
C,/bit
3
24
MOV
C,bit
3
24
MOV
bit,C
3
24
JC
rel
jump if C set
2
24
3
24
JNC
rel
jmp if C not set
2
24
2
24
JB
bit,rel
jump if bit set
3
24
3
24
JNB
bit,rel
jmp if bit not set
3
24
1
12
JBC
bit, rel
jmp&clear if set
3
24
CJNE A,#data,rel
CJNE Rn,#data,rel
compare and
jump if not
equal
CJNE @Ri,#data,rel
DJNZ Rn,rel
DJNZ direct, rel
NOP
decrement and
jump if not zero
no operation
move bit to bit
ASSEMBLER DIRECTIVES
EQU
DATA
IDATA
XDATA
BIT
CODE
DS
DBIT
DB
define symbol
define internal memory symbol
define indirect addressing symbol
define external memory symbol
define internal bit memory symbol
define program memory symbol
reserve bytes of data memory
reserve bits of bit memory
store byte values in program memory
BIG MEMORY
BIG MEMORY
FFFFh
(NOP instructions)
FUNCTIONAL BLOCK DIAGRAM
* pin numbers below refer to MQFP package
12
2
JMP
CJNE A,direct,rel
CODE MEMORY SPACE
FFFFh
F800h
F7FFh
DW
ORG
END
CSEG
XSEG
DSEG
ISEG
BSEG
store word values in program memory
set segment location counter
end of assembly source file
select program memory space
select external data memory space
select internal data memory space
select indirectly addressed internal
data memory space
select bit addressable memory space
BIG MEMORY
BIG MEMORY
industry standard 8052
32 I/O lines, programmable PLL clock
(98KHz to 12.58MHz from 32KHz crystal)
other on-chip features: calibrated temperature sensor, power supply
monitor, watchdog timer, flexible serial
interface ports, voltage reference, time interval
counter, dual 8/16bit PWM, power-on-reset
by
te
s
O
S
pe C
rio
d
by
te
s
O
S
pe C
rio
d
s
XCHD A,@Ri
microcontroller:
s
PUSH direct
62K bytes Flash/EE code memory
4K bytes Flash/EE data memory
EA=1
EA=0
internal
code space
external
code space
62K bytes
Flash/EE
(64K
addressable)
0000h
0000h
AIN1
9
AIN2
10
AIN3
11
AIN4
12
AIN5
4
(primary ADC)
AIN
MUX
BUF
SD ADC
SD ADC
PSMCON.5
WDS
IE0
RDY0/RDY1
TF0
IE1
TF1
ISPI/I2CI
RI/TI
TF2/EXF2
TIMECON.2
BIG MEMORY
Power Supply Monitor Interrupt
WatchDog Timer Interrupt
External Interrupt 0
End of ADC Conversion Interrupt
Timer0 Overflow Interrupt
External Interrupt 1
Timer1 Overflow Interrupt
SPI/I2C Interrupt
UART Interrupt
Timer2 Interrupt
Time Interval Counter Interrupt
BIG MEMORY
TEMP
sensor
Vector Priority
within
Address Level
Interrupt Name
43h
5Bh
03h
33h
0Bh
13h
1Bh
3Bh
23h
2Bh
53h
BIG MEMORY
1
2
3
4
5
6
7
8
9
10
11
bandgap
reference
BIG MEMORY
8
REFIN-
7
62K x 8
code
3
IEXC2
4
8052
Flash/EE
MCU
core
baudrate timer
asynchronous
serial port
(UART)
POR
256 x 8
user RAM
synchronous
serial interface
(SPI or I2C)
www.analog.com/microconverter
BIG MEMORY
16bit
counter
timers
watchdog
timer
power supply
monitor
downloader
debugger
200µA / 400µA
IEXC1
BUF
2K x 8
user “XRAM”
Flash/EE
VREF
detect
DAC
PWM
4K x 8
data
(256 counts
per oC)
REFIN+
ADC
control
&
calibration
16 bit
INTERRUPT VECTOR ADDRESSES
Interrupt
Bit
DAC
control
(auxillary ADC)
AIN
MUX
ADuC836
ADC
control
&
calibration
16 bit
PGA
time
interval
counter
BIG MEMORY
3
DAC
1
PWM0
2
PWM1
22
T0
23
T1
1
T2
2
T2EX
18
INT0
19
INT1
OSC &
PLL
33
direct,A
EEPROM:
23
32
A,#data
XRL
12bit, 15µs, voltage output, rail-to-rail
<1LSB DNL
XTAL2
XRL
DAC:
XTAL1
24
24
16bit SD with programmable gain,
plus 16bit SD auxiliary ADC
P3.0 (RxD)
P3.1 (TxD)
P3.2 (INT0)
P3.3 (INT1)
P3.4 (T0 / PWMclk)
P3.5 (T1)
P3.6 (WR)
P3.7 (RD)
1
1
ADC:
16
17
18
19
22
23
24
25
MOVC A,@A+DPTR move from
code memory
MOVC A,@A+PC
logical OR
the ADuC836 is:
13
A,source
24
41
P2.1 / A9 / A17
SS
direct,#data
XRL
3
P2.0 / A8 / A16
31
26
27
14
ORL
2,3 12,24
30
29
SCLOCK
SDATA/MOSI
MISO
dest,#data
MOV DPTR,#data16
28
P3.0 / RxD
P2.0 (A8 / A16)
P2.1 (A9 / A17)
P2.2 (A10 / A18)
P2.3 (A11 / A19)
P2.4 (A12 / A20)
P2.5 (A13 / A21)
P2.6 (A14 / A22)
P2.7 (A15 / A23)
MOV
RESET
18
28
29
30
31
36
37
38
39
direct,A
17
16
single-pin
emulator
ORL
15
42
41
40
1,2,3 24
12
12
ALE
PSEN
EA
ORL
2
2
logical AND
17
ORL
a “Data Acquisition System on a Chip”
16
12
12
s
2
1,2
by
te
s
O
S
pe C
rio
d
dest,source
EA
direct,#data
ANL
MOV
43
12
1,2
move source
to destination
40
direct,A
MOV
A,#data
SDATA / MOSI
A,#data
ANL
dest,A
29
ANL
Data Transfer Operations
MOV
27
TxD
12
MISO
1,2
RxD
1
16
A,source
P1.0 (T2 / PWM0)
P1.1 (T2EX / PWM1)
P1.2 (IEXC1 / DAC)
P1.3 (IEXC2 / AIN5)
P1.4 (AIN1)
P1.5 (AIN2)
P1.6 (AIN3)
P1.7 (AIN4 / DAC)
decimal adjust
14
ANL
1
2
3
4
9
10
11
12
A
SS
12
Logical Operations
15
48
15
RESET
1
P1.7 / AIN4 / DAC
13
21
35
47
divide A by B
P1.6 / AIN3
14
DGND
AB
13
MicroConverter®
Quick Reference Guide
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
48
11
12
* INC DPTR increments the 24bit value DPP/DPH/DPL
BIG MEMORY
43
44
45
46
49
50
51
52
1
ADuC836
52pin MQFP
TOP VIEW
(not to scale)
DVDD
multiply A by B
56pin CSP
TOP VIEW
(not to scale)
6
12
by
te
s
O
S
pe C
rio
d
12
MOV
REFIN+
12
1
A,source
REFIN-
1
1,2
decrement
#data16 16bit constant included in instruction
9
20
34
48
DA
increment
12
7
5
DIV
6 6,7,8 AGND
39
38
37
36
35
34
33
32
31
30
29
28
27
AVDD
AB
8bit constant included in instruction
pin 1 identifier
1
2
3
4
5
6
7
8
9
10
11
12
13
AGND
MUL
any of [Rn, direct, @Ri]
#data
AVDD
42
41
40
39
38
37
36
35
34
33
32
31
30
29
pin 1 identifier
ADuC836
PRINTED IN U.S.A.
source
dest
4,5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SP
A
DEC
5
12
BIG MEMORY
ADuC836
C
DEC
12
subtract from A 1,2
with borrow
2
BIG MEMORY
14
15
16
17
18
19
20
21
22
23
24
25
26
DPTR *
2
any of [Rn, direct, @Ri]
FP
INC
P1.3 / IEXC2 / AIN5
source
Q
source
P1.2 / IEXC1 / DAC
3
M
INC
2
4
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A
3
indirect addressing using R0 or R1
FP
INC
8bit internal address (00h-FFh)
@Ri
Q
SUBB A,#data
direct
12
SP
SUBB A,source
12
M
ADDC A,#data
add with carry
2
1,2
s
ADDC A,source
BIG MEMORY
G03106-2.5-0802 (0)
1
ADD
add source to A
BIG MEMORY
56
55
54
53
52
51
50
49
48
47
46
45
44
43
Arithmetic Operations
Legend
BIG MEMORY
PIN FUNCTIONS
by
te
s
O
S
pe C
rio
d
s
M
Q
FP
INSTRUCTION SET
BIG MEMORY
52
51
50
49
48
47
46
45
44
43
42
41
40
BIG MEMORY
C
BIG MEMORY
SP
BIG MEMORY
C
BIG MEMORY
REV. 0
BIG MEMORY
BIG MEMORY
BIG MEMORY
BIG MEMORY
DATA MEMORY:
BIG MEMORY
BIG MEMORY
BIG MEMORY
BIG MEMORY
BIG MEMORY
BIG MEMORY
RAM, SFRs, user Flash/EE (all read/write)
00h
PCON
(reserved)
80h
P0
FFh 81h
SP
07h 82h
DPL
00h 83h
DPH
00h 84h
DPP
00h
(reserved)
87h
(reserved)
(reserved)
88h
TCON
00h 89h
TMOD
00h 8Ah
TL0
00h 8Bh
TL1
00h 8Ch
TH0
00h 8Dh
TH1
00h
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
FFh
P1
90h
00h
(reserved)
00h
00h A7h
T3CON
00h 9Eh
AEh
00h A6h
T3FD
9Dh
00h A5h
(not used)
55h
00h A4h
I2CADD
00h 9Bh
00h A3h
I2CDAT
00h 9Ah
00h A2h
SBUF
00h 99h
FFh A1h
SCON
A0h
98h
00h
DPCON
MIN
SEC
HTHSEC
00h AFh
INTVAL
HOUR
A0h
TIMECON
00h A9h
A8h
P2
00h
CFG836
PWMCON
(reserved)
B7h
00h
(reserved)
00h B4h
(reserved)
00h B3h
(reserved)
00h B2h
IEIP2
00h
FFh B1h
IE
D7h
00h BFh
00h
03h
DEh
DFh
00h
F7h
SPH
B0h
04h
SPICON
F8h
SPR1
F9h
0
SPR0
F8h
0
SPICON
F8h
00h
BIG MEMORY
BIG MEMORY
BIG MEMORY
BIG MEMORY
BIG MEMORY
BIG MEMORY
DPCON
primary ADC ready flag
auxiliary ADC ready flag
calibration flag
no external reference flag
primary ADC error flag
auxiliary ADC error flag
ADCMODE ADC Mode Register
ADMODE.5
ADMODE.4
ADMODE.2
ADMODE.1
ADMODE.0
primary ADC enable bit
auxiliary ADC enable bit
mode bits
[powerdown, idle, sngl-conv, cont-conv,
zero-selfcal, fs-selfcal, zero-syscal, fs-syscal]
ADC0CON Primary ADC Control Register
AD0CON.7
AD0CON.6
AD0CON.5
AD0CON.4
AD0CON.3
AD0CON.2
AD0CON.1
AD0CON.0
(this bit must contain zero)
external reference select bit (0=internal ref)
channel selection bits:
[AIN1-AIN2,AIN3-AIN4,AIN2-AIN2,AIN3-AIN2]
unipolar select bit (0=bipolar)
range select bits:
[±20mV, ±40mV, ±80mV, ±160mV, ±320mV,
±640mV, ±1.28V, ±2.56V]
ADC1CON Auxiliary ADC Control Register
AD1CON.6
AD1CON.5
AD1CON.4
AD1CON.3
external reference select bit (0=internal ref)
channel selection bits:
[AIN3, AIN4, TEMP, AIN5]
unipolar select bit (0 = bipolar)
SF Sync Filter Register: fADC = 4,096Hz / (3·SF)
GN0H,GN0M
ADC0 gain coefficient
GN1H,GN1L
ADC1 gain coefficient
enable
enable
enable
enable
enable
enable
enable
enable
ADC0H,ADC0M
ADC0 data
ADC1H,ADC1L
ADC1 data
ICON
Current Source Control Register
ICON.6
ICON.5
ICON.4
ICON.3
ICON.2
ICON.1
ICON.0
burnout current enable bit
ADC1 current correction bit (0=correction off)
ADC0 current correction bit (0=correction off)
I2 pin select bit [0=pin4 / 1=pin3]
I1 pin select bit [0=pin3 / 1=pin4]
I2 enable bit (0=disable)
I1 enable bit (0=disable)
DACCON
DACCON.4
DACCON.3
DACCON.2
DACCON.1
DACCON.0
DAC Control register
DAC pin select bit [0=pin3 / 1=pin12]
ModeSelect (0=12bit, 1=8bit)
RangeSelect (0=2.5V, 1=AVDD)
Clear DAC (0=0V, 1=normal operation)
PowerDown DAC (0=off, 1=on)
DACH,DACL
PLLCON
PLLCON.7
PLLCON.6
PLLCON.5
PLLCON.4
PLLCON.3
PLLCON.2
PLLCON.1
PLLCON.0
DAC data registers
PLL Control Register
oscillator powerdown control bit (0=XTAL on)
PLL lock indicator flag (0=out of lock)
(this bit must contain zero)
EA detect status bit (reflects state of EA pin)
“fast interrupt” control bit (0=normal)
3-bit clock divider value, “CD” (default=3):
fCORE = 12,582,912Hz / 2CD
TIMECON Time Interval Counter Control Register
TIMECON.6
TIMECON.5
TIMECON.4
TIMECON.3
TIMECON.2
TIMECON.1
TIMECON.0
(this bit must contain 1)
interval timebase select bits
[128th sec, seconds, minutes, hours]
single time interval control bit (0=reload&restart)
time interval interrupt bit, “TII”
time interval enable bit (0=disable&clear)
time clock enable bit (0=disable)
1
TIC Elapsed 128th Second Register
80h
TIC Interval Register
1
INTVAL
TIC Elapsed Seconds Register
TIC Elapsed Minutes Register
TIC Elapsed Hours Register
Data Flash/EE comand register
READ page
PROGRAM page
VERIFY page
ERASE page
ERASE ALL
82h PROGRAM byte
0Fh EXIT ULOAD mode
F0h ENTER ULOAD mode
(all others reserved)
81h
01h
02h
04h
05h
06h
82h
1
83h
1
SPICON SPI Control register
SPI inturrupt (set at end of SPI transfer)
write collision error flag
SPI enable (0=I2C enable, 1=SPI enable)
master mode select (0=slave)
clock polarity select (0=SCLK idles low)
clock phase select (0=leading edge latch)
SPI bitrate select bits
bitrate = FCORE / [2, 4, 8, 16]
SPI Data register
1
85h
1
84h
I2CCON I2C Control register
MDO
MDE
MCO
MDI
I2CM
I2CRS
I2CTX
I2CI
master mode SDATA output bit
master mode SDATA output enable (0=disable)
master mode SCLK output bit
master mode SDATA input bit
master mode select bit (0=slave mode)
serial port reset
transmission direction status (0=RX,1=TX)
serial interface interrupt
I2CADD I2C Address register
I2CDAT
I2C Data register
86h
PWMCON PWM Control register
1
Stack Pointer
Interrupt Enable register #1
SPIDAT
87h
SP
EA
EADC
ET2
ES
ET1
EX1
ET0
EX0
1
0
Power Supply Monitor control register
DVDD compare bit (0=fault)
AVDD compare bit (0=fault)
PSM interrupt bit
DVDD trip point select bits
[4.63V, 3.08V, 2.93V, 2.63V]
AVDD trip point select bits
[4.63V, 3.08V, 2.93V, 2.63V]
PSM powerdown control (1=on / 0=off)
IE
88h
IT0
PSMCON
PSMCON.7
PSMCON.6
PSMCON.5
PSMCON.4
PSMCON.3
PSMCON.2
PSMCON.1
PSMCON.0
ADC1 offset coefficient
0
IE0
89h
0
IT1
8Ah
Watchdog Timer control register
watchdog timeout selection bits
0000-0111 = timeout=[15.6, 31.2, 62.5, 125, 500
1000 = immediate reset
1000, 2000] ms
all others codes = reserved
watchdog interrupt response enable
watchdog status flag
watchdog enable
watchdog write enable
OF1H,OF1L
Data Flash/EE data registers
0
IE1
8Bh
0
TR0
8Ch
0
TF0
8Dh
0
TR1
8Eh
0
TF1
WDCON
SPH
ISPI
WCOL
SPE
SPIM
CPOL
CPHA
SPR1
SPR0
PWMCON.6 PWM mode bits [0=disabled, 1=single/var.res.,
PWMCON.5
2=twin/8bit, 3=twin/16bit, 4=dual/16bitNRZ,
PWMCON.4
5=dual/8bit, 6=dual/16bitRZ, 7=(reserved)]
PWMCON.3 PWM clock divide bits
PWMCON.2
PWM counter = clock / [1,4,16,64]
PWMCON.1 PWM clock source bits [1=FXTAL/15, 2=FXTAL,
PWMCON.0
3=external input, 4=FVCO(12.58MHz)]
PWM0H,PWM0L PWM0 data registers
Stack Pointer High byte
inturrupts (0=all inturrupts disabled)
RDY0/RDY1 (ADC interrupt)
TF2/EXF2 (Timer2 overflow interrupt)
RI/TI (serial port interrupt)
TF1 (Timer1 overflow interrupt)
IE1 (external interrupt 1)
TF0 (Timer0 overflow interrupt)
IE0 (external interrupt 0)
IEIP2 Interrupt Enable/Priority register #2
IEIP2.6
IEIP2.5
IEIP2.4
IEIP2.3
IEIP2.2
IEIP2.1
IEIP2.0
pirority of TII interrupt (timer interval)
priority of PSMI interrupt (power supply monitor)
priority of ISPI/I2CI interrupt (serial interface)
(this bit must contain zero)
enable TII interrupt (timer interval)
enable PSMI interrupt (power supply monitor)
enable ISPI/I2CI interrupt (serial interface)
IP
Interrupt Priority register
PADC
PT2
PS
PT1
PX1
PT0
PX0
priority
priority
priority
priority
priority
priority
priority
TMOD
of
of
of
of
of
of
of
RDY0/RDY1 (ADC interrupt)
TF2/EXF2 (Timer2 overflow interrupt)
RI/TI (serial port interrupt)
TF1 (Timer1 overflow interrupt)
IE1 (external interrupt 1)
TF0 (Timer0 overflow interrupt)
IE0 (external interrupt 0)
Timer Mode register
TMOD.3/.7
gate control bit (0=ignore INTx)
TMOD.2/.6
counter/timer select bit (0=timer)
TMOD.1/.5
timer mode selecton bits
TMOD.0/.4
[13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]
(upper nibble = Timer1, lower nibble = Timer0)
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer Control register
Timer1 overflow flag
Timer1 run control (0=off, 1=run)
Timer0 overflow flag
Timer0 run control (0=off, 1=run)
external INT1 flag
IE1 type (0=level trig, 1=edge trig)
external INT0 flag
IE0 type (0=level trig, 1=edge trig)
TH0,TL0
Timer0 registers
TH1,TL1
Timer1 registers
T2CON
Timer2 Control register
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CNT2
CAP2
overflow flag
external flag
receive clock enable (0=Timer1 used for RxD clk)
transmit clock enable (0=Timer1 used for TxD clk)
external enable (0=ignore T2EX, 1=cap/rld on T2EX)
run control (0=stop, 1=run)
timer/counter select (0=timer, 1=counter)
capture/reload select (0=reload, 1=capture)
TH2,TL2
Timer2 register
RCAP2H,RCAP2L Timer2 Reload/Capture
P0
Port0 register (also A0-A7 & D0-D7)
P1
Port1 register
P1.2-1.7 analog/digital pins (1=analog function, 0=digital input)
T2EX
timer/counter 2 capture/reload trigger (or digital I/O)
T2
timer/counter 2 external input (or digital I/O)
P2
Port2 register (also A8-A15 & A16-A23)
P3
Port3 register
RD
WR
T1
T0
INT1
INT0
TxD
RxD
external data memory read strobe
external data memory write strobe
timer/counter 1 external input
timer/counter 0 external input
external interrupt 1
external interrupt 0
serial port transmit data line
serial port receive data line
SCON
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Serial communications Control register
UART mode control bits baud rate:
00 - 8bit shift register - FCORE/12
01 - 8bit UART
- variable
10 - 9bit UART
- FCORE/64(x2)
11 - 9bit UART
- variable
in modes 2&3, enables multiprocessor communication
receive enable control bit
in modes 2&3, 9th bit transmitted
in modes 2&3, 9th bit received
transmit interrupt flag
receive interrupt flag
SBUF
PCON
PCON.7
PCON.6
PCON.5
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
Serial port Buffer register
Power Control register
double baud rate control
enable serial interrupt (ISI) from power-down mode
enable interrupt 0 (INT0) from power-down mode
ALE disable (0=normal, 1=forces ALE high)
general purpose flag
general purpose flag
power-down control bit (0=normal)
idle-mode control (0=normal)
PWM1H,PWM1L PWM1 data registers
PSW
Program Status Word
T3CON
CY
AC
F0
RS1
RS0
OV
F1
P
carry flag
auxiliary carry flag
general purpose flag 0
register bank select control bits
active register bank = [0,1,2,3]
overflow flag
general purpose flag 1
parity of ACC
T3CON.7
T3CON.2
T3CON.1
T3CON.0
T3FD
Timer 3 Control register
Timer 3 baud rate enable (0=disable)
binary divide factor (DIV)
DIV = log[FCORE/(32·baudrate)] / log2
(rounded down)
Timer 3 Fractional Divider register
T3FD = (2·FCORE) / (baudrate·2DIV) - 64
CFG836
CFG836.7
CFG836.0
all others
BIG MEMORY
(3X hex = ADuC836)
Data Pointer Control register
data pointer auto-toggle enable (0=disable)
shadow data pointer mode control bits
[1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
main data pointer mode control bits
[1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
(not implemented to allow INC DPCON toggling)
data pointer select [0=main, 1=shadow]
ADC0 offset coefficient
EDATA1,EDATA2,EDATA3,EDATA4
mnemonic
reset value
address
Chip ID Register
DPCON.6
DPCON.5
DPCON.4
DPCON.3
DPCON.2
DPCON.1
DPCON.0
PRE3
PRE2
PRE1
PRE0
WDIR
WDS
WDE
WDWR
BIG MEMORY
OF0H,OF0M
EADRH,EADRL Data Flash/EE address registers
* calibration coefficients are preconfigured at power-up to factory calibrated values
BIG MEMORY
CHIPID
RDY0
RDY1
CAL
NOXREF
ERR0
ERR1
ECON
these bits are contained in this byte
mnemonic
address
reset value
BIG MEMORY BIG MEMORY
SFR DESCRIPTIONS
ADCSTAT ADC Status Register
HTHSEC
SEC
MIN
HOUR
8Fh
1
T2
90h
1
T2EX
91h
92h
97h
1
96h
1
95h
1
94h
1
93h
1
1
98h
0
99h
0
RB8
9Ah
0
TB8
9Bh
0
REN
9Ch
0
SM2
9Dh
0
SM1
9Eh
0
SM0
9Fh
A1h
1
A2h
1
A3h
1
A4h
1
A5h
1
A6h
1
A7h
TI
A0h
1
RI
0
1
0
EX0
A8h
0
ET0
A9h
0
EX1
AAh
0
ET1
ABh
0
ES
ACh
0
ET2
ADh
0
EADC
AEh
0
EA
AFh
1
RXD
B0h
1
TXD
B1h
1
INT0
B2h
1
INT1
B3h
1
T0
B4h
1
T1
B5h
1
WR
B6h
1
RD
0
PT0
B9h
0
PX1
BAh
0
PT1
BBh
0
PS
BCh
0
PT2
BDh
0
PADC
BEh
0
BFh
B7h
B8h
PX0
0
0
WDWR
C0h
WDS
C2h
0
WDIR
C3h
1
PRE0
C4h
0
PRE1
C5h
PRE2
C6h
0
PRE3
C7h
TF2
0
CEh
EXF2
0
0
CDh
RCLK
0
CCh
TCLK
0
CBh
EXEN2
0
CAh
TR2
0
0
C1h
WDE
0
0
CAP2
C8h
0
CNT2
C9h
D0h
0
D1h
0
D2h
0
D3h
0
D4h
0
D5h
0
D6h
0
D7h
CFh
0
0
P
D8h
0
F1
D9h
0
DAh
0
OV
RS0
DBh
0
DCh
0
RS1
F0
DDh
0
DEh
0
AC
CY
DFh
SPR1
F9h
CPHA
FDh
0
WCOL
FEh
0
Register Bank 0
ISPI
Register Bank 1
FFh
0
0
SPR0
Register Bank 2
SFR details
E0h
Register Bank 3
lower RAM
details
0
R0
E1h
00h
0
R1
0
ERR1
R2
01h
E2h
02h
1
0
2
E3h
R3
0
03h
000h
E4h
3
00h
NOXREF ERR0
R4
0
04h
CAL
4
E5h
R5
0
R6
05h
(16M bytes
addressable)
RDY1
06h
5
2K bytes
E6h
6
128 bytes
lower RAM
(direct or
indirect
addressing)
0
R7
RDY0
R0
07h
E7h
08h
7
0
8
external
XRAM
E8h
R1
CFG836.0=0
internal
XRAM
0
R2
09h
CFG836.0=1
E9h
0Ah
9
128 bytes
SFRs
upper RAM
(direct
(indirect
addressing
addressing
only)
only)
0
10
FFh
EAh
R3
0
0Bh
EBh
R4
11
0
R5
0Ch
ECh
0Dh
12
0
13
EDh
R6
7FFh
0
0Eh
( page 0 )
EEh
14
000h
0
R7
EFh
R0
0Fh
0
10h
15
I2CI
16
F0h
R1
0
R2
11h
I2CTX
12h
17
F1h
18
0
R3
I2CRS
13h
F2h
19
0
R4
I2CM
14h
F3h
20
4K bytes
(1K pages)
data
Flash/EE
(accessible
through
SFRs)
0
R5
MDI
R6
15h
F4h
16h
21
0
22
MCO
R7
F5h
17h
FFFFFFh
( page 1023 )
0
23
3FFh
MDE
R0
F6h
18h
0
24
MDO
R1
F7h
R2
19h
MAP KEY
1Ah
25
(reserved)
26
F8h
R3
0
1Bh
1
27
DATA MEMORY SPACE
(read/write area)
FAh
R4
0
1Ch
CPOL
28
FBh
R5
0
R6
1Dh
SPIM
1Eh
29
FCh
30
R7
0
1Fh
SPE
31
(reserved)
00h
00h BEh
01h
(reserved)
02h
00h BDh
03h
PWM1H
04h
BCh
05h
PWM1L
06h
PWM0H
07h
00h
20h
PWM0L
08h
32
00h B9h
10h
09h
P3
11g
0Ah
B8h
12h
0Bh
EDATA4
13h
0Ch
EDATA3
14h
0Dh
EDATA2
15h
0Eh
EDATA1
16h
0Fh
(reserved)
17h
21h
(reserved)
22h
33
ECON
34
IP
18h
EADRH
19h
00h C6h
1Ah
EADRL
1Bh
C6h
1Ch
2Xh
1Dh
C2h
1Eh
10h
1Fh
C0h
23h
00h
35
(reserved)
20h
00h CDh
28h
21h
(reserved)
29h
22g
00h CCh
2Ah
23h
(reserved)
2Bh
24h
00h CBh
2Ch
25h
CHIPID
2Dh
26h
CAh
2Eh
27h
(reserved)
2Fh
24h
00h
25h
36
WDCON
37
C8h
30h
(reserved)
31h
(reserved)
32h
00h
33h
TH2
34h
45h D5h
35h
TL2
36h
00h D4h
37h
RCAP2H
26h
07h D3h
38
RCAP2L
38h
00h D2h
39h
(reserved)
3Ah
00h D1h
3Bh
T2CON
3Ch
D0h
3Dh
PLLCON
3Eh
(reserved)
3Fh
(reserved)
27h
00h
39
ICON
40h
00h DDh
41h
SF
42h
00h DCh
43h
00h DBh
44h
DAh
45h
(reserved)
46h
ADCMODE ADC0CON ADC1CON
47h
00h
28h
PSW
40
D8h
48h
(reserved)
49h
PSMCON
4Ah
(reserved)
4Bh
80h
4Ch
ADC1H
4Dh
00h E5h
4Eh
ADC1L
4Fh
Bit Addressable
Area
80h E4h
29h
ADC0H
41
00h E3h
50h
ADC0M
51h
E2h
52h
00h
53h
ADCSTAT
54h
E0h
55h
~59h
56h
OF1H
57h
~9Ah EDh
2Ah
OF1L
42
~53h ECh
58h
OF0H
59h
~55h EBh
5Ah
OF0M
5Bh
EAh
5Ch
(reserved)
5Dh
00h
5Eh
ACC
5Fh
E8h
2Bh
(reserved)
43
(reserved)
60h
GN1H*
68h
61h
GN1L*
69h
62h
GN0H*
6Ah
63h
GN0M*
6Bh
64h
(reserved)
6Ch
65h
I2CCON
6Dh
66h
SPIDAT
6Eh
67h
(reserved)
6Fh
2Ch
(reserved)
2Dh
44
(reserved)
45
(not used)
70h
(reserved)
78h
71h
(reserved)
79h
72h
00h
7Ah
73h
B
7Bh
74h
F0h
7Ch
75h
(reserved)
7Dh
76h
(reserved)
7Eh
77h
00h
7Fh
2Eh
DACCON
2Fh
46
(bit addresses)
00h FDh
MSB
address
47
General Purpose
Area
DACH
30h
00h FCh
...
48
DACL
...
FBh
7Fh
LSB
address
127
(reserved)
LOWER RAM
HEX
address
decimal
address
SFR MAP & RESET VALUES
BIG MEMORY
ADuC836 Configuration register
extended stack pointer enable (0=disable)
internal XRAM enable (0=external XRAM only)
(reserved)
BIG MEMORY
BIG MEMORY
DPP
Data Pointer Page
DPH,DPL (DPTR)
Data Pointer
ACC
Accumulator
B
auxiliary math register
BIG MEMORY
BIG MEMORY