PIN FUNCTIONS
8bit internal address (00h-FFh)
3
2
P1.2 / IEXC1 / DAC
@Ri
indirect addressing using R0 or R1
4
3
source
any of [Rn, direct, @Ri]
5
4,5
dest
any of [Rn, direct, @Ri]
6 6,7,8 AGND
#data
8bit constant included in instruction
7
9
REFIN-
12
#data16 16bit constant included in instruction
1
12
bit
8bit direct address of bit
8
10
REFIN+
1,2
12
rel
signed 8bit offset
9
11
P1.4 / AIN1
DPTR *
1
24
addr11
11bit address in current 2K page
10
12
P1.5 / AIN2
A
1
12
addr16
16bit address
11
13
P1.6 / AIN3
DEC
source
1,2
12
12
14
P1.7 / AIN4 / DAC
MUL
AB
multiply A by B
1
48
13
15
SS
DIV
AB
divide A by B
1
48
DA
A
decimal adjust
1
12
12
14
16
MISO
27
29
MOSI / D1
40
43
EA
ANL
A,#data
2
12
15
17
RESET
28
30
P2.0 / A8 / A16
41
44
PSEN
direct,A
2
12
16
18
P3.0 / RxD
29
31
P2.1 / A9 / A17
42
45
ALE
direct,#data
3
24
17
19
P3.1 / TxD
30
32
P2.2 / A10 / A18
43
46
P0.0 / AD0
A,source
1,2
12
18
20
P3.2 / INT0
31
33
P2.3 / A11 / A19
44
47
P0.1 / AD1
A,#data
2
12
19
21
P3.3 / INT1
32
34
XTAL1 (in)
45
48
P0.2 / AD2
1,2,3 24
ORL
direct,A
2
12
20
22
DVDD
33
35
XTAL2 (out)
46
49
P0.3 / AD3
3
24
21
23
DGND
34
36
DVDD
47
50
DGND
1,2
12
22
24
P3.4 / T0
35 37,38 DGND
48
51
DVDD
25
P3.5 / T1
36
39
P2.4 / A12 / A20
49
52
P0.4 / AD4
12
2
12
24
26
P3.6 / WR
37
40
P2.5 / A13 / A21
50
53
P0.5 / AD5
3
24
25
27
P3.7 / RD
38
41
P2.6 / A14 / A22
51
54
P0.6 / AD6
1
12
26
28
SCLOCK / D0
39
42
P2.7 / A15 / A23
52
55
P0.7 / AD7
1
12
XRL
direct,#data
1
24
CLR
A
clear A to zero
1
24
CPL
A
complement A
1
24
RL
A
rotate A left
1
12
MOVX @Ri,A
move to/from
data memory
MOVX @DPTR,A
push onto stack
2
24
RLC
A
...through C
1
12
direct
pop from stack
2
24
RR
A
rotate A right
1
12
XCH
A,source
exchange bytes 1,2
12
RRC
A
...through C
1
12
exchg low digits
12
SWAP A
swap nibbles
1
12
1
by
te
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s
XCHD A,@Ri
Program Branching
ACALL addr11
LCALL addr16
call subroutine
2
24
Boolean Variable Manipulation
CLR
C
bit
3
24
CLR
RET
return from sub.
1
24
SETB C
RETI
return from int.
1
24
SETB bit
AJMP addr11
LJMP addr16
SJMP rel
JMP
jump
@A+DPTR
2
24
CPL
C
3
24
CPL
bit
2
24
ANL
C,bit
1
24
ANL
C,/bit
clear bit to zero
set bit to one
1
2
12
12
2
12
1
12
2
12
AND bit with C
2
24
...NOTbit with C
2
24
complement bit
JZ
rel
jump if A = 0
2
24
ORL
C,bit
OR bit with C
2
24
JNZ
rel
jump if A not 0
2
24
ORL
C,/bit
...NOTbit with C
2
24
3
24
MOV
C,bit
2
12
3
24
MOV
bit,C
2
24
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
compare and
jump if not
equal
CJNE @Ri,#data,rel
DJNZ Rn,rel
DJNZ direct, rel
NOP
decrement and
jump if not zero
no operation
move bit to bit
3
24
JC
rel
jump if C set
2
24
3
24
JNC
rel
jmp if C not set
2
24
2
24
JB
bit,rel
jump if bit set
3
24
3
24
JNB
bit,rel
jmp if bit not set
3
24
1
12
JBC
bit, rel
jmp&clear if set
3
24
ASSEMBLER DIRECTIVES
EQU
DATA
IDATA
XDATA
BIT
CODE
DS
DBIT
DB
define symbol
define internal memory symbol
define indirect addressing symbol
define external memory symbol
define internal bit memory symbol
define program memory symbol
reserve bytes of data memory
reserve bits of bit memory
store byte values in program memory
DW
ORG
END
CSEG
XSEG
DSEG
ISEG
BSEG
store word values in program memory
set segment location counter
end of assembly source file
select program memory space
select external data memory space
select internal data memory space
select indirectly addressed internal
data memory space
select bit addressable memory space
calibrated temperature sensor, power supply
monitor, watchdog timer, flexible serial
interface ports, voltage reference, time interval
counter
PROGRAM MEMORY SPACE (read only)
FFFFh
FUNCTIONAL BLOCK DIAGRAM
external
program
memory
12
1
industry standard 8052
32 I/O lines, programmable PLL clock
(98KHz to 12MHz from 32KHz crystal)
other on-chip features:
by
te
s
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ds
PUSH direct
POP
microcontroller:
64K bytes
addressable
2000h
1FFFh
EA=1
internal
8K bytes
Flash/EE
0000h
AIN1
9
AIN2
10
(primary ADC)
AIN
MUX
BUF
EA=0
external
AIN3
11
AIN4
12
AIN5
4
(auxillary ADC)
TEMP
sensor
Σ∆ ADC
Interrupt
Bit
PSMCON.5
WDS
IE0
RDY0/RDY1
TF0
IE1
TF1
ISPI
RI/TI
TF2/EXF2
TIMECON.2
Interrupt Name
Power Supply Monitor Interrupt
WatchDog Timer Interrupt
External Interrupt 0
End of ADC Conversion Interrupt
Timer0 Overflow Interrupt
External Interrupt 1
Timer1 Overflow Interrupt
SPI Interrupt
UART Interrupt
Timer2 Interrupt
Time Interval Counter Interrupt
Vector
Address
43h
5Bh
03h
33h
0Bh
13h
1Bh
3Bh
23h
2Bh
53h
1
2
3
4
5
6
7
8
9
10
11
bandgap
reference
(256 counts
per oC)
REFIN+
8
REFIN-
7
3
IEXC2
4
3
DAC
22
T0
23
T1
1
T2
2
T2EX
time
interval
counter
18
INT0
19
INT1
OSC &
PLL
26
D0
27
D1
BUF
256 x 8
user RAM
8052
MCU
core
Flash/EE
watchdog
timer
power supply
monitor
downloader
debugger
200µA / 400µA
IEXC1
640 x 8
data
DAC
Flash/EE
8K x 8
program
VREF
detect
DAC
control
ADC
control
&
calibration
16 bit
AIN
MUX
INTERRUPT VECTOR ADDRESSES
Priority
within
Level
ADuC816
ADC
control
&
calibration
16 bit
Σ∆ ADC
PGA
asynchronous
serial port
(UART)
synchronous
serial interface
(SPI)
16bit
counter
timers
33
24
32
1
XTAL2
MOVX A,@Ri
MOVX A,@DPTR
2
XTAL1
direct,A
P3.0 (RxD)
P3.1 (TxD)
P3.2 (INT0)
P3.3 (INT1)
P3.4 (T0)
P3.5 (T1)
P3.6 (WR)
P3.7 (RD)
A,#data
XRL
16
17
18
19
22
23
24
25
XRL
24
13
24
1
SS
1
8K bytes Flash/EE program memory
640 bytes Flash/EE data memory
26
27
14
MOVC A,@A+DPTR move from
code memory
MOVC A,@A+PC
logical XOR
EEPROM:
23
SCLOCK
MOSI
MISO
direct,#data
A,source
P2.0 (A8 / A16)
P2.1 (A9 / A17)
P2.2 (A10 / A18)
P2.3 (A11 / A19)
P2.4 (A12 / A20)
P2.5 (A13 / A21)
P2.6 (A14 / A22)
P2.7 (A15 / A23)
ORL
XRL
28
29
30
31
36
37
38
39
24
12bit, 15µs, voltage output, rail-to-rail
<1LSB DNL
single-pin
emulator
3
DAC:
42
41
40
15
2,3 12,24
MOV DPTR,#data16
logical OR
ALE
PSEN
EA
RESET
dest,#data
ORL
ORL
17
MOV
12
12
16
dest,source
2
1,2
TxD
MOV
move source
to destination
16bit Σ∆ with programmable gain,
plus 16bit Σ∆ auxiliary ADC
RxD
A,#data
dest,A
ADC:
P1.0 (T2)
P1.1 (T2EX)
P1.2 (IEXC1 / DAC)
P1.3 (IEXC2 / AIN5)
P1.4 (AIN1)
P1.5 (AIN2)
P1.6 (AIN3)
P1.7 (AIN4 / DAC)
MOV
the ADuC816 is:
1
2
3
4
9
10
11
12
ANL
21
35
47
1,2
DGND
by
te
s
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pe C
rio
d
s
1,2
logical AND
MicroConverter®
Quick Reference Guide
a “Data Acquisition System on a Chip”
A,source
MOV
MOV
ADuC816
52pin PQFP
TOP VIEW
(not to scale)
ANL
ANL
12
39
38
37
36
35
34
33
32
31
30
29
28
27
Logical Operations
Data Transfer Operations
A,source
56pin CSP
TOP VIEW
(not to scale)
pin 1 identifier
1
2
3
4
5
6
7
8
9
10
11
12
13
by
te
s
O
S
pe C
rio
ds
* INC DPTR increments the 24bit value DPP/DPH/DPL
42
41
40
39
38
37
36
35
34
33
32
31
30
29
pin 1 identifier
ADuC816
PQ
FP
INC
DEC
decrement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DVDD
increment
12
12
P1.3 / IEXC2 / AIN5
AVDD
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
direct
43
44
45
46
49
50
51
52
source
12
12
6
INC
2
1,2
subtract from A 1,2
with borrow
2
ADuC816
20
34
48
A
P1.1 / T2EX
5
SUBB A,#data
INC
1
AVDD
ADDC A,#data
SUBB A,source
add with carry
2
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ADDC A,source
add source to A
register addressing using R0-R7
AGND
A,#data
Rn
G02416-2.5-02/02 (A)
ADD
Legend
12
PRINTED IN U.S.A.
1,2
P1.0 / T2
52
51
50
49
48
47
46
45
44
43
42
41
40
A,source
56
14
15
16
17
18
19
20
21
22
23
24
25
26
ADD
1
C
SP
Arithmetic Operations
by
te
s
O
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s
INSTRUCTION SET
www.analog.com/microconverter
REV. A
SFR DESCRIPTIONS
DATA MEMORY:
RAM, SFRs, user Flash/EE (all read/write)
00h
PCON
87h
(reserved)
(reserved)
DPP
00h
00h 84h
DPH
00h 83h
DPL
80h
P0
FFh 81h
SP
07h 82h
(reserved)
(reserved)
00h
00h 8Dh
TH1
TH0
00h 8Ch
TL1
00h 8Bh
TL0
00h 8Ah
TMOD
00h 89h
TCON
(not used)
(not used)
(not used)
FFh
P1
90h
88h
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(reserved)
(reserved)
00h
SBUF
00h 99h
SCON
98h
(not used)
00h
INTVAL
00h A6h
HOUR
00h A5h
MIN
00h A4h
SEC
00h A3h
HTHSEC
00h A2h
TIMECON
FFh A1h
(reserved)
(reserved)
00h
(not used)
(reserved)
EDATA4
03h
(reserved)
D7h
DEh
PLLCON
DFh
(reserved)
PSMCON
00h
(reserved)
SPIDAT
F7h
B
P2
A0h
(reserved)
lower RAM
details
SFR details
ADCMODE ADC Mode Register
ADMODE.5
ADMODE.4
ADMODE.2
ADMODE.1
ADMODE.0
primary ADC enable bit
auxiliary ADC enable bit
mode bits
[powerdown, idle, sngl-conv, cont-conv,
zero-selfcal, fs-selfcal, zero-syscal, fs-syscal]
ADC0CON Primary ADC Control Register
AD0CON.7
AD0CON.6
AD0CON.5
AD0CON.4
AD0CON.3
AD0CON.2
AD0CON.1
AD0CON.0
(this bit must contain zero)
external reference select bit (0=internal ref)
channel selection bits:
[AIN1-AIN2,AIN3-AIN4,AIN2-AIN2,AIN3-AIN2]
unipolar select bit (0=bipolar)
range select bits:
[±20mV, ±40mV, ±80mV, ±160mV, ±320mV,
±640mV, ±1.28V, ±2.56V]
ADC1CON Auxiliary ADC Control Register
AD1CON.6
AD1CON.5
AD1CON.4
AD1CON.3
external reference select bit (0=internal ref)
channel selection bits:
[AIN3, AIN4, TEMP, AIN5]
unipolar select bit (0 = bipolar)
SF Sync Filter Register: fADC = 4,096Hz ÷ (3·SF)
OF0H,OF0M,OF0L ADC0 offset coefficient
ADC1 offset coefficient
GN0H,GN0M,GN0L ADC0 gain coefficient
GN1H,GN1L
ADC1 gain coefficient
ADC0H,ADC0M
ADC0 data
ADC1H,ADC1L
ADC1 data
ICON
Current Source Control Register
ICON.6
ICON.5
ICON.4
ICON.3
ICON.2
ICON.1
ICON.0
burnout current enable bit
ADC1 current correction bit (0=correction off)
ADC0 current correction bit (0=correction off)
I2 pin select bit [0=pin4 / 1=pin3]
I1 pin select bit [0=pin3 / 1=pin4]
I2 enable bit (0=disable)
I1 enable bit (0=disable)
DACCON
DACCON.4
DACCON.3
DACCON.2
DACCON.1
DACCON.0
DAC Control register
DAC pin select bit [0=pin3 / 1=pin12]
ModeSelect (0=12bit, 1=8bit)
RangeSelect (0=2.5V, 1=AVDD)
Clear DAC (0=0V, 1=normal operation)
PowerDown DAC (0=off, 1=on)
DACH,DACL
PLLCON
PLLCON.7
PLLCON.6
PLLCON.5
PLLCON.4
PLLCON.3
PLLCON.2
PLLCON.1
PLLCON.0
DAC data registers
PLL Control Register
oscillator powerdown control bit (0=normal)
PLL lock indicator flag (0=out of lock)
(this bit must contain zero)
EA detect status bit (reflects state of EA pin)
“fast interrupt” control bit (0=normal)
3-bit clock divideer value, “CD” (default=3):
fCORE = 12,582,912Hz ÷ 2CD
SPR1
F9h
SPR0
0
F8h
SPICON
0
F8h
00h
* calibration coefficients are preconfigured at power-up to factory calibrated values
TIC Elapsed 128th Second Register
CHIPID
1
84h
1
1
86h
1
87h
DCON
mnemonic
reset value
address
enable inturrupts (0=all inturrupts disabled)
enable RDY0/RDY1 (ADC interrupt)
enable TF2/EXF2 (Timer2 overflow interrupt)
enable RI/TI (serial port interrupt)
enable TF1 (Timer1 overflow interrupt)
enable IE1 (external interrupt 1)
enable TF0 (Timer0 overflow interrupt)
enable IE0 (external interrupt 0)
IEIP2 Interrupt Enable/Priority register #2
IEIP2.7
IEIP2.6
IEIP2.5
IEIP2.4
IEIP2.3
IEIP2.2
IEIP2.1
IEIP2.0
(not used)
pirority of TII interrupt (timer interval)
priority of PSMI interrupt (power supply monitor)
priority of ISPI interrupt (serial interface)
(this bit must contain zero)
enable TII interrupt (timer interval)
enable PSMI interrupt (power supply monitor)
enable ISPI interrupt (serial interface)
IP
Interrupt Priority register
IP.7
PADC
PT2
PS
PT1
PX1
PT0
PX0
(not used)
priority of RDY0/RDY1 (ADC interrupt)
priority of TF2/EXF2 (Timer2 overflow interrupt)
priority of RI/TI (serial port interrupt)
priority of TF1 (Timer1 overflow interrupt)
priority of IE1 (external INT1)
priority of TF0 (Timer0 overflow interrupt)
priority of IE0 (external INT0)
TMOD
Timer Mode register
TMOD.3/.7
gate control bit (0=ignore INTx)
TMOD.2/.6
counter/timer select bit (0=timer)
TMOD.1/.5
timer mode selecton bits
TMOD.0/.4
[13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]
(upper nibble = Timer1, lower nibble = Timer0)
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer Control register
Timer1 overflow flag
Timer1 run control (0=off, 1=run)
Timer0 overflow flag
Timer0 run control (0=off, 1=run)
external INT1 flag
IE1 type (0=level trig, 1=edge trig)
external INT0 flag
IE0 type (0=level trig, 1=edge trig)
TH0,TL0
Timer0 registers
TH1,TL1
Timer1 registers
T2CON
Timer2 Control register
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CNT2
CAP2
overflow flag
external flag
receive clock enable (0=Timer1 used for RxD clk)
transmit clock enable (0=Timer1 used for TxD clk)
external enable (0=ignore T2EX, 1=cap/rld on T2EX)
run control (0=stop, 1=run)
timer/counter select (0=timer, 1=counter)
capture/reload select (0=reload, 1=capture)
TH2,TL2
Timer2 register
RCAP2H,RCAP2L Timer2 Reload/Capture
P0
Port0 register
P1
Port1 register
P1.2-1.7 analog/digital pins (1=analog function, 0=digital input)
T2EX
timer/counter 2 capture/reload trigger (or digital I/O)
T2
timer/counter 2 external input (or digital I/O)
Port2 register
TIC Elapsed Minutes Register
external data memory read strobe
external data memory write strobe
timer/counter 1 external input
timer/counter 0 external input
external interrupt 1
external interrupt 0
serial port transmit data line
serial port receive data line
TIC Elapsed Hours Register
READ page
PROGRAM page
VERIFY page
ERASE page
ERASE ALL
81h READ byte
82h PROGRAM byte
0Fh EXIT ULOAD mode
F0h ENTER ULOAD mode
(all others reserved)
SCON Serial communications Control register
SM0
SM1
Data Flash/EE address registers
SPI Control register
SPI inturrupt (set at end of SPI transfer)
write collision error flag
SPI enable (0=DCON enable, 1=SPI enable)
master mode select (0=slave)
clock polarity select (0=SCLK idles low)
clock phase select (0=leading edge latch)
SPI bitrate select bits
bitrate = FCORE / [2, 4, 8, 16]
SPI Data register
D0 & D1 Control register
(enabled if SPE=0, see SPICON register above)
D1
D1 output bit
D1EN
D1 output enable (0=disable)
D0
D0 output bit
D0EN
D0 output enable (0=disable)
PRE3
PRE2
PRE1
PRE0
WDIR
WDS
WDE
WDWR
EA
EADC
ET2
ES
ET1
EX1
ET0
EX0
Port3 register
Data Flash/EE data registers
SPIDAT
Interrupt Enable register #1
RD
WR
T1
T0
INT1
INT0
TxD
RxD
EDATA1,EDATA2,EDATA3,EDATA4
ISPI
WCOL
SPE
SPIM
CPOL
CPHA
SPR1
SPR0
Stack Pointer
IE
P3
EADRH,EADRL
SPICON
SP
P2
Data Flash/EE comand register
01h
02h
04h
05h
06h
DVDD compare bit (0=fault)
AVDD compare bit (0=fault)
PSM interrupt bit
DVDD trip point select bits
[4.63V, 3.08V, 2.93V, 2.63V]
AVDD trip point select bits
[4.63V, 3.08V, 2.93V, 2.63V]
PSM powerdown control (1=on / 0=off)
TIC Elapsed Seconds Register
Chip ID Register (1X hex = ADuC816)
ECON
83h
1
82h
1
81h
1
80h
1
HTHSEC
SEC
MIN
HOUR
85h
0
IT0
IE0
IT1
IE1
TR0
TF0
TIC Interval Register
0
TR1
INTVAL
8Eh
24hour select bit (0=255hour)
interval timebase select bits
[128th sec, seconds, minutes, hours]
single time interval control bit (0=reload&restart)
time interval interrupt bit, “TII”
time interval enable bit (0=disable&clear)
time clock enable bit (0=disable)
WDCON
these bits are contained in this byte
mnemonic
address
reset value
TIMECON.6
TIMECON.5
TIMECON.4
TIMECON.3
TIMECON.2
TIMECON.1
TIMECON.0
0
8Fh
TF1
8Dh
0
8Ch
0
8Bh
0
8Ah
0
89h
0
88h
1
T2
1
T2EX
91h
1
92h
1
93h
1
94h
1
1
96h
97h
1
95h
98h
0
TI
99h
0
RB8
9Ah
0
TB8
9Bh
0
REN
9Ch
0
SM2
9Dh
0
SM1
9Eh
0
9Fh
SM0
90h
0
RI
1
A0h
1
A1h
1
A2h
1
A3h
1
A4h
1
ET0
EX1
ET1
ES
ET2
A5h
1
A6h
1
A7h
EX0
0
0
EADC
AEh
0
AFh
EA
ADh
0
ACh
0
ABh
0
AAh
0
A9h
0
A8h
1
B7h
1
B6h
1
B5h
1
B4h
1
B3h
1
B2h
1
B1h
1
B0h
0
B8h
RXD
TXD
B9h
BAh
INT0
INT1
BBh
BCh
T0
T1
BDh
0
BEh
WR
RD
BFh
0
PADC
PT2
0
PS
0
PT1
0
PX1
0
PT0
WDE
0
PX0
WDWR
0
0
WDS
PRE0
PRE1
PRE2
PRE3
C7h
0
C6h
0
C5h
0
C4h
1
C3h
WDIR
C2h
0
C1h
0
C0h
0
CAP2
0
CNT2
C9h
0
TR2
CAh
0
EXEN2
CBh
0
TCLK
CCh
0
RCLK
CDh
0
EXF2
CEh
0
TF2
CFh
D0h
0
D1h
0
D2h
0
D3h
0
D4h
0
D5h
0
D6h
0
D7h
C8h
0
0
D8h
0
F1
D9h
0
OV
DAh
0
RS0
DBh
0
RS1
DCh
0
F0
DDh
0
AC
DEh
0
CY
DFh
0
E0h
E8h
P
0
0
0
F0h
0
0
E1h
0
ERR1
E2h
0
E3h
R0
0
00h
E4h
0
NOXREF ERR0
R1
0
R2
01h
000000h
CAL
02h
1
00h
E5h
2
Register
Bank 0
0
R3
RDY1
03h
E6h
R4
3
0
R5
04h
RDY0
05h
4
E7h
5
E9h
R6
0
06h
EAh
6
128 bytes
lower RAM
(direct or
indirect
addressing)
0
R7
EBh
R0
07h
0
08h
7
ECh
8
0
R1
EDh
09h
0
9
SFRs
(direct
addressing
only)
EEh
R2
0
0Ah
128 bytes
upper RAM
(indirect
addressing
only)
EFh
10
FFh
F1h
R3
0
0Bh
F2h
11
Register
Bank 1
0
R4
D0EN
R5
0Ch
F3h
0Dh
12
0
13
F4h
R6
(16MEG
addressable)
0
0Eh
( page 0 )
D0
14
00h
F5h
R7
0
0Fh
D1EN
15
F6h
R0
0
R1
10h
D1
11h
16
external
data
memory
F7h
17
Register
Bank 2
MAP KEY
R2
04h
12h
SPICON
18
0
R3
SPR0
R4
13h
F8h
14h
19
0
20
640 bytes
(160 pages)
data
Flash/EE
(accessible
through
SFRs)
SPR1
R5
F9h
R6
15h
1
16h
21
CPHA
22
PSMCON.7
PSMCON.6
PSMCON.5
PSMCON.4
PSMCON.3
PSMCON.2
PSMCON.1
PSMCON.0
primary ADC ready flag
auxiliary ADC ready flag
calibration flag
no external reference flag
primary ADC error flag
auxiliary ADC error flag
TIMECON Time Interval Counter Control Register
FAh
R7
PSMCON Power Supply Monitor control register
RDY0
RDY1
CAL
NOXREF
ERR0
ERR1
OF1H,OF1L
FFFFFFh
0
17h
( page 159 )
CPOL
23
9Fh
FBh
R0
0
18h
SPIM
R1
24
FCh
19h
0
R2
25
SPE
R3
1Ah
FDh
1Bh
26
0
27
DATA MEMORY SPACE
(read/write area)
Register
Bank 3
WCOL
R4
FEh
1Ch
0
28
F8h
R5
ISPI
1Dh
FFh
29
(reserved)
R6
(reserved)
1Eh
(reserved)
30
(reserved)
R7
A0h
1Fh
IEIP2
00h
31
00h A9h
08h
01h
A8h
09h
02h
FFh
0Ah
03h
IE
0Bh
04h
B0h
0Ch
05h
00h BFh
0Dh
06h
(reserved)
0Eh
07h
00h BEh
0Fh
20h
(reserved)
21h
32
00h BDh
33
(not used)
10h
BCh
11g
(not used)
12h
(not used)
13h
(not used)
14h
(reserved)
15h
(reserved)
16h
00h
17h
00h B9h
22h
P3
34
B8h
18h
00h
19h
EDATA3
1Ah
EDATA2
1Bh
EDATA1
1Ch
ECON
1Dh
IP
1Eh
EADRL
1Fh
C6h
23h
16h
20h
35
C2h
28h
21h
10h
29h
22g
C0h
2Ah
23h
00h
2Bh
24h
(reserved)
2Ch
25h
00h CDh
2Dh
26h
(reserved)
2Eh
27h
00h CCh
2Fh
24h
(reserved)
25h
36
00h CBh
37
CHIPID
30h
CAh
31h
(reserved)
32h
00h
33h
WDCON
34h
C8h
35h
(reserved)
36h
00h
37h
TH2
26h
45h D5h
38
TL2
38h
00h D4h
39h
RCAP2H
3Ah
07h D3h
3Bh
RCAP2L
3Ch
00h D2h
3Dh
(reserved)
3Eh
00h D1h
3Fh
T2CON
27h
D0h
40h
39
(reserved)
48h
41h
(reserved)
49h
42h
00h
4Ah
43h
ICON
4Bh
44h
00h DDh
4Ch
45h
SF
4Dh
46h
00h DCh
4Eh
47h
Bit Addressable
Area
00h DBh
4Fh
28h
DAh
29h
40
(reserved)
41
ADCMODE ADC0CON ADC1CON
50h
00h
51h
PSW
52h
D8h
53h
(reserved)
54h
80h
55h
ADC1H
56h
00h E5h
57h
ADC1L
2Ah
80h E4h
42
ADC0H
58h
00h E3h
59h
ADC0M
5Ah
E2h
5Bh
00h
5Ch
ADCSTAT
5Dh
E0h
5Eh
~59h
5Fh
OF1H
2Bh
~9Ah EDh
60h
43
OF1L
68h
61h
~53h ECh
69h
62h
OF0H
6Ah
63h
~55h EBh
6Bh
64h
OF0M
6Ch
65h
EAh
6Dh
66h
(reserved)
6Eh
67h
00h
6Fh
2Ch
ACC
2Dh
44
E8h
45
(reserved)
70h
GN1H*
71h
GN1L*
72h
GN0H*
73h
GN0M*
74h
(reserved)
75h
DCON
76h
(reserved)
77h
(reserved)
2Eh
(reserved)
46
(not used)
78h
(reserved)
79h
(reserved)
7Ah
F0h
7Bh
00h
(reserved)
7Ch
(bit addresses)
(reserved)
7Dh
00h
7Eh
DACCON
7Fh
00h FDh
2Fh
DACH
MSB
address
47
General Purpose
Area
00h FCh
30h
DACL
...
48
FBh
7Fh
...
LSB
address
127
(reserved)
LOWER RAM
HEX
address
decimal
address
SFR MAP & RESET VALUES
ADCSTAT ADC Status Register
Watchdog Timer control register
watchdog timeout selection bits
0000-0111 = timeout=[15.6, 31.2, 62.5, 125, 500
1000 = immediate reset
1000, 2000] ms
all others codes = reserved
watchdog interrupt response enable
watchdog status flag
watchdog enable
watchdog write enable
SM2
REN
TB8
RB8
TI
RI
UART mode control bits baud rate:
00 - 8bit shift register - FCORE/12
01 - 8bit UART
- TimerOverflowRate/32(x2)
10 - 9bit UART
- FCORE/64(x2)
11 - 9bit UART
- TimerOverflowRate/32(x2)
in modes 2&3, enables multiprocessor communication
receive enable control bit
in modes 2&3, 9th bit transmitted
in modes 2&3, 9th bit received
transmit interrupt flag
receive interrupt flag
SBUF
Serial port Buffer register
PCON Power Control register
PCON.7
PCON.6
PCON.5
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
double baud rate control
enable serial interrupt (ISI) from power-down mode
enable interrupt 0 (INT0) from power-down mode
ALE disable (0=normal, 1=forces ALE high)
general purpose flag
general purpose flag
power-down control bit (0=normal)
idle-mode control (0=normal)
PSW
Program Status Word
CY
AC
F0
RS1
RS0
OV
F1
P
carry flag
auxiliary carry flag
general purpose flag 0
register bank select control bits
active register bank = [0,1,2,3]
overflow flag
general purpose flag 1
parity of ACC
DPP
Data Pointer Page
DPH,DPL (DPTR)
Data Pointer
ACC
Accumulator
B
auxiliary math register