TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PIN FUNCTIONS
indirect addressing using R0 or R1
source
any of [Rn, direct, @Ri]
dest
any of [Rn, direct, @Ri]
#data
8bit constant included in instruction
12
#data16 16bit constant included in instruction
1
12
bit
8bit direct address of bit
1,2
12
rel
signed 8bit offset
DPTR
1
24
addr11
11bit address in current 2K page
DEC
A
1
12
addr16
16bit address
DEC
source
1,2
12
2
DLOAD
27
XTAL2
ANL
A,#data
2
12
3
P3.0 / RxD
26
XTAL1
direct,A
2
12
4
P3.1 / TxD
25
SCLOCK / D0
direct,#data
3
24
5
P3.2 / INT0
24
P3.7 / MOSI / D1
MOV
1,2
ANL
A,source
MOV
A,#data
MOV
dest,A
MOV
dest,source
MOV
dest,#data
move source
to destination
12
logical AND
2
12
ORL
A,source
1,2
12
6
P3.3 / INT1
23
P3.6 / MISO
1,2
12
ORL
A,#data
2
12
7
P3.4 / T0 / CONVST
22
P3.5 / T1 / SS / EXTCLK
1,2,3 24
ORL
direct,A
2
12
8
P1.0 / T2
21
P1.7 / ADC5 / DAC1
ORL
direct,#data
3
24
9
P1.1 / T2EX
20
P1.6 / ADC4 / DAC0
2,3 12,24
logical OR
MOV DPTR,#data16
3
24
XRL
A,source
1,2
12
10
RESET
19
P1.5 / ADC3
MOVC A,@A+DPTR move from
code memory
MOVC A,@A+PC
1
24
XRL
A,#data
2
12
11
P1.2 / ADC0
18
P1.4 / ADC2
1
24
XRL
direct,A
MOVX A,@Ri
1
24
XRL
direct,#data
1
24
CLR
A
MOVX @Ri,A
move to/from
data memory
clear A to zero
2
12
12
P1.3 / ADC1
17
CREF
3
24
13
AVDD
16
VREF
1
12
14
AGND
15
AGND
1
24
CPL
A
complement A
1
12
1
24
RL
A
rotate A left
1
12
push onto stack
2
24
RLC
A
...through C
1
12
2
MOVX @DPTR,A
PUSH direct
logical XOR
direct
pop from stack
24
RR
A
rotate A right
1
12
A,source
exchange bytes 1,2
12
RRC
A
...through C
1
12
exchg low digits
12
SWAP A
swap nibbles
1
12
1
by
te
s
O
S
pe C
ri o
d
s
XCHD A,@Ri
Program Branching
ACALL addr11
LCALL addr16
call subroutine
Boolean Variable Manipulation
2
24
CLR
C
3
24
CLR
bit
clear bit to zero
1
12
2
12
1
12
2
12
1
12
RET
return from sub.
1
24
SETB C
RETI
return from int.
1
24
SETB bit
2
24
CPL
3
24
CPL
bit
2
12
2
24
ANL
C,bit
AND bit with C
2
24
1
24
ANL
C,/bit
...NOTbit with C
2
24
2
24
ORL
C,bit
OR bit with C
2
24
AJMP addr11
LJMP addr16
SJMP rel
jump
JMP
@A+DPTR
JZ
rel
jump if A = 0
JNZ
rel
jump if A not 0
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
compare and
jump if not
equal
CJNE @Ri,#data,rel
DJNZ Rn,rel
DJNZ direct, rel
NOP
decrement and
jump if not zero
no operation
set bit to one
C
complement bit
2
24
ORL
C,/bit
3
24
MOV
C,bit
3
24
MOV
bit,C
3
24
JC
rel
2
24
JNC
2
24
3
1
...NOTbit with C
2
24
2
12
2
24
jump if C set
2
24
rel
jmp if C not set
2
24
JB
bit,rel
jump if bit set
3
24
24
JNB
bit,rel
jmp if bit not set
3
24
12
JBC
bit, rel
jmp&clear if set
3
24
move bit to bit
TSSOP
define symbol
define internal memory symbol
define indirect addressing symbol
define external memory symbol
define internal bit memory symbol
define program memory symbol
reserve bytes of data memory
reserve bits of bit memory
store byte values in program memory
TSSOP
TSSOP
DW
ORG
END
CSEG
XSEG
DSEG
ISEG
BSEG
TSSOP
TSSOP
dual, 12bit, 15µs, voltage output
<1LSB DNL
8K bytes Flash/EE program memory
640 bytes Flash/EE data memory
microcontroller:
industry standard 8052
16 I/O lines, programmable PLL clock
(131KHz to 16MHz from 32KHz crystal)
temperature monitor, power supply monitor,
watchdog timer, flexible serial interface ports,
FUNCTIONAL BLOCK DIAGRAM
PROGRAM MEMORY SPACE (read only)
1FFFh
internal
8K bytes
Flash/EE
8K bytes
addressable
0000h
(no parallel external memory interface)
hardware
CONVST
7
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
11
12
18
19
20
21
INTERRUPT VECTOR ADDRESSES
ADuC814
AIN
MUX
TEMP
monitor
ADC
control
&
calibration
12bit ADC
T/H
Interrupt
Bit
TSSOP
Interrupt Name
PSMCON.5
PLLCON.6
WDS
IE0
ADCI
TF0
IE1
TF1
ISPI
RI/TI
TF2/EXF2
TIMECON.2
TSSOP
Vector
Address
Power Supply Monitor Interrupt
PLL Lock Interrupt
WatchDog Timer Interrupt
External Interrupt 0
End of ADC Conversion Interrupt
Timer0 Overflow Interrupt
External Interrupt 1
Timer1 Overflow Interrupt
SPI Interrupt
UART Interrupt
Timer2 Interrupt
Time Interval Counter Interrupt
TSSOP
TSSOP
TSSOP
43h
4Bh
5Bh
03h
33h
0Bh
13h
1Bh
3Bh
23h
2Bh
53h
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
VREF
16
CREF
17
TSSOP
20
DAC0
DAC1
BUF
21
DAC1
256 x 8
user RAM
Flash/EE
8K x 8
program
8052
Flash/EE
MCU
core
BUF
asynchronous
serial port
(UART)
watchdog
timer
power supply
monitor
downloader
debugger
POR
synchronous
serial interface
(SPI)
www.analog.com/microconverter
TSSOP
BUF
(-2 mV/oC)
2.5V
bandgap
reference
Priority
within
Level
DAC0
DAC
control
640 bytes
data
store word values in program memory
set segment location counter
end of assembly source file
select program memory space
select external data memory space
select internal data memory space
select indirectly addressed internal
data memory space
select bit addressable memory space
TSSOP
DAC:
other on-chip features:
ASSEMBLER DIRECTIVES
EQU
DATA
IDATA
XDATA
BIT
CODE
DS
DBIT
DB
12bit, 5µs, 6channel, self calibrating,
guaranteed no missing codes, high-speed
data capture mode
Flash/EEPROM:
by
te
s
O
S
pe C
ri o
ds
POP
XCH
ADC:
P1.0 (T2)
P1.1 (T2EX)
P1.2 (ADC0)
P1.3 (ADC1)
P1.4 (ADC2)
P1.5 (ADC3)
P1.6 (ADC4 / DAC0)
P1.7 (ADC5 / DAC1)
MOVX A,@DPTR
the ADuC814 is:
16bit
counter
timers
time
interval
counter
OSC &
PLL
27
by
te
s
O
S
pe C
rio
d
ANL
26
Data Transfer Operations
XTAL2
12
DVDD
12
XTAL1
1
28
1,2
22
decimal adjust
DGND
A,source
SS
A
1
ANL
25
24
23
DA
a “Data Acquisition System on a Chip”
Logical Operations
SCLOCK
MOSI
MISO
48
48
2
1
1
DLOAD
multiply A by B
divide A by B
4
AB
AB
s
MUL
DIV
3
decrement
TxD
INC
increment
RxD
source
10
INC
MicroConverter®
Quick Reference Guide
RESET
A
ADuC814
28pin TSSOP
TOP VIEW
(not to scale)
8
9
11
12
18
19
20
21
INC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
12
12
pin 1 identifier
28
2
subtract from A 1,2
with borrow
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P3.0 (RxD)
P3.1 (TxD)
P3.2 (INT0)
P3.3 (INT1)
P3.4 (T0 / CONVST)
P3.5 (T1 / SS / EXTCLK)
P3.6 (MISO)
P3.7 (MOSI / D1)
8bit internal address (00h-FFh)
@Ri
TSSOP
3
4
5
6
7
22
23
24
direct
by
te
s
O
S
pe C
rio
ds
SUBB A,#data
12
12
DVDD
ADDC A,#data
SUBB A,source
add with carry
2
1,2
DGND
ADDC A,source
add source to A
register addressing using R0-R7
14
15
A,#data
Rn
13
ADD
Legend
12
AVDD
1,2
TSSOP
AGND
AGND
A,source
G02945-1-4/02 (0)
by
te
s
O
S
pe C
rio
d
ADD
PRINTED IN U.S.A.
Arithmetic Operations
TSSOP
ADuC814
s
INSTRUCTION SET
TSSOP
single-pin
emulator
TSSOP
TSSOP
TSSOP
TSSOP
7
T0
22
T1
8
T2
9
T2EX
5
INT0
6
INT1
25
D0
24
D1
REV. 0
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
SFR DESCRIPTIONS
DATA MEMORY:
ADCCON1
RAM, SFRs, user Flash/EE (all read/write)
SFR details
SPR0
0
F8h
SPICON
0
F8h
00h
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
00h
PCON
87h
(reserved)
(reserved)
(reserved)
00h
DPH
00h 83h
DPL
SP
81h
(not used)
0
IT0
88h
0
89h
0
IE0
ADCOFSH
ADCOFSL
ADC Offset
calibration coefficients
DACCON
DAC Control register
DACCON.7
DACCON.6
DACCON.5
DACCON.4
DACCON.3
DACCON.2
DACCON.1
DACCON.0
DAC1 data registers
DAC0H,DAC0L
DAC0 data registers
fCORE = 16,777,216Hz ÷ 2CD
TIMECON Time Interval Counter Control Register
8Ah
Stack Pointer
IE
Interrupt Enable register #1
EA
EADC
ET2
ES
ET1
EX1
ET0
EX0
enable inturrupts (0=all inturrupts disabled)
enable ADCI (ADC interrupt)
enable TF2/EXF2 (Timer2 overflow interrupt)
enable RI/TI (serial port interrupt)
enable TF1 (Timer1 overflow interrupt)
enable IE1 (external interrupt 1)
enable TF0 (Timer0 overflow interrupt)
enable IE0 (external interrupt 0)
IP
Interrupt Priority register
IP.7
PADC
PT2
PS
PT1
PX1
PT0
PX0
(not used)
priority of ADCI (ADC interrupt)
priority of TF2/EXF2 (Timer2 overflow interrupt)
priority of RI/TI (serial port interrupt)
priority of TF1 (Timer1 overflow interrupt)
priority of IE1 (external INT1)
priority of TF0 (Timer0 overflow interrupt)
priority of IE0 (external INT0)
IEIP2.7
IEIP2.6
IEIP2.5
IEIP2.4
IEIP2.3
IEIP2.2
IEIP2.1
IEIP2.0
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
8Ch
8Dh
Timer Control register
Timer1 overflow flag (auto cleared on vector to ISR)
Timer1 run control (0=off, 1=run)
Timer0 overflow flag (auto cleared on vector to ISR)
Timer0 run control (0=off, 1=run)
external INT1 flag (auto cleared on vector to ISR)
IE1 type (0=level trig, 1=edge trig)
external INT0 flag (auto cleared on vector to ISR)
IE0 type (0=level trig, 1=edge trig)
TH0,TL0
Timer0 registers
TH1,TL1
Timer1 registers
T2CON
Timer2 Control register
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CNT2
CAP2
overflow flag
external flag
receive clock enable (0=Timer1 used for RxD clk)
transmit clock enable (0=Timer1 used for TxD clk)
external enable (0=ignore T2EX, 1=cap/rld on T2EX)
run control (0=stop, 1=run)
timer/counter select (0=timer, 1=counter)
capture/reload select (0=reload, 1=capture)
TH2,TL2
Timer2 register
HTHSEC
SEC
MIN
HOUR
TIC Elapsed 128th Second Register
P1
TIC Elapsed Seconds Register
TIC Elapsed Minutes Register
P1.2-1.7 analog/digital pins (1=analog function, 0=digital input)
T2EX
timer/counter 2 capture/reload trigger
T2
timer/counter 2 external input
TIC Elapsed Hours Register
P3
Port3 register
CFG814
ADuC814 Configuration Register
CFG814.0
CFG814.1
SPI enable (0=disabled)
PLL bypas (0=XTAL+PLL, 1=P3.5)
RD
WR
T1
T0
INT1
INT0
TxD
RxD
external data memory read strobe
external data memory write strobe
timer/counter 1 external input
timer/counter 0 external input
external interrupt 1
external interrupt 0
serial port transmit data line
serial port receive data line
ISPI
WCOL
SPE
SPIM
CPOL
CPHA
SPR1
SPR0
Data Flash/EE comand register
READ page
05h ERASE page
PROGRAM page 06h ERASE ALL
VERIFY page
othersreserved
Data Flash/EE address register
SPI Control register
SPI inturrupt (set at end of SPI transfer)
write collision error flag
SPI enable (0=DCON enable, 1=SPI enable)
master mode select (0=slave)
clock polarity select (0=SCLK idles low)
clock phase select (0=leading edge latch)
SPI bitrate select bits
bitrate = Fcore / [2,4,8,16] (slave: SPR0=SS)
SPIDAT
SPI Data register
DCON
D0 & D1 Control register
(enabled if SPE=0, see SPICON register above)
D1
D1 output bit
D1EN
D1 output enable (0=disable)
D0
D0 output bit
D0EN
D0 output enable (0=disable)
PRE3
PRE2
PRE1
PRE0
WDIR
WDS
WDE
WDWR
TSSOP
Timer Mode register
TMOD.3/.7
gate control bit (0=ignore INTx)
TMOD.2/.6
counter/timer select bit (0=timer)
TMOD.1/.5
timer mode selecton bits
TMOD.0/.4
[13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]
(upper nibble = Timer1, lower nibble = Timer0)
RCAP2H,RCAP2L Timer2 Reload/Capture
SPICON
mnemonic
reset value
address
priority of LOCK interrupt (PLL lock)
priority of TII interrupt (time interval)
priority of PSMI interrupt (power supply monitor)
priority of ISPI interrupt (serial interface)
enable LOCK interrupt (PLL lock)
enable TII interrupt (time interval)
enable PSMI (power supply monitor interrupt)
enable ISPI interrupt (serial interface)
TIC Interval Register
0
IE1
8Bh
SP
Port1 register
SCON Serial communications Control register
SM0
SM1
UART mode control bits baud rate:
00 - 8bit shift register - FOSC/12
01 - 8bit UART
- TimerOverflowRate/32(x2)
10 - 9bit UART
- FOSC/64(x2)
11 - 9bit UART
- TimerOverflowRate/32(x2)
in modes 2&3, enables multiprocessor communication
receive enable control bit
in modes 2&3, 9th bit transmitted
in modes 2&3, 9th bit received
transmit interrupt flag
receive interrupt flag
Data Flash/EE data registers
0
TR0
(reserved)
PSM status bit (1=normal / 0=fault)
PSM interrupt bit
trip point select bits
[4.63V, 3.08V, 2.93V, 2.63V]
(reserved)
(reserved)
PSM enable control (0=off, 1=on)
INTVAL
ETIM1,ETIM2 Data Flash/EE timing registers
0
TF0
24hour select bit (0=255hour)
INTVAL timebase select bits
[128th sec, seconds, minutes, hours]
single time interval control bit (0=reload&restart)
time interval interrupt bit, “TII”
time interval enable bit (0=disable&clear)
time clock enable bit (0=disable)
EDATA1,EDATA2,EDATA3,EDATA4
8Eh
TR1
PLL Control register
oscillator powerdown control bit (0=normal)
PLL lock indicator flag (0=out of lock)
(this bit must contain zero)
(this bit must contain zero)
“fast interrupt” control bit (0=normal)
3-bit clock divider value, “CD” (default=3):
TIMECON.6
TIMECON.5
TIMECON.4
TIMECON.3
TIMECON.2
TIMECON.1
TIMECON.0
PSMCON.7
PSMCON.6
PSMCON.5
PSMCON.4
PSMCON.3
PSMCON.2
PSMCON.1
PSMCON.0
TMOD
ModeSelect (0=12bit, 1=8bit)
DAC1 RangeSelect (0=2.5V, 1=VDD)
DAC0 RangeSelect (0=2.5V, 1=VDD)
Clear DAC1 (0=0V, 1=normal operation)
Clear DAC0 (0=0V, 1=normal operation)
SynchronousUpdate (1=asynchronous)
PowerDown DAC1 (0=off, 1=on)
PowerDown DAC0 (0=off, 1=on)
DAC1H,DAC1L
PLLCON.7
PLLCON.6
PLLCON.5
PLLCON.4
PLLCON.3
PLLCON.2
PLLCON.1
PLLCON.0
PSMCON Power Supply Monitor control register
IEIP2 Interrupt Enable/Priority register #2
ADC Gain
calibration coefficients
EADRL
0
TF1
ADC Data registers
ADCGAINH
ADCGAINL
WDCON
TSSOP
ADC Control register #3
busy indicator flag (0=ADC not active)
gain calibration disable bit (0=gain cal enabled)
number of averages selection bits
[15,1,31,63] averages
offset calibration disable bit (0=offset cal enabled)
(this bit must contain 1)
calibration type (0=offset cal, 1=gain cal)
start calibration bit, set to 1 to begin cal
ADCDATAL
0
IT1
ADCCON3.7
ADCCON3.6
ADCCON3.5
ADCCON3.4
ADCCON3.3
ADCCON3.2
ADCCON3.1
ADCCON3.0
01h
02h
04h
* calibration coefficients are preconfigured at power-up to factory calibrated values
TSSOP
ADCCON3
ECON
8Fh
T2
90h
1
T2EX
92h
93h
94h
95h
97h
1
96h
1
1
1
1
1
91h
RI
TI
RB8
9Ah
9Bh
0
TB8
REN
9Ch
0
9Dh
0
SM2
SM1
SM0
AFh
9Fh
0
9Eh
AAh
0
ABh
0
ACh
0
ADh
0
AEh
0
0
0
A9h
0
99h
0
98h
A8h
0
EX0
B0h
B1h
ET0
EX1
B2h
B3h
ET1
ES
B4h
B5h
1
B6h
ET2
EA
B7h
RD
1
WR
EADC
T1
1
T0
PS
1
INT1
1
INT0
1
TXD
1
RXD
PX0
B8h
0
PT0
B9h
0
BAh
WDWR
WDE
WDS
PX1
PT1
0
0
BEh
PT2
PSI
BFh
0
PADC
BDh
0
BCh
0
BBh
0
WDIR
PRE0
PRE1
PRE2
PRE3
C7h
0
C6h
0
C5h
0
C4h
0
C3h
CAh
C2h
0
C9h
C1h
0
C0h
0
CAP2
EXEN2
0
CCh
CDh
CEh
CFh
TF2
0
EXF2
0
RCLK
0
TCLK
0
CBh
TR2
0
CNT2
0
C8h
0
F1
OV
RS0
RS1
F0
AC
CY
D7h
0
D6h
0
D5h
0
D4h
0
D3h
0
D2h
0
D1h
0
D0h
P
0
0
CS0
E0h
D8h
0
0
CS1
D9h
E1h
0
0
CS2
DAh
E2h
0
0
CS3
DBh
E3h
0
0
DCh
E4h
0
0
DDh
E5h
0
0
DEh
E6h
ADCSPI CCONV SCONV
0
ADCI
DFh
0
E8h
E9h
EAh
EBh
0
0
0
F0h
0
F1h
0
E7h
0
SPR1
F9h
ADC Control register #2
ADC interrupt flag
enables ADC-to-SPI high-speed data capture mode
continuous conversion enable bit
single conversion start bit
input channel select bits:
0 - 5 = ADC0 - ADC5
8 = temperature sensor
9=DAC0, A=DAC1, B=AGND, C=VREF
PLLCON
these bits are contained in this byte
mnemonic
address
reset value
ADCI
ADCSPI
CCONV
SCONV
CS3
CS2
CS1
CS0
ADCDATAH
07h 82h
(reserved)
(reserved)
00h
00h 8Dh
TH1
TH0
TL1
00h 8Bh
00h 8Ch
(not used)
(not used)
(not used)
(not used)
(not used)
(reserved)
00h
(not used)
EDATA4
(reserved)
53h
(reserved)
D7h
DEh
PLLCON
PSMCON
DFh
00h
(reserved)
EFh
00h
ADCCON1
SPIDAT
F7h
(not used)
TL0
00h 8Ah
TMOD
00h 89h
TCON
88h
DAC0L
SPICON
SPR0
F8h
0
F9h
0
SPR1
lower RAM
details
0
R0
ECh
R1
00h
0
01h
0
EDh
1
0
R2
EEh
R3
02h
0
03h
2
EFh
3
00h
Register
Bank 0
D0EN
R4
D0
R5
04h
D1EN
05h
4
D1
5
F2h
R6
0
06h
F3h
6
128 bytes
lower RAM
(direct or
indirect
addressing)
0
R7
F4h
R0
07h
0
08h
7
F5h
8
0
R1
F6h
09h
0
9
SFRs
(direct
addressing
only)
F7h
R2
128 bytes
upper RAM
(indirect
addressing
only)
MAP KEY
0Ah
CPHA
10
FFh
FAh
R3
0
0Bh
CPOL
11
Register
Bank 1
FBh
R4
0
0Ch
SPIM
12
FCh
R5
0
0Dh
( page 0 )
SPE
13
00h
FDh
R6
0
R7
0Eh
WCOL
0Fh
14
FEh
15
0
R0
ISPI
10h
FFh
16
(not used)
R1
(not used)
11h
(not used)
17
FFh
R2
P1
12h
90h
18
ADC Control register #1
ADC mode (0=off, 1=on)
external Vref select bit (0=on-chip Vref)
conversion time = 16 / ADCclk
ADCclk = 16,777,216Hz / [8,4,16,32]
acquisition time select bits
acq time = [1,2,3,4] / ADCclk
Timer2 convert enable
external CONVST enable
ADCCON2
( page 159 )
640 bytes
(160 pages)
data
Flash/EE
(accessible
through
SFRs)
Register
Bank 2
1
R3
(not used)
R4
13h
(not used)
14h
19
04h
20
CFG814
R5
9Ch
15h
(reserved)
R6
21
(reserved)
R7
16h
00h
17h
22
SBUF
23
9Fh
00h 99h
R0
SCON
R1
18h
98h
19h
24
0
25
00h
R2
INTVAL
1Ah
00h A6h
26
HOUR
R3
00h A5h
1Bh
MIN
27
DATA MEMORY SPACE
(read/write area)
Register
Bank 3
00h A4h
R4
SEC
1Ch
00h A3h
28
HTHSEC
R5
00h A2h
R6
1Dh
TIMECON
1Eh
29
A1h
30
(not used)
00h
(reserved)
01h
(reserved)
02h
(reserved)
03h
(reserved)
04h
(reserved)
05h
A0h
06h
R7
IEIP2
07h
1Fh
00h A9h
20h
31
A8h
32
0
08h
FFh
09h
IE
0Ah
B0h
0Bh
1
0Ch
(reserved)
0Dh
(reserved)
0Eh
(reserved)
0Fh
(reserved)
21h
(reserved)
10h
33
(reserved)
18h
11g
P3
19h
12h
00h BFh
1Ah
13h
EDATA3
1Bh
14h
00h BEh
1Ch
15h
EDATA2
1Dh
16h
00h BDh
1Eh
17h
EDATA1
1Fh
22h
10h BCh
23h
34
ETIM2
35
20h BBh
20h
ETIM1
28h
21h
00h BAh
29h
22g
ECON
2Ah
23h
00h B9h
2Bh
24h
IP
2Ch
25h
B8h
2Dh
26h
0
2Eh
27h
00h
2Fh
24h
EADRL
25h
36
C6h
37
10h
30h
C0h
38h
31h
00h
39h
32h
(reserved)
3Ah
33h
00h CDh
3Bh
34h
(not used)
3Ch
35h
00h CCh
3Dh
36h
(reserved)
3Eh
37h
00h CBh
3Fh
26h
(reserved)
27h
38
CAh
39
(reserved)
40h
00h
41h
WDCON
42h
C8h
43h
0
44h
(reserved)
45h
TH2
46h
TL2
47h
RCAP2H
28h
RCAP2L
40
(reserved)
48h
00h
49h
T2CON
4Ah
D0h
4Bh
(reserved)
4Ch
(reserved)
4Dh
(reserved)
4Eh
(reserved)
4Fh
Bit Addressable
Area
(reserved)
29h
(reserved)
41
PSW
50h
(reserved)
51h
(reserved)
52h
(reserved)
53h
(reserved)
54h
00h
55h
00h DAh
56h
00h D9h
57h
D8h
2Ah
00h
58h
42
E0h
60h
59h
ADCCON2 ADCDATAL ADCDATAH
61h
5Ah
(reserved)
62h
5Bh
(reserved)
63h
5Ch
(reserved)
64h
5Dh
(reserved)
65h
5Eh
(reserved)
66h
5Fh
(reserved)
67h
2Bh
00h
2Ch
43
ACC
44
E8h
68h
(reserved)
69h
(reserved)
6Ah
(reserved)
6Bh
(reserved)
6Ch
(reserved)
6Dh
(reserved)
6Eh
DCON
6Fh
(reserved)
2Dh
00h
45
*20h F5h
70h
*00h F4h
71h
*20h F3h
72h
*00h F2h
73h
F0h
74h
0
75h
00h F1h
(reserved)
76h
(reserved)
77h
04h
2Eh
DACCON
46
00h FDh
78h
DAC1H
79h
00h FCh
7Ah
DAC1L
7Bh
00h FBh
7Ch
(bit addresses)
DAC0H
7Dh
00h FAh
7Eh
ADCOFSL ADCOFSH ADCGAINL ADCGAINH ADCCON3
7Fh
04h F9h
2Fh
B
30h
47
F8h
...
48
0
...
General Purpose
Area
LSB
address
7Fh
MSB
address
127
LOWER RAM
HEX
address
decimal
address
SFR MAP & RESET VALUES
ADCCON1.7
ADCCON1.6
ADCCON1.5
ADCCON1.4
ADCCON1.3
ADCCON1.2
ADCCON1.1
ADCCON1.0
Watchdog Timer control register
watchdog timeout selection bits
0-7=[15.6,31.2,62.5,125,250,500,1000,2000]ms
8=0ms (immediate reset)
>8=reserved
watchdog interrupt response bit
watchdog status flag (1 indicates watchdog timeout)
watchdog enable control (0=disabled)
watchdog write enable bit (set to enable write)
TSSOP
TSSOP
TSSOP
SM2
REN
TB8
RB8
TI
RI
SBUF
Serial port Buffer register
PCON Power Control register
PCON.7
PCON.6
PCON.5
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
double baud rate control
enable serial interrupt (ISI) from power-down mode
enable interrupt 0 (INT0) from power-down mode
ALE disable (0=normal, 1=forces ALE high)
general purpose flag
general purpose flag
power-down control bit (recoverable with hard reset)
idle-mode control (recoverable with enabled interrupt)
PSW
Program Status Word
CY
AC
F0
RS1
RS0
OV
F1
P
carry flag
auxiliary carry flag
general purpose flag 0
register bank select control bits
active register bank = [0,1,2,3]
overflow flag
general purpose flag 1
parity of ACC
DPH,DPL (DPTR)
Data Pointer
ACC
Accumulator
B
auxiliary math register
TSSOP
TSSOP
TSSOP