Course Project
 Next and final step: Project final presentation
 April 19: team 5-7
 April 21: team 1-4
 Everything in your project
 A final demo in class is required
 Project final report
 Due before the final exam
 Expected length: > 8 pages
 Provide all the necessary technical details of your system
design
ECE 351 Digital Systems Design
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Recap from the last class
 An important category of VHDL program is
implementation of counters
 Binary counter
 Ripple counter
 Shift register
 Ring/Johnson counters
 Implementing counters in VHDL
 Choices of using different packages
 Pros and cons
ECE 351 Digital Systems Design
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ECE 351
Digital Systems Design
Medium Scale Integrated Circuits - 3
Wei Gao
Spring 2016
3
Arithmetic Operations using MSI
 Adders
 Subtractors
 Multipliers
 Dividers
ECE 351 Digital Systems Design
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Addition – Half Adder
 One bit addition can be accomplished with an XOR gate
(modulo sum 2)
0
+0
0




1
+0
1
0
+1
1
1
+1
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Notice that we need to also generate a “Carry Out” bit
The “Carry Out” bit can be generated using an AND gate
This type of circuit is called a “Half Adder”
It is only “Half” because it doesn’t consider a “Carry In”
bit
ECE 351 Digital Systems Design
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Addition – Full Adder
 To create a full adder, we need to include the “Carry In”
in the Sum
Cin A B
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Cout
0
0
0
1
0
1
1
1
Sum
0
1
1
0
1
0
0
1
Sum = A ⊕ B ⊕ Cin
Cout = Cin∙A + A∙B + Cin∙B
 You could also use two "Half Adders" to accomplish the
same thing
ECE 351 Digital Systems Design
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Addition – Ripple Carry Adder
 Cascading full adders together will allow the Cout’s
to propagate through the circuit
 This configuration is called a Ripple Carry Adder
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Addition – Ripple Carry Adder
 What is the delay through the Full Adder?
 Each Full Adder has the following logic:
Sum = A ⊕ B ⊕ Cin
Cout = Cin∙A + A∙B + Cin∙B
 tFull-Adder will be the longest combinational logic delay path
in the adder
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Addition – Ripple Carry Adder
 What is the delay through the entire iterative circuit?
 tRCA = n·tFull-Adder
 The delay increases linearly with the number of bits
 Different topologies within the full-adder to reduce delay
(Δt) will have a n·Δt effect
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Subtraction – Half Subtractor
 One bit subtraction can be accomplished using
combinational logic
(A-B)
A
0
0
1
1
B
0
1
0
1
Bout
0
1
0
0
D
0
1
1
0
D =A⊕B
Bout = A'·B
 Output: same as addition
 Need to have the “borrow out” bit
ECE 351 Digital Systems Design
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Subtraction – Full Subtractor
 To create a full subtractor, we need to include the
“Borrow In” in the Difference
(A-B-Bin)
A B Bin
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Bout
0
1
1
1
0
0
0
1
D
0
1
1
0
1
0
0
1
D = A ⊕ B ⊕ Bin
Bout = A'∙B + A'∙Bin + B∙Bin
 Very similar to addition
 The Sum and Difference Logic are identical
 The Carry and Borrow Logic are close
ECE 351 Digital Systems Design
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Subtraction
 Can we manipulate the subtraction logic so that Full Adders
can be used as Full Subtractors?
Addition
S = A ⊕ B ⊕ Cin
Cout = A∙B + A∙Cin + B∙Cin
Subtraction
D = A ⊕ B ⊕ Bin
Bout = A'∙B + A'∙Bin + B∙Bin
 Let's manipulate Bout to get it into a form similar to Cout
Bout = A'∙B + A'∙Bin + B∙Bin
Bout' = (A+B') ∙ (A+Bin') ∙ (B'+Bin')
Generalized DeMorgan's Theorem
Bout' = (A∙A∙B')+(A∙B'∙Bin')+(A∙B'∙B')+(B'∙B'∙Bin')+(A∙A∙Bin')+(A∙Bin'∙Bin')+(A∙B'∙Bin')+(B'∙Bin'∙Bin')
Bout' = (A∙B')+(A∙B'∙Bin')+(A∙Bin')+(B'∙Bin')
Remove redundant items
Bout' = (A∙B')+(A∙Bin')+(B'∙Bin')
ECE 351 Digital Systems Design
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Subtraction
 But this requires the Subtrahend and Bin be inverted,
how does this effect the Sum/Difference Logic?
Addition
Subtraction
S = A ⊕ B ⊕ Cin
D = A ⊕ B ⊕ Bin
 Remember that both inputs of a 2-input XOR can be
inverted without changing the logic function which
gives us:
S = A ⊕ B ⊕ Cin
D = A ⊕ B' ⊕ Bin'
ECE 351 Digital Systems Design
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Subtraction
 After all of this manipulation, we are left with
Addition
Subtraction
S = A ⊕ B ⊕ Cin
Cout = A∙B + A∙Cin + B∙Cin
D = A ⊕ B' ⊕ Bin'
Bout' = A∙B' + A∙Bin' + B'∙Bin'
 This means we can use "Full Adders" for subtraction
as long as:
 The Subtrahend is inverted
 Bin is inverted
 Bout is inverted
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Ripple Carry Subtractor
 In a ripple carry subtractor, intermediate Bout's are
fed into Bin's, which is a double inversion
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Multipliers
 Binary multiplication of an individual bit can be performed
using combinational logic:
A*B
0 0
0 1
1 0
1 1
P
0
0
0
1
we can say that:
P = A·B
 For multi-bit multiplication, we can mimic the algorithm that
we use when doing multiplication by hand: “Shift & add”
ex)
12
x3 4
48
+36
408
this number is the "Multiplicand"
this number is the "Multiplier"
1) multiplicand for digit (0)
2) multiplicand for digit (1)
3) Sum of all multiplicands
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"Shift and Add" Multipliers
 Example of Binary Multiplication using our "by hand" method
11
x 13
33
11
+
1 4 3
1011
x
1101
1011
0000
1011
+1011
10001111
- multiplicand
- multiplier
- these are the individual multiplicands
- the final product is the sum of all multiplicands
 This is simple and straightforward. BUT, the addition of the
individual multiplicand products requires as many as n-inputs.
 We would really like to re-use our Full Adder circuits, which
only have 3 inputs.
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"Shift and Add" Multipliers
 We can perform the additions of each multiplicand after it is
created
 This is called a "Partial Product“
 To keep the algorithm consistent, we use "0000" as the first
Partial Product
1011
x
1101
0000
1011
1011
0000↓
01011
1011↓↓
110111
1011↓↓↓
10001111
- Original multiplicand
- Original multiplier
- Partial Product for 1st multiply
- Shifted Multiplicand for 1st multiply
- Partial Product for 2nd multiply
- Shifted Multiplicand for 2nd multiply
- Partial Product for 3rd multiply
- Shifted Multiplicand for 3rd multiply
- Partial Product for 4th multiply
- Shifted Multiplicand for 4th multiply
- the final product is the sum of all multiplicands
ECE 351 Digital Systems Design
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"Shift and Add" Multipliers
 Graphical view of product terms and summation
ECE 351 Digital Systems Design
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"Shift and Add" Multipliers
 Graphical View of interconnect for an 8x8 multiplier.
Note the Full Adders
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"Sequential" Multipliers
 The main speed limitation of the Combinational "Shift and
Add" multiplier is the delay through the adder chain.
 In the worst case, the number of delay paths through the
adders would be [n + 2(n-2)]
 ex)
4-bit
8-bit
= 8 Full Adders
= 20 Full Adders
 We can reduce this delay by using a register to accumulate
the incremental additions as they take place.
 This would reduce the number of operation states to [n-1]
ECE 351 Digital Systems Design
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Signed Multipliers
 One of the simplest ways is to first convert any
negative numbers to positive, then use the unsigned
multiplier
 The sign bit is added after the multiplication
following:
pos x pos = pos
pos x neg = neg
neg x pos = neg
neg x neg = pos
Remember 0=pos and 1=neg is 2's comp so this is an XOR
ECE 351 Digital Systems Design
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Division
 Division - "Repeated Subtraction“
 A simple algorithm to divide is to count the number of
times you can subtract the divisor from the dividend
 This is slow, but simple
 The number of times it can be subtracted without going
negative is the "Quotient“
 If the subtracted value results in a zero/negative number,
whatever was left prior to the subtraction is the
"Remainder"
ECE 351 Digital Systems Design
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Division
 Division - "Shift and Subtract"
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Summary
 Adders
 Half-adder
 Full-adder
 Ripple-carry adder
 Substractors
 Utilize the full adders
 Multipliers
 Shift-and-add
 Sequential multipliers
 Signed multipliers
 Divisions
ECE 351 Digital Systems Design
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